static_inst.hh revision 5865:54ed46881217
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "sim/faults.hh" 40#include "base/bitfield.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "cpu/op_class.hh" 45#include "sim/faults.hh" 46#include "sim/host.hh" 47 48// forward declarations 49struct AlphaSimpleImpl; 50struct OzoneImpl; 51struct SimpleImpl; 52class ThreadContext; 53class DynInst; 54class Packet; 55 56class O3CPUImpl; 57template <class Impl> class BaseO3DynInst; 58typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 59template <class Impl> class OzoneDynInst; 60class InOrderDynInst; 61 62class CheckerCPU; 63class FastCPU; 64class AtomicSimpleCPU; 65class TimingSimpleCPU; 66class InorderCPU; 67class SymbolTable; 68class AddrDecodePage; 69 70namespace Trace { 71 class InstRecord; 72} 73 74typedef uint16_t MicroPC; 75 76static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1); 77 78static inline MicroPC 79romMicroPC(MicroPC upc) 80{ 81 return upc | MicroPCRomBit; 82} 83 84static inline MicroPC 85normalMicroPC(MicroPC upc) 86{ 87 return upc & ~MicroPCRomBit; 88} 89 90static inline bool 91isRomMicroPC(MicroPC upc) 92{ 93 return MicroPCRomBit & upc; 94} 95 96/** 97 * Base, ISA-independent static instruction class. 98 * 99 * The main component of this class is the vector of flags and the 100 * associated methods for reading them. Any object that can rely 101 * solely on these flags can process instructions without being 102 * recompiled for multiple ISAs. 103 */ 104class StaticInstBase : public RefCounted 105{ 106 protected: 107 108 /// Set of boolean static instruction properties. 109 /// 110 /// Notes: 111 /// - The IsInteger and IsFloating flags are based on the class of 112 /// registers accessed by the instruction. Although most 113 /// instructions will have exactly one of these two flags set, it 114 /// is possible for an instruction to have neither (e.g., direct 115 /// unconditional branches, memory barriers) or both (e.g., an 116 /// FP/int conversion). 117 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 118 /// will be set. 119 /// - If IsControl is set, then exactly one of IsDirectControl or 120 /// IsIndirect Control will be set, and exactly one of 121 /// IsCondControl or IsUncondControl will be set. 122 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 123 /// implemented as flags since in the current model there's no 124 /// other way for instructions to inject behavior into the 125 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 126 /// model we should be able to get rid of these flags and 127 /// implement this behavior via the execute() methods. 128 /// 129 enum Flags { 130 IsNop, ///< Is a no-op (no effect at all). 131 132 IsInteger, ///< References integer regs. 133 IsFloating, ///< References FP regs. 134 135 IsMemRef, ///< References memory (load, store, or prefetch). 136 IsLoad, ///< Reads from memory (load or prefetch). 137 IsStore, ///< Writes to memory. 138 IsStoreConditional, ///< Store conditional instruction. 139 IsIndexed, ///< Accesses memory with an indexed address computation 140 IsInstPrefetch, ///< Instruction-cache prefetch. 141 IsDataPrefetch, ///< Data-cache prefetch. 142 IsCopy, ///< Fast Cache block copy 143 144 IsControl, ///< Control transfer instruction. 145 IsDirectControl, ///< PC relative control transfer. 146 IsIndirectControl, ///< Register indirect control transfer. 147 IsCondControl, ///< Conditional control transfer. 148 IsUncondControl, ///< Unconditional control transfer. 149 IsCall, ///< Subroutine call. 150 IsReturn, ///< Subroutine return. 151 152 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 153 154 IsThreadSync, ///< Thread synchronization operation. 155 156 IsSerializing, ///< Serializes pipeline: won't execute until all 157 /// older instructions have committed. 158 IsSerializeBefore, 159 IsSerializeAfter, 160 IsMemBarrier, ///< Is a memory barrier 161 IsWriteBarrier, ///< Is a write barrier 162 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 163 164 IsNonSpeculative, ///< Should not be executed speculatively 165 IsQuiesce, ///< Is a quiesce instruction 166 167 IsIprAccess, ///< Accesses IPRs 168 IsUnverifiable, ///< Can't be verified by a checker 169 170 IsSyscall, ///< Causes a system call to be emulated in syscall 171 /// emulation mode. 172 173 //Flags for microcode 174 IsMacroop, ///< Is a macroop containing microops 175 IsMicroop, ///< Is a microop 176 IsDelayedCommit, ///< This microop doesn't commit right away 177 IsLastMicroop, ///< This microop ends a microop sequence 178 IsFirstMicroop, ///< This microop begins a microop sequence 179 //This flag doesn't do anything yet 180 IsMicroBranch, ///< This microop branches within the microcode for a macroop 181 IsDspOp, 182 183 NumFlags 184 }; 185 186 /// Flag values for this instruction. 187 std::bitset<NumFlags> flags; 188 189 /// See opClass(). 190 OpClass _opClass; 191 192 /// See numSrcRegs(). 193 int8_t _numSrcRegs; 194 195 /// See numDestRegs(). 196 int8_t _numDestRegs; 197 198 /// The following are used to track physical register usage 199 /// for machines with separate int & FP reg files. 200 //@{ 201 int8_t _numFPDestRegs; 202 int8_t _numIntDestRegs; 203 //@} 204 205 /// Constructor. 206 /// It's important to initialize everything here to a sane 207 /// default, since the decoder generally only overrides 208 /// the fields that are meaningful for the particular 209 /// instruction. 210 StaticInstBase(OpClass __opClass) 211 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 212 _numFPDestRegs(0), _numIntDestRegs(0) 213 { 214 } 215 216 public: 217 218 /// @name Register information. 219 /// The sum of numFPDestRegs() and numIntDestRegs() equals 220 /// numDestRegs(). The former two functions are used to track 221 /// physical register usage for machines with separate int & FP 222 /// reg files. 223 //@{ 224 /// Number of source registers. 225 int8_t numSrcRegs() const { return _numSrcRegs; } 226 /// Number of destination registers. 227 int8_t numDestRegs() const { return _numDestRegs; } 228 /// Number of floating-point destination regs. 229 int8_t numFPDestRegs() const { return _numFPDestRegs; } 230 /// Number of integer destination regs. 231 int8_t numIntDestRegs() const { return _numIntDestRegs; } 232 //@} 233 234 /// @name Flag accessors. 235 /// These functions are used to access the values of the various 236 /// instruction property flags. See StaticInstBase::Flags for descriptions 237 /// of the individual flags. 238 //@{ 239 240 bool isNop() const { return flags[IsNop]; } 241 242 bool isMemRef() const { return flags[IsMemRef]; } 243 bool isLoad() const { return flags[IsLoad]; } 244 bool isStore() const { return flags[IsStore]; } 245 bool isStoreConditional() const { return flags[IsStoreConditional]; } 246 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 247 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 248 bool isCopy() const { return flags[IsCopy];} 249 250 bool isInteger() const { return flags[IsInteger]; } 251 bool isFloating() const { return flags[IsFloating]; } 252 253 bool isControl() const { return flags[IsControl]; } 254 bool isCall() const { return flags[IsCall]; } 255 bool isReturn() const { return flags[IsReturn]; } 256 bool isDirectCtrl() const { return flags[IsDirectControl]; } 257 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 258 bool isCondCtrl() const { return flags[IsCondControl]; } 259 bool isUncondCtrl() const { return flags[IsUncondControl]; } 260 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 261 262 bool isThreadSync() const { return flags[IsThreadSync]; } 263 bool isSerializing() const { return flags[IsSerializing] || 264 flags[IsSerializeBefore] || 265 flags[IsSerializeAfter]; } 266 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 267 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 268 bool isMemBarrier() const { return flags[IsMemBarrier]; } 269 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 270 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 271 bool isQuiesce() const { return flags[IsQuiesce]; } 272 bool isIprAccess() const { return flags[IsIprAccess]; } 273 bool isUnverifiable() const { return flags[IsUnverifiable]; } 274 bool isSyscall() const { return flags[IsSyscall]; } 275 bool isMacroop() const { return flags[IsMacroop]; } 276 bool isMicroop() const { return flags[IsMicroop]; } 277 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 278 bool isLastMicroop() const { return flags[IsLastMicroop]; } 279 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 280 //This flag doesn't do anything yet 281 bool isMicroBranch() const { return flags[IsMicroBranch]; } 282 //@} 283 284 void setLastMicroop() { flags[IsLastMicroop] = true; } 285 /// Operation class. Used to select appropriate function unit in issue. 286 OpClass opClass() const { return _opClass; } 287}; 288 289 290// forward declaration 291class StaticInstPtr; 292 293/** 294 * Generic yet ISA-dependent static instruction class. 295 * 296 * This class builds on StaticInstBase, defining fields and interfaces 297 * that are generic across all ISAs but that differ in details 298 * according to the specific ISA being used. 299 */ 300class StaticInst : public StaticInstBase 301{ 302 public: 303 304 /// Binary machine instruction type. 305 typedef TheISA::MachInst MachInst; 306 /// Binary extended machine instruction type. 307 typedef TheISA::ExtMachInst ExtMachInst; 308 /// Logical register index type. 309 typedef TheISA::RegIndex RegIndex; 310 311 enum { 312 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 313 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 314 }; 315 316 317 /// Return logical index (architectural reg num) of i'th destination reg. 318 /// Only the entries from 0 through numDestRegs()-1 are valid. 319 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 320 321 /// Return logical index (architectural reg num) of i'th source reg. 322 /// Only the entries from 0 through numSrcRegs()-1 are valid. 323 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 324 325 /// Pointer to a statically allocated "null" instruction object. 326 /// Used to give eaCompInst() and memAccInst() something to return 327 /// when called on non-memory instructions. 328 static StaticInstPtr nullStaticInstPtr; 329 330 /** 331 * Memory references only: returns "fake" instruction representing 332 * the effective address part of the memory operation. Used to 333 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 334 * just the EA computation. 335 */ 336 virtual const 337 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 338 339 /** 340 * Memory references only: returns "fake" instruction representing 341 * the memory access part of the memory operation. Used to 342 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 343 * just the memory access (not the EA computation). 344 */ 345 virtual const 346 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 347 348 /// The binary machine instruction. 349 const ExtMachInst machInst; 350 351 protected: 352 353 /// See destRegIdx(). 354 RegIndex _destRegIdx[MaxInstDestRegs]; 355 /// See srcRegIdx(). 356 RegIndex _srcRegIdx[MaxInstSrcRegs]; 357 358 /** 359 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 360 * methods. Also useful to readily identify instructions from 361 * within the debugger when #cachedDisassembly has not been 362 * initialized. 363 */ 364 const char *mnemonic; 365 366 /** 367 * String representation of disassembly (lazily evaluated via 368 * disassemble()). 369 */ 370 mutable std::string *cachedDisassembly; 371 372 /** 373 * Internal function to generate disassembly string. 374 */ 375 virtual std::string 376 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 377 378 /// Constructor. 379 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 380 : StaticInstBase(__opClass), 381 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 382 { } 383 384 public: 385 386 virtual ~StaticInst() 387 { 388 if (cachedDisassembly) 389 delete cachedDisassembly; 390 } 391 392/** 393 * The execute() signatures are auto-generated by scons based on the 394 * set of CPU models we are compiling in today. 395 */ 396#include "cpu/static_inst_exec_sigs.hh" 397 398 /** 399 * Return the microop that goes with a particular micropc. This should 400 * only be defined/used in macroops which will contain microops 401 */ 402 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 403 404 /** 405 * Return the target address for a PC-relative branch. 406 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 407 * should be true). 408 */ 409 virtual Addr branchTarget(Addr branchPC) const 410 { 411 panic("StaticInst::branchTarget() called on instruction " 412 "that is not a PC-relative branch."); 413 M5_DUMMY_RETURN 414 } 415 416 /** 417 * Return the target address for an indirect branch (jump). The 418 * register value is read from the supplied thread context, so 419 * the result is valid only if the thread context is about to 420 * execute the branch in question. Invalid if not an indirect 421 * branch (i.e. isIndirectCtrl() should be true). 422 */ 423 virtual Addr branchTarget(ThreadContext *tc) const 424 { 425 panic("StaticInst::branchTarget() called on instruction " 426 "that is not an indirect branch."); 427 M5_DUMMY_RETURN 428 } 429 430 /** 431 * Return true if the instruction is a control transfer, and if so, 432 * return the target address as well. 433 */ 434 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 435 436 virtual Request::Flags memAccFlags() 437 { 438 panic("StaticInst::memAccFlags called on non-memory instruction"); 439 return 0; 440 }; 441 442 /** 443 * Return string representation of disassembled instruction. 444 * The default version of this function will call the internal 445 * virtual generateDisassembly() function to get the string, 446 * then cache it in #cachedDisassembly. If the disassembly 447 * should not be cached, this function should be overridden directly. 448 */ 449 virtual const std::string &disassemble(Addr pc, 450 const SymbolTable *symtab = 0) const 451 { 452 if (!cachedDisassembly) 453 cachedDisassembly = 454 new std::string(generateDisassembly(pc, symtab)); 455 456 return *cachedDisassembly; 457 } 458 459 /// Decoded instruction cache type. 460 /// For now we're using a generic hash_map; this seems to work 461 /// pretty well. 462 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 463 464 /// A cache of decoded instruction objects. 465 static DecodeCache decodeCache; 466 467 /** 468 * Dump some basic stats on the decode cache hash map. 469 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 470 */ 471 static void dumpDecodeCacheStats(); 472 473 /// Decode a machine instruction. 474 /// @param mach_inst The binary instruction to decode. 475 /// @retval A pointer to the corresponding StaticInst object. 476 //This is defined as inlined below. 477 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 478 479 /// Return name of machine instruction 480 std::string getName() { return mnemonic; } 481 482 /// Decoded instruction cache type, for address decoding. 483 /// A generic hash_map is used. 484 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 485 486 /// A cache of decoded instruction objects from addresses. 487 static AddrDecodeCache addrDecodeCache; 488 489 struct cacheElement { 490 Addr page_addr; 491 AddrDecodePage *decodePage; 492 493 cacheElement() 494 :decodePage(NULL) { } 495 } ; 496 497 /// An array of recently decoded instructions. 498 // might not use an array if there is only two elements 499 static struct cacheElement recentDecodes[2]; 500 501 /// Updates the recently decoded instructions entries 502 /// @param page_addr The page address recently used. 503 /// @param decodePage Pointer to decoding page containing the decoded 504 /// instruction. 505 static inline void 506 updateCache(Addr page_addr, AddrDecodePage *decodePage) 507 { 508 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 509 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 510 recentDecodes[0].page_addr = page_addr; 511 recentDecodes[0].decodePage = decodePage; 512 } 513 514 /// Searches the decoded instruction cache for instruction decoding. 515 /// If it is not found, then we decode the instruction. 516 /// Otherwise, we get the instruction from the cache and move it into 517 /// the address-to-instruction decoding page. 518 /// @param mach_inst The binary instruction to decode. 519 /// @param addr The address that contained the binary instruction. 520 /// @param decodePage Pointer to decoding page containing the instruction. 521 /// @retval A pointer to the corresponding StaticInst object. 522 //This is defined as inlined below. 523 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 524 AddrDecodePage * decodePage); 525}; 526 527typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 528 529/// Reference-counted pointer to a StaticInst object. 530/// This type should be used instead of "StaticInst *" so that 531/// StaticInst objects can be properly reference-counted. 532class StaticInstPtr : public RefCountingPtr<StaticInst> 533{ 534 public: 535 /// Constructor. 536 StaticInstPtr() 537 : RefCountingPtr<StaticInst>() 538 { 539 } 540 541 /// Conversion from "StaticInst *". 542 StaticInstPtr(StaticInst *p) 543 : RefCountingPtr<StaticInst>(p) 544 { 545 } 546 547 /// Copy constructor. 548 StaticInstPtr(const StaticInstPtr &r) 549 : RefCountingPtr<StaticInst>(r) 550 { 551 } 552 553 /// Construct directly from machine instruction. 554 /// Calls StaticInst::decode(). 555 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 556 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 557 { 558 } 559 560 /// Convert to pointer to StaticInstBase class. 561 operator const StaticInstBasePtr() 562 { 563 return this->get(); 564 } 565}; 566 567/// A page of a list of decoded instructions from an address. 568class AddrDecodePage 569{ 570 typedef TheISA::ExtMachInst ExtMachInst; 571 protected: 572 StaticInstPtr instructions[TheISA::PageBytes]; 573 bool valid[TheISA::PageBytes]; 574 Addr lowerMask; 575 576 public: 577 /// Constructor 578 AddrDecodePage() { 579 lowerMask = TheISA::PageBytes - 1; 580 memset(valid, 0, TheISA::PageBytes); 581 } 582 583 /// Checks if the instruction is already decoded and the machine 584 /// instruction in the cache matches the current machine instruction 585 /// related to the address 586 /// @param mach_inst The binary instruction to check 587 /// @param addr The address containing the instruction 588 inline bool decoded(ExtMachInst mach_inst, Addr addr) 589 { 590 return (valid[addr & lowerMask] && 591 (instructions[addr & lowerMask]->machInst == mach_inst)); 592 } 593 594 /// Returns the instruction object. decoded should be called first 595 /// to check if the instruction is valid. 596 /// @param addr The address of the instruction. 597 /// @retval A pointer to the corresponding StaticInst object. 598 inline StaticInstPtr getInst(Addr addr) 599 { return instructions[addr & lowerMask]; } 600 601 /// Inserts a pointer to a StaticInst object into the list of decoded 602 /// instructions on the page. 603 /// @param addr The address of the instruction. 604 /// @param si A pointer to the corresponding StaticInst object. 605 inline void insert(Addr addr, StaticInstPtr &si) 606 { 607 instructions[addr & lowerMask] = si; 608 valid[addr & lowerMask] = true; 609 } 610 611}; 612 613 614inline StaticInstPtr 615StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 616{ 617#ifdef DECODE_CACHE_HASH_STATS 618 // Simple stats on decode hash_map. Turns out the default 619 // hash function is as good as anything I could come up with. 620 const int dump_every_n = 10000000; 621 static int decodes_til_dump = dump_every_n; 622 623 if (--decodes_til_dump == 0) { 624 dumpDecodeCacheStats(); 625 decodes_til_dump = dump_every_n; 626 } 627#endif 628 629 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 630 631 // checks recently decoded addresses 632 if (recentDecodes[0].decodePage && 633 page_addr == recentDecodes[0].page_addr) { 634 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 635 return recentDecodes[0].decodePage->getInst(addr); 636 637 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 638 } 639 640 if (recentDecodes[1].decodePage && 641 page_addr == recentDecodes[1].page_addr) { 642 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 643 return recentDecodes[1].decodePage->getInst(addr); 644 645 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 646 } 647 648 // searches the page containing the address to decode 649 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 650 if (iter != addrDecodeCache.end()) { 651 updateCache(page_addr, iter->second); 652 if (iter->second->decoded(mach_inst, addr)) 653 return iter->second->getInst(addr); 654 655 return searchCache(mach_inst, addr, iter->second); 656 } 657 658 // creates a new object for a page of decoded instructions 659 AddrDecodePage * decodePage = new AddrDecodePage; 660 addrDecodeCache[page_addr] = decodePage; 661 updateCache(page_addr, decodePage); 662 return searchCache(mach_inst, addr, decodePage); 663} 664 665inline StaticInstPtr 666StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 667 AddrDecodePage * decodePage) 668{ 669 DecodeCache::iterator iter = decodeCache.find(mach_inst); 670 if (iter != decodeCache.end()) { 671 decodePage->insert(addr, iter->second); 672 return iter->second; 673 } 674 675 StaticInstPtr si = TheISA::decodeInst(mach_inst); 676 decodePage->insert(addr, si); 677 decodeCache[mach_inst] = si; 678 return si; 679} 680 681#endif // __CPU_STATIC_INST_HH__ 682