static_inst.hh revision 5677:c8479d55206c
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "sim/faults.hh" 40#include "base/bitfield.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "cpu/op_class.hh" 45#include "sim/faults.hh" 46#include "sim/host.hh" 47 48// forward declarations 49struct AlphaSimpleImpl; 50struct OzoneImpl; 51struct SimpleImpl; 52class ThreadContext; 53class DynInst; 54class Packet; 55 56class O3CPUImpl; 57template <class Impl> class BaseO3DynInst; 58typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 59 60template <class Impl> 61class OzoneDynInst; 62 63class CheckerCPU; 64class FastCPU; 65class AtomicSimpleCPU; 66class TimingSimpleCPU; 67class InorderCPU; 68class SymbolTable; 69class AddrDecodePage; 70 71namespace Trace { 72 class InstRecord; 73} 74 75typedef uint16_t MicroPC; 76 77static const MicroPC MicroPCRomBit = 1 << (sizeof(MicroPC) * 8 - 1); 78 79static inline MicroPC 80romMicroPC(MicroPC upc) 81{ 82 return upc | MicroPCRomBit; 83} 84 85static inline MicroPC 86normalMicroPC(MicroPC upc) 87{ 88 return upc & ~MicroPCRomBit; 89} 90 91static inline bool 92isRomMicroPC(MicroPC upc) 93{ 94 return MicroPCRomBit & upc; 95} 96 97/** 98 * Base, ISA-independent static instruction class. 99 * 100 * The main component of this class is the vector of flags and the 101 * associated methods for reading them. Any object that can rely 102 * solely on these flags can process instructions without being 103 * recompiled for multiple ISAs. 104 */ 105class StaticInstBase : public RefCounted 106{ 107 protected: 108 109 /// Set of boolean static instruction properties. 110 /// 111 /// Notes: 112 /// - The IsInteger and IsFloating flags are based on the class of 113 /// registers accessed by the instruction. Although most 114 /// instructions will have exactly one of these two flags set, it 115 /// is possible for an instruction to have neither (e.g., direct 116 /// unconditional branches, memory barriers) or both (e.g., an 117 /// FP/int conversion). 118 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 119 /// will be set. 120 /// - If IsControl is set, then exactly one of IsDirectControl or 121 /// IsIndirect Control will be set, and exactly one of 122 /// IsCondControl or IsUncondControl will be set. 123 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 124 /// implemented as flags since in the current model there's no 125 /// other way for instructions to inject behavior into the 126 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 127 /// model we should be able to get rid of these flags and 128 /// implement this behavior via the execute() methods. 129 /// 130 enum Flags { 131 IsNop, ///< Is a no-op (no effect at all). 132 133 IsInteger, ///< References integer regs. 134 IsFloating, ///< References FP regs. 135 136 IsMemRef, ///< References memory (load, store, or prefetch). 137 IsLoad, ///< Reads from memory (load or prefetch). 138 IsStore, ///< Writes to memory. 139 IsStoreConditional, ///< Store conditional instruction. 140 IsIndexed, ///< Accesses memory with an indexed address computation 141 IsInstPrefetch, ///< Instruction-cache prefetch. 142 IsDataPrefetch, ///< Data-cache prefetch. 143 IsCopy, ///< Fast Cache block copy 144 145 IsControl, ///< Control transfer instruction. 146 IsDirectControl, ///< PC relative control transfer. 147 IsIndirectControl, ///< Register indirect control transfer. 148 IsCondControl, ///< Conditional control transfer. 149 IsUncondControl, ///< Unconditional control transfer. 150 IsCall, ///< Subroutine call. 151 IsReturn, ///< Subroutine return. 152 153 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 154 155 IsThreadSync, ///< Thread synchronization operation. 156 157 IsSerializing, ///< Serializes pipeline: won't execute until all 158 /// older instructions have committed. 159 IsSerializeBefore, 160 IsSerializeAfter, 161 IsMemBarrier, ///< Is a memory barrier 162 IsWriteBarrier, ///< Is a write barrier 163 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 164 165 IsNonSpeculative, ///< Should not be executed speculatively 166 IsQuiesce, ///< Is a quiesce instruction 167 168 IsIprAccess, ///< Accesses IPRs 169 IsUnverifiable, ///< Can't be verified by a checker 170 171 IsSyscall, ///< Causes a system call to be emulated in syscall 172 /// emulation mode. 173 174 //Flags for microcode 175 IsMacroop, ///< Is a macroop containing microops 176 IsMicroop, ///< Is a microop 177 IsDelayedCommit, ///< This microop doesn't commit right away 178 IsLastMicroop, ///< This microop ends a microop sequence 179 IsFirstMicroop, ///< This microop begins a microop sequence 180 //This flag doesn't do anything yet 181 IsMicroBranch, ///< This microop branches within the microcode for a macroop 182 IsDspOp, 183 184 NumFlags 185 }; 186 187 /// Flag values for this instruction. 188 std::bitset<NumFlags> flags; 189 190 /// See opClass(). 191 OpClass _opClass; 192 193 /// See numSrcRegs(). 194 int8_t _numSrcRegs; 195 196 /// See numDestRegs(). 197 int8_t _numDestRegs; 198 199 /// The following are used to track physical register usage 200 /// for machines with separate int & FP reg files. 201 //@{ 202 int8_t _numFPDestRegs; 203 int8_t _numIntDestRegs; 204 //@} 205 206 /// Constructor. 207 /// It's important to initialize everything here to a sane 208 /// default, since the decoder generally only overrides 209 /// the fields that are meaningful for the particular 210 /// instruction. 211 StaticInstBase(OpClass __opClass) 212 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 213 _numFPDestRegs(0), _numIntDestRegs(0) 214 { 215 } 216 217 public: 218 219 /// @name Register information. 220 /// The sum of numFPDestRegs() and numIntDestRegs() equals 221 /// numDestRegs(). The former two functions are used to track 222 /// physical register usage for machines with separate int & FP 223 /// reg files. 224 //@{ 225 /// Number of source registers. 226 int8_t numSrcRegs() const { return _numSrcRegs; } 227 /// Number of destination registers. 228 int8_t numDestRegs() const { return _numDestRegs; } 229 /// Number of floating-point destination regs. 230 int8_t numFPDestRegs() const { return _numFPDestRegs; } 231 /// Number of integer destination regs. 232 int8_t numIntDestRegs() const { return _numIntDestRegs; } 233 //@} 234 235 /// @name Flag accessors. 236 /// These functions are used to access the values of the various 237 /// instruction property flags. See StaticInstBase::Flags for descriptions 238 /// of the individual flags. 239 //@{ 240 241 bool isNop() const { return flags[IsNop]; } 242 243 bool isMemRef() const { return flags[IsMemRef]; } 244 bool isLoad() const { return flags[IsLoad]; } 245 bool isStore() const { return flags[IsStore]; } 246 bool isStoreConditional() const { return flags[IsStoreConditional]; } 247 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 248 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 249 bool isCopy() const { return flags[IsCopy];} 250 251 bool isInteger() const { return flags[IsInteger]; } 252 bool isFloating() const { return flags[IsFloating]; } 253 254 bool isControl() const { return flags[IsControl]; } 255 bool isCall() const { return flags[IsCall]; } 256 bool isReturn() const { return flags[IsReturn]; } 257 bool isDirectCtrl() const { return flags[IsDirectControl]; } 258 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 259 bool isCondCtrl() const { return flags[IsCondControl]; } 260 bool isUncondCtrl() const { return flags[IsUncondControl]; } 261 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 262 263 bool isThreadSync() const { return flags[IsThreadSync]; } 264 bool isSerializing() const { return flags[IsSerializing] || 265 flags[IsSerializeBefore] || 266 flags[IsSerializeAfter]; } 267 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 268 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 269 bool isMemBarrier() const { return flags[IsMemBarrier]; } 270 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 271 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 272 bool isQuiesce() const { return flags[IsQuiesce]; } 273 bool isIprAccess() const { return flags[IsIprAccess]; } 274 bool isUnverifiable() const { return flags[IsUnverifiable]; } 275 bool isSyscall() const { return flags[IsSyscall]; } 276 bool isMacroop() const { return flags[IsMacroop]; } 277 bool isMicroop() const { return flags[IsMicroop]; } 278 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 279 bool isLastMicroop() const { return flags[IsLastMicroop]; } 280 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 281 //This flag doesn't do anything yet 282 bool isMicroBranch() const { return flags[IsMicroBranch]; } 283 //@} 284 285 void setLastMicroop() { flags[IsLastMicroop] = true; } 286 /// Operation class. Used to select appropriate function unit in issue. 287 OpClass opClass() const { return _opClass; } 288}; 289 290 291// forward declaration 292class StaticInstPtr; 293 294/** 295 * Generic yet ISA-dependent static instruction class. 296 * 297 * This class builds on StaticInstBase, defining fields and interfaces 298 * that are generic across all ISAs but that differ in details 299 * according to the specific ISA being used. 300 */ 301class StaticInst : public StaticInstBase 302{ 303 public: 304 305 /// Binary machine instruction type. 306 typedef TheISA::MachInst MachInst; 307 /// Binary extended machine instruction type. 308 typedef TheISA::ExtMachInst ExtMachInst; 309 /// Logical register index type. 310 typedef TheISA::RegIndex RegIndex; 311 312 enum { 313 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 314 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 315 }; 316 317 318 /// Return logical index (architectural reg num) of i'th destination reg. 319 /// Only the entries from 0 through numDestRegs()-1 are valid. 320 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 321 322 /// Return logical index (architectural reg num) of i'th source reg. 323 /// Only the entries from 0 through numSrcRegs()-1 are valid. 324 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 325 326 /// Pointer to a statically allocated "null" instruction object. 327 /// Used to give eaCompInst() and memAccInst() something to return 328 /// when called on non-memory instructions. 329 static StaticInstPtr nullStaticInstPtr; 330 331 /** 332 * Memory references only: returns "fake" instruction representing 333 * the effective address part of the memory operation. Used to 334 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 335 * just the EA computation. 336 */ 337 virtual const 338 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 339 340 /** 341 * Memory references only: returns "fake" instruction representing 342 * the memory access part of the memory operation. Used to 343 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 344 * just the memory access (not the EA computation). 345 */ 346 virtual const 347 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 348 349 /// The binary machine instruction. 350 const ExtMachInst machInst; 351 352 protected: 353 354 /// See destRegIdx(). 355 RegIndex _destRegIdx[MaxInstDestRegs]; 356 /// See srcRegIdx(). 357 RegIndex _srcRegIdx[MaxInstSrcRegs]; 358 359 /** 360 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 361 * methods. Also useful to readily identify instructions from 362 * within the debugger when #cachedDisassembly has not been 363 * initialized. 364 */ 365 const char *mnemonic; 366 367 /** 368 * String representation of disassembly (lazily evaluated via 369 * disassemble()). 370 */ 371 mutable std::string *cachedDisassembly; 372 373 /** 374 * Internal function to generate disassembly string. 375 */ 376 virtual std::string 377 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 378 379 /// Constructor. 380 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 381 : StaticInstBase(__opClass), 382 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 383 { } 384 385 public: 386 387 virtual ~StaticInst() 388 { 389 if (cachedDisassembly) 390 delete cachedDisassembly; 391 } 392 393/** 394 * The execute() signatures are auto-generated by scons based on the 395 * set of CPU models we are compiling in today. 396 */ 397#include "cpu/static_inst_exec_sigs.hh" 398 399 /** 400 * Return the microop that goes with a particular micropc. This should 401 * only be defined/used in macroops which will contain microops 402 */ 403 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 404 405 /** 406 * Return the target address for a PC-relative branch. 407 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 408 * should be true). 409 */ 410 virtual Addr branchTarget(Addr branchPC) const 411 { 412 panic("StaticInst::branchTarget() called on instruction " 413 "that is not a PC-relative branch."); 414 M5_DUMMY_RETURN 415 } 416 417 /** 418 * Return the target address for an indirect branch (jump). The 419 * register value is read from the supplied thread context, so 420 * the result is valid only if the thread context is about to 421 * execute the branch in question. Invalid if not an indirect 422 * branch (i.e. isIndirectCtrl() should be true). 423 */ 424 virtual Addr branchTarget(ThreadContext *tc) const 425 { 426 panic("StaticInst::branchTarget() called on instruction " 427 "that is not an indirect branch."); 428 M5_DUMMY_RETURN 429 } 430 431 /** 432 * Return true if the instruction is a control transfer, and if so, 433 * return the target address as well. 434 */ 435 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 436 437 /** 438 * Return string representation of disassembled instruction. 439 * The default version of this function will call the internal 440 * virtual generateDisassembly() function to get the string, 441 * then cache it in #cachedDisassembly. If the disassembly 442 * should not be cached, this function should be overridden directly. 443 */ 444 virtual const std::string &disassemble(Addr pc, 445 const SymbolTable *symtab = 0) const 446 { 447 if (!cachedDisassembly) 448 cachedDisassembly = 449 new std::string(generateDisassembly(pc, symtab)); 450 451 return *cachedDisassembly; 452 } 453 454 /// Decoded instruction cache type. 455 /// For now we're using a generic hash_map; this seems to work 456 /// pretty well. 457 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 458 459 /// A cache of decoded instruction objects. 460 static DecodeCache decodeCache; 461 462 /** 463 * Dump some basic stats on the decode cache hash map. 464 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 465 */ 466 static void dumpDecodeCacheStats(); 467 468 /// Decode a machine instruction. 469 /// @param mach_inst The binary instruction to decode. 470 /// @retval A pointer to the corresponding StaticInst object. 471 //This is defined as inlined below. 472 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 473 474 /// Return name of machine instruction 475 std::string getName() { return mnemonic; } 476 477 /// Decoded instruction cache type, for address decoding. 478 /// A generic hash_map is used. 479 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 480 481 /// A cache of decoded instruction objects from addresses. 482 static AddrDecodeCache addrDecodeCache; 483 484 struct cacheElement { 485 Addr page_addr; 486 AddrDecodePage *decodePage; 487 488 cacheElement() 489 :decodePage(NULL) { } 490 } ; 491 492 /// An array of recently decoded instructions. 493 // might not use an array if there is only two elements 494 static struct cacheElement recentDecodes[2]; 495 496 /// Updates the recently decoded instructions entries 497 /// @param page_addr The page address recently used. 498 /// @param decodePage Pointer to decoding page containing the decoded 499 /// instruction. 500 static inline void 501 updateCache(Addr page_addr, AddrDecodePage *decodePage) 502 { 503 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 504 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 505 recentDecodes[0].page_addr = page_addr; 506 recentDecodes[0].decodePage = decodePage; 507 } 508 509 /// Searches the decoded instruction cache for instruction decoding. 510 /// If it is not found, then we decode the instruction. 511 /// Otherwise, we get the instruction from the cache and move it into 512 /// the address-to-instruction decoding page. 513 /// @param mach_inst The binary instruction to decode. 514 /// @param addr The address that contained the binary instruction. 515 /// @param decodePage Pointer to decoding page containing the instruction. 516 /// @retval A pointer to the corresponding StaticInst object. 517 //This is defined as inlined below. 518 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 519 AddrDecodePage * decodePage); 520}; 521 522typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 523 524/// Reference-counted pointer to a StaticInst object. 525/// This type should be used instead of "StaticInst *" so that 526/// StaticInst objects can be properly reference-counted. 527class StaticInstPtr : public RefCountingPtr<StaticInst> 528{ 529 public: 530 /// Constructor. 531 StaticInstPtr() 532 : RefCountingPtr<StaticInst>() 533 { 534 } 535 536 /// Conversion from "StaticInst *". 537 StaticInstPtr(StaticInst *p) 538 : RefCountingPtr<StaticInst>(p) 539 { 540 } 541 542 /// Copy constructor. 543 StaticInstPtr(const StaticInstPtr &r) 544 : RefCountingPtr<StaticInst>(r) 545 { 546 } 547 548 /// Construct directly from machine instruction. 549 /// Calls StaticInst::decode(). 550 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 551 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 552 { 553 } 554 555 /// Convert to pointer to StaticInstBase class. 556 operator const StaticInstBasePtr() 557 { 558 return this->get(); 559 } 560}; 561 562/// A page of a list of decoded instructions from an address. 563class AddrDecodePage 564{ 565 typedef TheISA::ExtMachInst ExtMachInst; 566 protected: 567 StaticInstPtr instructions[TheISA::PageBytes]; 568 bool valid[TheISA::PageBytes]; 569 Addr lowerMask; 570 571 public: 572 /// Constructor 573 AddrDecodePage() { 574 lowerMask = TheISA::PageBytes - 1; 575 memset(valid, 0, TheISA::PageBytes); 576 } 577 578 /// Checks if the instruction is already decoded and the machine 579 /// instruction in the cache matches the current machine instruction 580 /// related to the address 581 /// @param mach_inst The binary instruction to check 582 /// @param addr The address containing the instruction 583 inline bool decoded(ExtMachInst mach_inst, Addr addr) 584 { 585 return (valid[addr & lowerMask] && 586 (instructions[addr & lowerMask]->machInst == mach_inst)); 587 } 588 589 /// Returns the instruction object. decoded should be called first 590 /// to check if the instruction is valid. 591 /// @param addr The address of the instruction. 592 /// @retval A pointer to the corresponding StaticInst object. 593 inline StaticInstPtr getInst(Addr addr) 594 { return instructions[addr & lowerMask]; } 595 596 /// Inserts a pointer to a StaticInst object into the list of decoded 597 /// instructions on the page. 598 /// @param addr The address of the instruction. 599 /// @param si A pointer to the corresponding StaticInst object. 600 inline void insert(Addr addr, StaticInstPtr &si) 601 { 602 instructions[addr & lowerMask] = si; 603 valid[addr & lowerMask] = true; 604 } 605 606}; 607 608 609inline StaticInstPtr 610StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 611{ 612#ifdef DECODE_CACHE_HASH_STATS 613 // Simple stats on decode hash_map. Turns out the default 614 // hash function is as good as anything I could come up with. 615 const int dump_every_n = 10000000; 616 static int decodes_til_dump = dump_every_n; 617 618 if (--decodes_til_dump == 0) { 619 dumpDecodeCacheStats(); 620 decodes_til_dump = dump_every_n; 621 } 622#endif 623 624 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 625 626 // checks recently decoded addresses 627 if (recentDecodes[0].decodePage && 628 page_addr == recentDecodes[0].page_addr) { 629 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 630 return recentDecodes[0].decodePage->getInst(addr); 631 632 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 633 } 634 635 if (recentDecodes[1].decodePage && 636 page_addr == recentDecodes[1].page_addr) { 637 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 638 return recentDecodes[1].decodePage->getInst(addr); 639 640 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 641 } 642 643 // searches the page containing the address to decode 644 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 645 if (iter != addrDecodeCache.end()) { 646 updateCache(page_addr, iter->second); 647 if (iter->second->decoded(mach_inst, addr)) 648 return iter->second->getInst(addr); 649 650 return searchCache(mach_inst, addr, iter->second); 651 } 652 653 // creates a new object for a page of decoded instructions 654 AddrDecodePage * decodePage = new AddrDecodePage; 655 addrDecodeCache[page_addr] = decodePage; 656 updateCache(page_addr, decodePage); 657 return searchCache(mach_inst, addr, decodePage); 658} 659 660inline StaticInstPtr 661StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 662 AddrDecodePage * decodePage) 663{ 664 DecodeCache::iterator iter = decodeCache.find(mach_inst); 665 if (iter != decodeCache.end()) { 666 decodePage->insert(addr, iter->second); 667 return iter->second; 668 } 669 670 StaticInstPtr si = TheISA::decodeInst(mach_inst); 671 decodePage->insert(addr, si); 672 decodeCache[mach_inst] = si; 673 return si; 674} 675 676#endif // __CPU_STATIC_INST_HH__ 677