static_inst.hh revision 5597:e2983d751be4
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "sim/faults.hh" 40#include "base/bitfield.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "cpu/op_class.hh" 45#include "sim/faults.hh" 46#include "sim/host.hh" 47 48// forward declarations 49struct AlphaSimpleImpl; 50struct OzoneImpl; 51struct SimpleImpl; 52class ThreadContext; 53class DynInst; 54class Packet; 55 56class O3CPUImpl; 57template <class Impl> class BaseO3DynInst; 58typedef BaseO3DynInst<O3CPUImpl> O3DynInst; 59 60template <class Impl> 61class OzoneDynInst; 62 63class CheckerCPU; 64class FastCPU; 65class AtomicSimpleCPU; 66class TimingSimpleCPU; 67class InorderCPU; 68class SymbolTable; 69class AddrDecodePage; 70 71namespace Trace { 72 class InstRecord; 73} 74 75typedef uint32_t MicroPC; 76 77/** 78 * Base, ISA-independent static instruction class. 79 * 80 * The main component of this class is the vector of flags and the 81 * associated methods for reading them. Any object that can rely 82 * solely on these flags can process instructions without being 83 * recompiled for multiple ISAs. 84 */ 85class StaticInstBase : public RefCounted 86{ 87 protected: 88 89 /// Set of boolean static instruction properties. 90 /// 91 /// Notes: 92 /// - The IsInteger and IsFloating flags are based on the class of 93 /// registers accessed by the instruction. Although most 94 /// instructions will have exactly one of these two flags set, it 95 /// is possible for an instruction to have neither (e.g., direct 96 /// unconditional branches, memory barriers) or both (e.g., an 97 /// FP/int conversion). 98 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 99 /// will be set. 100 /// - If IsControl is set, then exactly one of IsDirectControl or 101 /// IsIndirect Control will be set, and exactly one of 102 /// IsCondControl or IsUncondControl will be set. 103 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 104 /// implemented as flags since in the current model there's no 105 /// other way for instructions to inject behavior into the 106 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 107 /// model we should be able to get rid of these flags and 108 /// implement this behavior via the execute() methods. 109 /// 110 enum Flags { 111 IsNop, ///< Is a no-op (no effect at all). 112 113 IsInteger, ///< References integer regs. 114 IsFloating, ///< References FP regs. 115 116 IsMemRef, ///< References memory (load, store, or prefetch). 117 IsLoad, ///< Reads from memory (load or prefetch). 118 IsStore, ///< Writes to memory. 119 IsStoreConditional, ///< Store conditional instruction. 120 IsIndexed, ///< Accesses memory with an indexed address computation 121 IsInstPrefetch, ///< Instruction-cache prefetch. 122 IsDataPrefetch, ///< Data-cache prefetch. 123 IsCopy, ///< Fast Cache block copy 124 125 IsControl, ///< Control transfer instruction. 126 IsDirectControl, ///< PC relative control transfer. 127 IsIndirectControl, ///< Register indirect control transfer. 128 IsCondControl, ///< Conditional control transfer. 129 IsUncondControl, ///< Unconditional control transfer. 130 IsCall, ///< Subroutine call. 131 IsReturn, ///< Subroutine return. 132 133 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 134 135 IsThreadSync, ///< Thread synchronization operation. 136 137 IsSerializing, ///< Serializes pipeline: won't execute until all 138 /// older instructions have committed. 139 IsSerializeBefore, 140 IsSerializeAfter, 141 IsMemBarrier, ///< Is a memory barrier 142 IsWriteBarrier, ///< Is a write barrier 143 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 144 145 IsNonSpeculative, ///< Should not be executed speculatively 146 IsQuiesce, ///< Is a quiesce instruction 147 148 IsIprAccess, ///< Accesses IPRs 149 IsUnverifiable, ///< Can't be verified by a checker 150 151 IsSyscall, ///< Causes a system call to be emulated in syscall 152 /// emulation mode. 153 154 //Flags for microcode 155 IsMacroop, ///< Is a macroop containing microops 156 IsMicroop, ///< Is a microop 157 IsDelayedCommit, ///< This microop doesn't commit right away 158 IsLastMicroop, ///< This microop ends a microop sequence 159 IsFirstMicroop, ///< This microop begins a microop sequence 160 //This flag doesn't do anything yet 161 IsMicroBranch, ///< This microop branches within the microcode for a macroop 162 IsDspOp, 163 164 NumFlags 165 }; 166 167 /// Flag values for this instruction. 168 std::bitset<NumFlags> flags; 169 170 /// See opClass(). 171 OpClass _opClass; 172 173 /// See numSrcRegs(). 174 int8_t _numSrcRegs; 175 176 /// See numDestRegs(). 177 int8_t _numDestRegs; 178 179 /// The following are used to track physical register usage 180 /// for machines with separate int & FP reg files. 181 //@{ 182 int8_t _numFPDestRegs; 183 int8_t _numIntDestRegs; 184 //@} 185 186 /// Constructor. 187 /// It's important to initialize everything here to a sane 188 /// default, since the decoder generally only overrides 189 /// the fields that are meaningful for the particular 190 /// instruction. 191 StaticInstBase(OpClass __opClass) 192 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 193 _numFPDestRegs(0), _numIntDestRegs(0) 194 { 195 } 196 197 public: 198 199 /// @name Register information. 200 /// The sum of numFPDestRegs() and numIntDestRegs() equals 201 /// numDestRegs(). The former two functions are used to track 202 /// physical register usage for machines with separate int & FP 203 /// reg files. 204 //@{ 205 /// Number of source registers. 206 int8_t numSrcRegs() const { return _numSrcRegs; } 207 /// Number of destination registers. 208 int8_t numDestRegs() const { return _numDestRegs; } 209 /// Number of floating-point destination regs. 210 int8_t numFPDestRegs() const { return _numFPDestRegs; } 211 /// Number of integer destination regs. 212 int8_t numIntDestRegs() const { return _numIntDestRegs; } 213 //@} 214 215 /// @name Flag accessors. 216 /// These functions are used to access the values of the various 217 /// instruction property flags. See StaticInstBase::Flags for descriptions 218 /// of the individual flags. 219 //@{ 220 221 bool isNop() const { return flags[IsNop]; } 222 223 bool isMemRef() const { return flags[IsMemRef]; } 224 bool isLoad() const { return flags[IsLoad]; } 225 bool isStore() const { return flags[IsStore]; } 226 bool isStoreConditional() const { return flags[IsStoreConditional]; } 227 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 228 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 229 bool isCopy() const { return flags[IsCopy];} 230 231 bool isInteger() const { return flags[IsInteger]; } 232 bool isFloating() const { return flags[IsFloating]; } 233 234 bool isControl() const { return flags[IsControl]; } 235 bool isCall() const { return flags[IsCall]; } 236 bool isReturn() const { return flags[IsReturn]; } 237 bool isDirectCtrl() const { return flags[IsDirectControl]; } 238 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 239 bool isCondCtrl() const { return flags[IsCondControl]; } 240 bool isUncondCtrl() const { return flags[IsUncondControl]; } 241 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 242 243 bool isThreadSync() const { return flags[IsThreadSync]; } 244 bool isSerializing() const { return flags[IsSerializing] || 245 flags[IsSerializeBefore] || 246 flags[IsSerializeAfter]; } 247 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 248 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 249 bool isMemBarrier() const { return flags[IsMemBarrier]; } 250 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 251 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 252 bool isQuiesce() const { return flags[IsQuiesce]; } 253 bool isIprAccess() const { return flags[IsIprAccess]; } 254 bool isUnverifiable() const { return flags[IsUnverifiable]; } 255 bool isSyscall() const { return flags[IsSyscall]; } 256 bool isMacroop() const { return flags[IsMacroop]; } 257 bool isMicroop() const { return flags[IsMicroop]; } 258 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 259 bool isLastMicroop() const { return flags[IsLastMicroop]; } 260 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 261 //This flag doesn't do anything yet 262 bool isMicroBranch() const { return flags[IsMicroBranch]; } 263 //@} 264 265 void setLastMicroop() { flags[IsLastMicroop] = true; } 266 /// Operation class. Used to select appropriate function unit in issue. 267 OpClass opClass() const { return _opClass; } 268}; 269 270 271// forward declaration 272class StaticInstPtr; 273 274/** 275 * Generic yet ISA-dependent static instruction class. 276 * 277 * This class builds on StaticInstBase, defining fields and interfaces 278 * that are generic across all ISAs but that differ in details 279 * according to the specific ISA being used. 280 */ 281class StaticInst : public StaticInstBase 282{ 283 public: 284 285 /// Binary machine instruction type. 286 typedef TheISA::MachInst MachInst; 287 /// Binary extended machine instruction type. 288 typedef TheISA::ExtMachInst ExtMachInst; 289 /// Logical register index type. 290 typedef TheISA::RegIndex RegIndex; 291 292 enum { 293 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 294 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 295 }; 296 297 298 /// Return logical index (architectural reg num) of i'th destination reg. 299 /// Only the entries from 0 through numDestRegs()-1 are valid. 300 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 301 302 /// Return logical index (architectural reg num) of i'th source reg. 303 /// Only the entries from 0 through numSrcRegs()-1 are valid. 304 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 305 306 /// Pointer to a statically allocated "null" instruction object. 307 /// Used to give eaCompInst() and memAccInst() something to return 308 /// when called on non-memory instructions. 309 static StaticInstPtr nullStaticInstPtr; 310 311 /** 312 * Memory references only: returns "fake" instruction representing 313 * the effective address part of the memory operation. Used to 314 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 315 * just the EA computation. 316 */ 317 virtual const 318 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 319 320 /** 321 * Memory references only: returns "fake" instruction representing 322 * the memory access part of the memory operation. Used to 323 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 324 * just the memory access (not the EA computation). 325 */ 326 virtual const 327 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 328 329 /// The binary machine instruction. 330 const ExtMachInst machInst; 331 332 protected: 333 334 /// See destRegIdx(). 335 RegIndex _destRegIdx[MaxInstDestRegs]; 336 /// See srcRegIdx(). 337 RegIndex _srcRegIdx[MaxInstSrcRegs]; 338 339 /** 340 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 341 * methods. Also useful to readily identify instructions from 342 * within the debugger when #cachedDisassembly has not been 343 * initialized. 344 */ 345 const char *mnemonic; 346 347 /** 348 * String representation of disassembly (lazily evaluated via 349 * disassemble()). 350 */ 351 mutable std::string *cachedDisassembly; 352 353 /** 354 * Internal function to generate disassembly string. 355 */ 356 virtual std::string 357 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 358 359 /// Constructor. 360 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 361 : StaticInstBase(__opClass), 362 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 363 { } 364 365 public: 366 367 virtual ~StaticInst() 368 { 369 if (cachedDisassembly) 370 delete cachedDisassembly; 371 } 372 373/** 374 * The execute() signatures are auto-generated by scons based on the 375 * set of CPU models we are compiling in today. 376 */ 377#include "cpu/static_inst_exec_sigs.hh" 378 379 /** 380 * Return the microop that goes with a particular micropc. This should 381 * only be defined/used in macroops which will contain microops 382 */ 383 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 384 385 /** 386 * Return the target address for a PC-relative branch. 387 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 388 * should be true). 389 */ 390 virtual Addr branchTarget(Addr branchPC) const 391 { 392 panic("StaticInst::branchTarget() called on instruction " 393 "that is not a PC-relative branch."); 394 M5_DUMMY_RETURN 395 } 396 397 /** 398 * Return the target address for an indirect branch (jump). The 399 * register value is read from the supplied thread context, so 400 * the result is valid only if the thread context is about to 401 * execute the branch in question. Invalid if not an indirect 402 * branch (i.e. isIndirectCtrl() should be true). 403 */ 404 virtual Addr branchTarget(ThreadContext *tc) const 405 { 406 panic("StaticInst::branchTarget() called on instruction " 407 "that is not an indirect branch."); 408 M5_DUMMY_RETURN 409 } 410 411 /** 412 * Return true if the instruction is a control transfer, and if so, 413 * return the target address as well. 414 */ 415 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 416 417 /** 418 * Return string representation of disassembled instruction. 419 * The default version of this function will call the internal 420 * virtual generateDisassembly() function to get the string, 421 * then cache it in #cachedDisassembly. If the disassembly 422 * should not be cached, this function should be overridden directly. 423 */ 424 virtual const std::string &disassemble(Addr pc, 425 const SymbolTable *symtab = 0) const 426 { 427 if (!cachedDisassembly) 428 cachedDisassembly = 429 new std::string(generateDisassembly(pc, symtab)); 430 431 return *cachedDisassembly; 432 } 433 434 /// Decoded instruction cache type. 435 /// For now we're using a generic hash_map; this seems to work 436 /// pretty well. 437 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 438 439 /// A cache of decoded instruction objects. 440 static DecodeCache decodeCache; 441 442 /** 443 * Dump some basic stats on the decode cache hash map. 444 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 445 */ 446 static void dumpDecodeCacheStats(); 447 448 /// Decode a machine instruction. 449 /// @param mach_inst The binary instruction to decode. 450 /// @retval A pointer to the corresponding StaticInst object. 451 //This is defined as inlined below. 452 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 453 454 /// Return name of machine instruction 455 std::string getName() { return mnemonic; } 456 457 /// Decoded instruction cache type, for address decoding. 458 /// A generic hash_map is used. 459 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 460 461 /// A cache of decoded instruction objects from addresses. 462 static AddrDecodeCache addrDecodeCache; 463 464 struct cacheElement { 465 Addr page_addr; 466 AddrDecodePage *decodePage; 467 468 cacheElement() 469 :decodePage(NULL) { } 470 } ; 471 472 /// An array of recently decoded instructions. 473 // might not use an array if there is only two elements 474 static struct cacheElement recentDecodes[2]; 475 476 /// Updates the recently decoded instructions entries 477 /// @param page_addr The page address recently used. 478 /// @param decodePage Pointer to decoding page containing the decoded 479 /// instruction. 480 static inline void 481 updateCache(Addr page_addr, AddrDecodePage *decodePage) 482 { 483 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 484 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 485 recentDecodes[0].page_addr = page_addr; 486 recentDecodes[0].decodePage = decodePage; 487 } 488 489 /// Searches the decoded instruction cache for instruction decoding. 490 /// If it is not found, then we decode the instruction. 491 /// Otherwise, we get the instruction from the cache and move it into 492 /// the address-to-instruction decoding page. 493 /// @param mach_inst The binary instruction to decode. 494 /// @param addr The address that contained the binary instruction. 495 /// @param decodePage Pointer to decoding page containing the instruction. 496 /// @retval A pointer to the corresponding StaticInst object. 497 //This is defined as inlined below. 498 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 499 AddrDecodePage * decodePage); 500}; 501 502typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 503 504/// Reference-counted pointer to a StaticInst object. 505/// This type should be used instead of "StaticInst *" so that 506/// StaticInst objects can be properly reference-counted. 507class StaticInstPtr : public RefCountingPtr<StaticInst> 508{ 509 public: 510 /// Constructor. 511 StaticInstPtr() 512 : RefCountingPtr<StaticInst>() 513 { 514 } 515 516 /// Conversion from "StaticInst *". 517 StaticInstPtr(StaticInst *p) 518 : RefCountingPtr<StaticInst>(p) 519 { 520 } 521 522 /// Copy constructor. 523 StaticInstPtr(const StaticInstPtr &r) 524 : RefCountingPtr<StaticInst>(r) 525 { 526 } 527 528 /// Construct directly from machine instruction. 529 /// Calls StaticInst::decode(). 530 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 531 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 532 { 533 } 534 535 /// Convert to pointer to StaticInstBase class. 536 operator const StaticInstBasePtr() 537 { 538 return this->get(); 539 } 540}; 541 542/// A page of a list of decoded instructions from an address. 543class AddrDecodePage 544{ 545 typedef TheISA::ExtMachInst ExtMachInst; 546 protected: 547 StaticInstPtr instructions[TheISA::PageBytes]; 548 bool valid[TheISA::PageBytes]; 549 Addr lowerMask; 550 551 public: 552 /// Constructor 553 AddrDecodePage() { 554 lowerMask = TheISA::PageBytes - 1; 555 memset(valid, 0, TheISA::PageBytes); 556 } 557 558 /// Checks if the instruction is already decoded and the machine 559 /// instruction in the cache matches the current machine instruction 560 /// related to the address 561 /// @param mach_inst The binary instruction to check 562 /// @param addr The address containing the instruction 563 inline bool decoded(ExtMachInst mach_inst, Addr addr) 564 { 565 return (valid[addr & lowerMask] && 566 (instructions[addr & lowerMask]->machInst == mach_inst)); 567 } 568 569 /// Returns the instruction object. decoded should be called first 570 /// to check if the instruction is valid. 571 /// @param addr The address of the instruction. 572 /// @retval A pointer to the corresponding StaticInst object. 573 inline StaticInstPtr getInst(Addr addr) 574 { return instructions[addr & lowerMask]; } 575 576 /// Inserts a pointer to a StaticInst object into the list of decoded 577 /// instructions on the page. 578 /// @param addr The address of the instruction. 579 /// @param si A pointer to the corresponding StaticInst object. 580 inline void insert(Addr addr, StaticInstPtr &si) 581 { 582 instructions[addr & lowerMask] = si; 583 valid[addr & lowerMask] = true; 584 } 585 586}; 587 588 589inline StaticInstPtr 590StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 591{ 592#ifdef DECODE_CACHE_HASH_STATS 593 // Simple stats on decode hash_map. Turns out the default 594 // hash function is as good as anything I could come up with. 595 const int dump_every_n = 10000000; 596 static int decodes_til_dump = dump_every_n; 597 598 if (--decodes_til_dump == 0) { 599 dumpDecodeCacheStats(); 600 decodes_til_dump = dump_every_n; 601 } 602#endif 603 604 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 605 606 // checks recently decoded addresses 607 if (recentDecodes[0].decodePage && 608 page_addr == recentDecodes[0].page_addr) { 609 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 610 return recentDecodes[0].decodePage->getInst(addr); 611 612 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 613 } 614 615 if (recentDecodes[1].decodePage && 616 page_addr == recentDecodes[1].page_addr) { 617 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 618 return recentDecodes[1].decodePage->getInst(addr); 619 620 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 621 } 622 623 // searches the page containing the address to decode 624 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 625 if (iter != addrDecodeCache.end()) { 626 updateCache(page_addr, iter->second); 627 if (iter->second->decoded(mach_inst, addr)) 628 return iter->second->getInst(addr); 629 630 return searchCache(mach_inst, addr, iter->second); 631 } 632 633 // creates a new object for a page of decoded instructions 634 AddrDecodePage * decodePage = new AddrDecodePage; 635 addrDecodeCache[page_addr] = decodePage; 636 updateCache(page_addr, decodePage); 637 return searchCache(mach_inst, addr, decodePage); 638} 639 640inline StaticInstPtr 641StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 642 AddrDecodePage * decodePage) 643{ 644 DecodeCache::iterator iter = decodeCache.find(mach_inst); 645 if (iter != decodeCache.end()) { 646 decodePage->insert(addr, iter->second); 647 return iter->second; 648 } 649 650 StaticInstPtr si = TheISA::decodeInst(mach_inst); 651 decodePage->insert(addr, si); 652 decodeCache[mach_inst] = si; 653 return si; 654} 655 656#endif // __CPU_STATIC_INST_HH__ 657