static_inst.hh revision 5222:bb733a878f85
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#ifndef __CPU_STATIC_INST_HH__ 32#define __CPU_STATIC_INST_HH__ 33 34#include <bitset> 35#include <string> 36 37#include "arch/isa_traits.hh" 38#include "arch/utility.hh" 39#include "sim/faults.hh" 40#include "base/bitfield.hh" 41#include "base/hashmap.hh" 42#include "base/misc.hh" 43#include "base/refcnt.hh" 44#include "cpu/op_class.hh" 45#include "cpu/o3/dyn_inst.hh" 46#include "sim/faults.hh" 47#include "sim/host.hh" 48 49// forward declarations 50struct AlphaSimpleImpl; 51struct OzoneImpl; 52struct SimpleImpl; 53class ThreadContext; 54class DynInst; 55class Packet; 56 57template <class Impl> 58class OzoneDynInst; 59 60class CheckerCPU; 61class FastCPU; 62class AtomicSimpleCPU; 63class TimingSimpleCPU; 64class InorderCPU; 65class SymbolTable; 66class AddrDecodePage; 67 68namespace Trace { 69 class InstRecord; 70} 71 72typedef uint32_t MicroPC; 73 74/** 75 * Base, ISA-independent static instruction class. 76 * 77 * The main component of this class is the vector of flags and the 78 * associated methods for reading them. Any object that can rely 79 * solely on these flags can process instructions without being 80 * recompiled for multiple ISAs. 81 */ 82class StaticInstBase : public RefCounted 83{ 84 protected: 85 86 /// Set of boolean static instruction properties. 87 /// 88 /// Notes: 89 /// - The IsInteger and IsFloating flags are based on the class of 90 /// registers accessed by the instruction. Although most 91 /// instructions will have exactly one of these two flags set, it 92 /// is possible for an instruction to have neither (e.g., direct 93 /// unconditional branches, memory barriers) or both (e.g., an 94 /// FP/int conversion). 95 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 96 /// will be set. 97 /// - If IsControl is set, then exactly one of IsDirectControl or 98 /// IsIndirect Control will be set, and exactly one of 99 /// IsCondControl or IsUncondControl will be set. 100 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 101 /// implemented as flags since in the current model there's no 102 /// other way for instructions to inject behavior into the 103 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 104 /// model we should be able to get rid of these flags and 105 /// implement this behavior via the execute() methods. 106 /// 107 enum Flags { 108 IsNop, ///< Is a no-op (no effect at all). 109 110 IsInteger, ///< References integer regs. 111 IsFloating, ///< References FP regs. 112 113 IsMemRef, ///< References memory (load, store, or prefetch). 114 IsLoad, ///< Reads from memory (load or prefetch). 115 IsStore, ///< Writes to memory. 116 IsStoreConditional, ///< Store conditional instruction. 117 IsIndexed, ///< Accesses memory with an indexed address computation 118 IsInstPrefetch, ///< Instruction-cache prefetch. 119 IsDataPrefetch, ///< Data-cache prefetch. 120 IsCopy, ///< Fast Cache block copy 121 122 IsControl, ///< Control transfer instruction. 123 IsDirectControl, ///< PC relative control transfer. 124 IsIndirectControl, ///< Register indirect control transfer. 125 IsCondControl, ///< Conditional control transfer. 126 IsUncondControl, ///< Unconditional control transfer. 127 IsCall, ///< Subroutine call. 128 IsReturn, ///< Subroutine return. 129 130 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 131 132 IsThreadSync, ///< Thread synchronization operation. 133 134 IsSerializing, ///< Serializes pipeline: won't execute until all 135 /// older instructions have committed. 136 IsSerializeBefore, 137 IsSerializeAfter, 138 IsMemBarrier, ///< Is a memory barrier 139 IsWriteBarrier, ///< Is a write barrier 140 IsERET, /// <- Causes the IFU to stall (MIPS ISA) 141 142 IsNonSpeculative, ///< Should not be executed speculatively 143 IsQuiesce, ///< Is a quiesce instruction 144 145 IsIprAccess, ///< Accesses IPRs 146 IsUnverifiable, ///< Can't be verified by a checker 147 148 IsSyscall, ///< Causes a system call to be emulated in syscall 149 /// emulation mode. 150 151 //Flags for microcode 152 IsMacroop, ///< Is a macroop containing microops 153 IsMicroop, ///< Is a microop 154 IsDelayedCommit, ///< This microop doesn't commit right away 155 IsLastMicroop, ///< This microop ends a microop sequence 156 IsFirstMicroop, ///< This microop begins a microop sequence 157 //This flag doesn't do anything yet 158 IsMicroBranch, ///< This microop branches within the microcode for a macroop 159 IsDspOp, 160 161 NumFlags 162 }; 163 164 /// Flag values for this instruction. 165 std::bitset<NumFlags> flags; 166 167 /// See opClass(). 168 OpClass _opClass; 169 170 /// See numSrcRegs(). 171 int8_t _numSrcRegs; 172 173 /// See numDestRegs(). 174 int8_t _numDestRegs; 175 176 /// The following are used to track physical register usage 177 /// for machines with separate int & FP reg files. 178 //@{ 179 int8_t _numFPDestRegs; 180 int8_t _numIntDestRegs; 181 //@} 182 183 /// Constructor. 184 /// It's important to initialize everything here to a sane 185 /// default, since the decoder generally only overrides 186 /// the fields that are meaningful for the particular 187 /// instruction. 188 StaticInstBase(OpClass __opClass) 189 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 190 _numFPDestRegs(0), _numIntDestRegs(0) 191 { 192 } 193 194 public: 195 196 /// @name Register information. 197 /// The sum of numFPDestRegs() and numIntDestRegs() equals 198 /// numDestRegs(). The former two functions are used to track 199 /// physical register usage for machines with separate int & FP 200 /// reg files. 201 //@{ 202 /// Number of source registers. 203 int8_t numSrcRegs() const { return _numSrcRegs; } 204 /// Number of destination registers. 205 int8_t numDestRegs() const { return _numDestRegs; } 206 /// Number of floating-point destination regs. 207 int8_t numFPDestRegs() const { return _numFPDestRegs; } 208 /// Number of integer destination regs. 209 int8_t numIntDestRegs() const { return _numIntDestRegs; } 210 //@} 211 212 /// @name Flag accessors. 213 /// These functions are used to access the values of the various 214 /// instruction property flags. See StaticInstBase::Flags for descriptions 215 /// of the individual flags. 216 //@{ 217 218 bool isNop() const { return flags[IsNop]; } 219 220 bool isMemRef() const { return flags[IsMemRef]; } 221 bool isLoad() const { return flags[IsLoad]; } 222 bool isStore() const { return flags[IsStore]; } 223 bool isStoreConditional() const { return flags[IsStoreConditional]; } 224 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 225 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 226 bool isCopy() const { return flags[IsCopy];} 227 228 bool isInteger() const { return flags[IsInteger]; } 229 bool isFloating() const { return flags[IsFloating]; } 230 231 bool isControl() const { return flags[IsControl]; } 232 bool isCall() const { return flags[IsCall]; } 233 bool isReturn() const { return flags[IsReturn]; } 234 bool isDirectCtrl() const { return flags[IsDirectControl]; } 235 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 236 bool isCondCtrl() const { return flags[IsCondControl]; } 237 bool isUncondCtrl() const { return flags[IsUncondControl]; } 238 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 239 240 bool isThreadSync() const { return flags[IsThreadSync]; } 241 bool isSerializing() const { return flags[IsSerializing] || 242 flags[IsSerializeBefore] || 243 flags[IsSerializeAfter]; } 244 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 245 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 246 bool isMemBarrier() const { return flags[IsMemBarrier]; } 247 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 248 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 249 bool isQuiesce() const { return flags[IsQuiesce]; } 250 bool isIprAccess() const { return flags[IsIprAccess]; } 251 bool isUnverifiable() const { return flags[IsUnverifiable]; } 252 bool isSyscall() const { return flags[IsSyscall]; } 253 bool isMacroop() const { return flags[IsMacroop]; } 254 bool isMicroop() const { return flags[IsMicroop]; } 255 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 256 bool isLastMicroop() const { return flags[IsLastMicroop]; } 257 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 258 //This flag doesn't do anything yet 259 bool isMicroBranch() const { return flags[IsMicroBranch]; } 260 //@} 261 262 /// Operation class. Used to select appropriate function unit in issue. 263 OpClass opClass() const { return _opClass; } 264}; 265 266 267// forward declaration 268class StaticInstPtr; 269 270/** 271 * Generic yet ISA-dependent static instruction class. 272 * 273 * This class builds on StaticInstBase, defining fields and interfaces 274 * that are generic across all ISAs but that differ in details 275 * according to the specific ISA being used. 276 */ 277class StaticInst : public StaticInstBase 278{ 279 public: 280 281 /// Binary machine instruction type. 282 typedef TheISA::MachInst MachInst; 283 /// Binary extended machine instruction type. 284 typedef TheISA::ExtMachInst ExtMachInst; 285 /// Logical register index type. 286 typedef TheISA::RegIndex RegIndex; 287 288 enum { 289 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 290 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 291 }; 292 293 294 /// Return logical index (architectural reg num) of i'th destination reg. 295 /// Only the entries from 0 through numDestRegs()-1 are valid. 296 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 297 298 /// Return logical index (architectural reg num) of i'th source reg. 299 /// Only the entries from 0 through numSrcRegs()-1 are valid. 300 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 301 302 /// Pointer to a statically allocated "null" instruction object. 303 /// Used to give eaCompInst() and memAccInst() something to return 304 /// when called on non-memory instructions. 305 static StaticInstPtr nullStaticInstPtr; 306 307 /** 308 * Memory references only: returns "fake" instruction representing 309 * the effective address part of the memory operation. Used to 310 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 311 * just the EA computation. 312 */ 313 virtual const 314 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 315 316 /** 317 * Memory references only: returns "fake" instruction representing 318 * the memory access part of the memory operation. Used to 319 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 320 * just the memory access (not the EA computation). 321 */ 322 virtual const 323 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 324 325 /// The binary machine instruction. 326 const ExtMachInst machInst; 327 328 protected: 329 330 /// See destRegIdx(). 331 RegIndex _destRegIdx[MaxInstDestRegs]; 332 /// See srcRegIdx(). 333 RegIndex _srcRegIdx[MaxInstSrcRegs]; 334 335 /** 336 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 337 * methods. Also useful to readily identify instructions from 338 * within the debugger when #cachedDisassembly has not been 339 * initialized. 340 */ 341 const char *mnemonic; 342 343 /** 344 * String representation of disassembly (lazily evaluated via 345 * disassemble()). 346 */ 347 mutable std::string *cachedDisassembly; 348 349 /** 350 * Internal function to generate disassembly string. 351 */ 352 virtual std::string 353 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 354 355 /// Constructor. 356 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 357 : StaticInstBase(__opClass), 358 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 359 { } 360 361 public: 362 363 virtual ~StaticInst() 364 { 365 if (cachedDisassembly) 366 delete cachedDisassembly; 367 } 368 369/** 370 * The execute() signatures are auto-generated by scons based on the 371 * set of CPU models we are compiling in today. 372 */ 373#include "cpu/static_inst_exec_sigs.hh" 374 375 /** 376 * Return the microop that goes with a particular micropc. This should 377 * only be defined/used in macroops which will contain microops 378 */ 379 virtual StaticInstPtr fetchMicroop(MicroPC micropc); 380 381 /** 382 * Return the target address for a PC-relative branch. 383 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 384 * should be true). 385 */ 386 virtual Addr branchTarget(Addr branchPC) const 387 { 388 panic("StaticInst::branchTarget() called on instruction " 389 "that is not a PC-relative branch."); 390 M5_DUMMY_RETURN 391 } 392 393 /** 394 * Return the target address for an indirect branch (jump). The 395 * register value is read from the supplied thread context, so 396 * the result is valid only if the thread context is about to 397 * execute the branch in question. Invalid if not an indirect 398 * branch (i.e. isIndirectCtrl() should be true). 399 */ 400 virtual Addr branchTarget(ThreadContext *tc) const 401 { 402 panic("StaticInst::branchTarget() called on instruction " 403 "that is not an indirect branch."); 404 M5_DUMMY_RETURN 405 } 406 407 /** 408 * Return true if the instruction is a control transfer, and if so, 409 * return the target address as well. 410 */ 411 bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; 412 413 /** 414 * Return string representation of disassembled instruction. 415 * The default version of this function will call the internal 416 * virtual generateDisassembly() function to get the string, 417 * then cache it in #cachedDisassembly. If the disassembly 418 * should not be cached, this function should be overridden directly. 419 */ 420 virtual const std::string &disassemble(Addr pc, 421 const SymbolTable *symtab = 0) const 422 { 423 if (!cachedDisassembly) 424 cachedDisassembly = 425 new std::string(generateDisassembly(pc, symtab)); 426 427 return *cachedDisassembly; 428 } 429 430 /// Decoded instruction cache type. 431 /// For now we're using a generic hash_map; this seems to work 432 /// pretty well. 433 typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 434 435 /// A cache of decoded instruction objects. 436 static DecodeCache decodeCache; 437 438 /** 439 * Dump some basic stats on the decode cache hash map. 440 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 441 */ 442 static void dumpDecodeCacheStats(); 443 444 /// Decode a machine instruction. 445 /// @param mach_inst The binary instruction to decode. 446 /// @retval A pointer to the corresponding StaticInst object. 447 //This is defined as inlined below. 448 static StaticInstPtr decode(ExtMachInst mach_inst, Addr addr); 449 450 /// Return name of machine instruction 451 std::string getName() { return mnemonic; } 452 453 /// Decoded instruction cache type, for address decoding. 454 /// A generic hash_map is used. 455 typedef m5::hash_map<Addr, AddrDecodePage *> AddrDecodeCache; 456 457 /// A cache of decoded instruction objects from addresses. 458 static AddrDecodeCache addrDecodeCache; 459 460 struct cacheElement { 461 Addr page_addr; 462 AddrDecodePage *decodePage; 463 464 cacheElement() 465 :decodePage(NULL) { } 466 } ; 467 468 /// An array of recently decoded instructions. 469 // might not use an array if there is only two elements 470 static struct cacheElement recentDecodes[2]; 471 472 /// Updates the recently decoded instructions entries 473 /// @param page_addr The page address recently used. 474 /// @param decodePage Pointer to decoding page containing the decoded 475 /// instruction. 476 static inline void 477 updateCache(Addr page_addr, AddrDecodePage *decodePage) 478 { 479 recentDecodes[1].page_addr = recentDecodes[0].page_addr; 480 recentDecodes[1].decodePage = recentDecodes[0].decodePage; 481 recentDecodes[0].page_addr = page_addr; 482 recentDecodes[0].decodePage = decodePage; 483 } 484 485 /// Searches the decoded instruction cache for instruction decoding. 486 /// If it is not found, then we decode the instruction. 487 /// Otherwise, we get the instruction from the cache and move it into 488 /// the address-to-instruction decoding page. 489 /// @param mach_inst The binary instruction to decode. 490 /// @param addr The address that contained the binary instruction. 491 /// @param decodePage Pointer to decoding page containing the instruction. 492 /// @retval A pointer to the corresponding StaticInst object. 493 //This is defined as inlined below. 494 static StaticInstPtr searchCache(ExtMachInst mach_inst, Addr addr, 495 AddrDecodePage * decodePage); 496}; 497 498typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 499 500/// Reference-counted pointer to a StaticInst object. 501/// This type should be used instead of "StaticInst *" so that 502/// StaticInst objects can be properly reference-counted. 503class StaticInstPtr : public RefCountingPtr<StaticInst> 504{ 505 public: 506 /// Constructor. 507 StaticInstPtr() 508 : RefCountingPtr<StaticInst>() 509 { 510 } 511 512 /// Conversion from "StaticInst *". 513 StaticInstPtr(StaticInst *p) 514 : RefCountingPtr<StaticInst>(p) 515 { 516 } 517 518 /// Copy constructor. 519 StaticInstPtr(const StaticInstPtr &r) 520 : RefCountingPtr<StaticInst>(r) 521 { 522 } 523 524 /// Construct directly from machine instruction. 525 /// Calls StaticInst::decode(). 526 explicit StaticInstPtr(TheISA::ExtMachInst mach_inst, Addr addr) 527 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst, addr)) 528 { 529 } 530 531 /// Convert to pointer to StaticInstBase class. 532 operator const StaticInstBasePtr() 533 { 534 return this->get(); 535 } 536}; 537 538/// A page of a list of decoded instructions from an address. 539class AddrDecodePage 540{ 541 typedef TheISA::ExtMachInst ExtMachInst; 542 protected: 543 StaticInstPtr instructions[TheISA::PageBytes]; 544 bool valid[TheISA::PageBytes]; 545 Addr lowerMask; 546 547 public: 548 /// Constructor 549 AddrDecodePage() { 550 lowerMask = TheISA::PageBytes - 1; 551 memset(valid, 0, TheISA::PageBytes); 552 } 553 554 /// Checks if the instruction is already decoded and the machine 555 /// instruction in the cache matches the current machine instruction 556 /// related to the address 557 /// @param mach_inst The binary instruction to check 558 /// @param addr The address containing the instruction 559 inline bool decoded(ExtMachInst mach_inst, Addr addr) 560 { 561 return (valid[addr & lowerMask] && 562 (instructions[addr & lowerMask]->machInst == mach_inst)); 563 } 564 565 /// Returns the instruction object. decoded should be called first 566 /// to check if the instruction is valid. 567 /// @param addr The address of the instruction. 568 /// @retval A pointer to the corresponding StaticInst object. 569 inline StaticInstPtr getInst(Addr addr) 570 { return instructions[addr & lowerMask]; } 571 572 /// Inserts a pointer to a StaticInst object into the list of decoded 573 /// instructions on the page. 574 /// @param addr The address of the instruction. 575 /// @param si A pointer to the corresponding StaticInst object. 576 inline void insert(Addr addr, StaticInstPtr &si) 577 { 578 instructions[addr & lowerMask] = si; 579 valid[addr & lowerMask] = true; 580 } 581 582}; 583 584 585inline StaticInstPtr 586StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr) 587{ 588#ifdef DECODE_CACHE_HASH_STATS 589 // Simple stats on decode hash_map. Turns out the default 590 // hash function is as good as anything I could come up with. 591 const int dump_every_n = 10000000; 592 static int decodes_til_dump = dump_every_n; 593 594 if (--decodes_til_dump == 0) { 595 dumpDecodeCacheStats(); 596 decodes_til_dump = dump_every_n; 597 } 598#endif 599 600 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 601 602 // checks recently decoded addresses 603 if (recentDecodes[0].decodePage && 604 page_addr == recentDecodes[0].page_addr) { 605 if (recentDecodes[0].decodePage->decoded(mach_inst, addr)) 606 return recentDecodes[0].decodePage->getInst(addr); 607 608 return searchCache(mach_inst, addr, recentDecodes[0].decodePage); 609 } 610 611 if (recentDecodes[1].decodePage && 612 page_addr == recentDecodes[1].page_addr) { 613 if (recentDecodes[1].decodePage->decoded(mach_inst, addr)) 614 return recentDecodes[1].decodePage->getInst(addr); 615 616 return searchCache(mach_inst, addr, recentDecodes[1].decodePage); 617 } 618 619 // searches the page containing the address to decode 620 AddrDecodeCache::iterator iter = addrDecodeCache.find(page_addr); 621 if (iter != addrDecodeCache.end()) { 622 updateCache(page_addr, iter->second); 623 if (iter->second->decoded(mach_inst, addr)) 624 return iter->second->getInst(addr); 625 626 return searchCache(mach_inst, addr, iter->second); 627 } 628 629 // creates a new object for a page of decoded instructions 630 AddrDecodePage * decodePage = new AddrDecodePage; 631 addrDecodeCache[page_addr] = decodePage; 632 updateCache(page_addr, decodePage); 633 return searchCache(mach_inst, addr, decodePage); 634} 635 636inline StaticInstPtr 637StaticInst::searchCache(ExtMachInst mach_inst, Addr addr, 638 AddrDecodePage * decodePage) 639{ 640 DecodeCache::iterator iter = decodeCache.find(mach_inst); 641 if (iter != decodeCache.end()) { 642 decodePage->insert(addr, iter->second); 643 return iter->second; 644 } 645 646 StaticInstPtr si = TheISA::decodeInst(mach_inst); 647 decodePage->insert(addr, si); 648 decodeCache[mach_inst] = si; 649 return si; 650} 651 652#endif // __CPU_STATIC_INST_HH__ 653