static_inst.hh revision 3271:4a871cbe6d84 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "arch/isa_traits.hh"
38#include "sim/faults.hh"
39#include "base/bitfield.hh"
40#include "base/hashmap.hh"
41#include "base/misc.hh"
42#include "base/refcnt.hh"
43#include "cpu/op_class.hh"
44#include "cpu/o3/dyn_inst.hh"
45#include "sim/faults.hh"
46#include "sim/host.hh"
47
48// forward declarations
49struct AlphaSimpleImpl;
50struct OzoneImpl;
51struct SimpleImpl;
52class ThreadContext;
53class DynInst;
54class Packet;
55
56template <class Impl>
57class OzoneDynInst;
58
59class CheckerCPU;
60class FastCPU;
61class AtomicSimpleCPU;
62class TimingSimpleCPU;
63class InorderCPU;
64class SymbolTable;
65
66namespace Trace {
67    class InstRecord;
68}
69
70typedef uint32_t MicroPC;
71
72/**
73 * Base, ISA-independent static instruction class.
74 *
75 * The main component of this class is the vector of flags and the
76 * associated methods for reading them.  Any object that can rely
77 * solely on these flags can process instructions without being
78 * recompiled for multiple ISAs.
79 */
80class StaticInstBase : public RefCounted
81{
82  protected:
83
84    /// Set of boolean static instruction properties.
85    ///
86    /// Notes:
87    /// - The IsInteger and IsFloating flags are based on the class of
88    /// registers accessed by the instruction.  Although most
89    /// instructions will have exactly one of these two flags set, it
90    /// is possible for an instruction to have neither (e.g., direct
91    /// unconditional branches, memory barriers) or both (e.g., an
92    /// FP/int conversion).
93    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
94    /// will be set.
95    /// - If IsControl is set, then exactly one of IsDirectControl or
96    /// IsIndirect Control will be set, and exactly one of
97    /// IsCondControl or IsUncondControl will be set.
98    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
99    /// implemented as flags since in the current model there's no
100    /// other way for instructions to inject behavior into the
101    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
102    /// model we should be able to get rid of these flags and
103    /// implement this behavior via the execute() methods.
104    ///
105    enum Flags {
106        IsNop,		///< Is a no-op (no effect at all).
107
108        IsInteger,	///< References integer regs.
109        IsFloating,	///< References FP regs.
110
111        IsMemRef,	///< References memory (load, store, or prefetch).
112        IsLoad,		///< Reads from memory (load or prefetch).
113        IsStore,	///< Writes to memory.
114        IsStoreConditional,    ///< Store conditional instruction.
115        IsInstPrefetch,	///< Instruction-cache prefetch.
116        IsDataPrefetch,	///< Data-cache prefetch.
117        IsCopy,         ///< Fast Cache block copy
118
119        IsControl,		///< Control transfer instruction.
120        IsDirectControl,	///< PC relative control transfer.
121        IsIndirectControl,	///< Register indirect control transfer.
122        IsCondControl,		///< Conditional control transfer.
123        IsUncondControl,	///< Unconditional control transfer.
124        IsCall,			///< Subroutine call.
125        IsReturn,		///< Subroutine return.
126
127        IsCondDelaySlot,///< Conditional Delay-Slot Instruction
128
129        IsThreadSync,	///< Thread synchronization operation.
130
131        IsSerializing,	///< Serializes pipeline: won't execute until all
132                        /// older instructions have committed.
133        IsSerializeBefore,
134        IsSerializeAfter,
135        IsMemBarrier,	///< Is a memory barrier
136        IsWriteBarrier,	///< Is a write barrier
137
138        IsNonSpeculative, ///< Should not be executed speculatively
139        IsQuiesce,      ///< Is a quiesce instruction
140
141        IsIprAccess,    ///< Accesses IPRs
142        IsUnverifiable, ///< Can't be verified by a checker
143
144        //Flags for microcode
145        IsMacroOp,      ///< Is a macroop containing microops
146        IsMicroOp,	///< Is a microop
147        IsDelayedCommit,	///< This microop doesn't commit right away
148        IsLastMicroOp,	///< This microop ends a microop sequence
149        //This flag doesn't do anything yet
150        IsMicroBranch,	///< This microop branches within the microcode for a macroop
151
152        NumFlags
153    };
154
155    /// Flag values for this instruction.
156    std::bitset<NumFlags> flags;
157
158    /// See opClass().
159    OpClass _opClass;
160
161    /// See numSrcRegs().
162    int8_t _numSrcRegs;
163
164    /// See numDestRegs().
165    int8_t _numDestRegs;
166
167    /// The following are used to track physical register usage
168    /// for machines with separate int & FP reg files.
169    //@{
170    int8_t _numFPDestRegs;
171    int8_t _numIntDestRegs;
172    //@}
173
174    /// Constructor.
175    /// It's important to initialize everything here to a sane
176    /// default, since the decoder generally only overrides
177    /// the fields that are meaningful for the particular
178    /// instruction.
179    StaticInstBase(OpClass __opClass)
180        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
181          _numFPDestRegs(0), _numIntDestRegs(0)
182    {
183    }
184
185  public:
186
187    /// @name Register information.
188    /// The sum of numFPDestRegs() and numIntDestRegs() equals
189    /// numDestRegs().  The former two functions are used to track
190    /// physical register usage for machines with separate int & FP
191    /// reg files.
192    //@{
193    /// Number of source registers.
194    int8_t numSrcRegs()  const { return _numSrcRegs; }
195    /// Number of destination registers.
196    int8_t numDestRegs() const { return _numDestRegs; }
197    /// Number of floating-point destination regs.
198    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
199    /// Number of integer destination regs.
200    int8_t numIntDestRegs() const { return _numIntDestRegs; }
201    //@}
202
203    /// @name Flag accessors.
204    /// These functions are used to access the values of the various
205    /// instruction property flags.  See StaticInstBase::Flags for descriptions
206    /// of the individual flags.
207    //@{
208
209    bool isNop() 	  const { return flags[IsNop]; }
210
211    bool isMemRef()    	  const { return flags[IsMemRef]; }
212    bool isLoad()	  const { return flags[IsLoad]; }
213    bool isStore()	  const { return flags[IsStore]; }
214    bool isStoreConditional()	  const { return flags[IsStoreConditional]; }
215    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
216    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
217    bool isCopy()         const { return flags[IsCopy];}
218
219    bool isInteger()	  const { return flags[IsInteger]; }
220    bool isFloating()	  const { return flags[IsFloating]; }
221
222    bool isControl()	  const { return flags[IsControl]; }
223    bool isCall()	  const { return flags[IsCall]; }
224    bool isReturn()	  const { return flags[IsReturn]; }
225    bool isDirectCtrl()	  const { return flags[IsDirectControl]; }
226    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
227    bool isCondCtrl()	  const { return flags[IsCondControl]; }
228    bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
229    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
230
231    bool isThreadSync()   const { return flags[IsThreadSync]; }
232    bool isSerializing()  const { return flags[IsSerializing] ||
233                                      flags[IsSerializeBefore] ||
234                                      flags[IsSerializeAfter]; }
235    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
236    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
237    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
238    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
239    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
240    bool isQuiesce() const { return flags[IsQuiesce]; }
241    bool isIprAccess() const { return flags[IsIprAccess]; }
242    bool isUnverifiable() const { return flags[IsUnverifiable]; }
243    bool isMacroOp() const { return flags[IsMacroOp]; }
244    bool isMicroOp() const { return flags[IsMicroOp]; }
245    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
246    bool isLastMicroOp() const { return flags[IsLastMicroOp]; }
247    //This flag doesn't do anything yet
248    bool isMicroBranch() const { return flags[IsMicroBranch]; }
249    //@}
250
251    /// Operation class.  Used to select appropriate function unit in issue.
252    OpClass opClass()     const { return _opClass; }
253};
254
255
256// forward declaration
257class StaticInstPtr;
258
259/**
260 * Generic yet ISA-dependent static instruction class.
261 *
262 * This class builds on StaticInstBase, defining fields and interfaces
263 * that are generic across all ISAs but that differ in details
264 * according to the specific ISA being used.
265 */
266class StaticInst : public StaticInstBase
267{
268  public:
269
270    /// Binary machine instruction type.
271    typedef TheISA::MachInst MachInst;
272    /// Binary extended machine instruction type.
273    typedef TheISA::ExtMachInst ExtMachInst;
274    /// Logical register index type.
275    typedef TheISA::RegIndex RegIndex;
276
277    enum {
278        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
279        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
280    };
281
282
283    /// Return logical index (architectural reg num) of i'th destination reg.
284    /// Only the entries from 0 through numDestRegs()-1 are valid.
285    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
286
287    /// Return logical index (architectural reg num) of i'th source reg.
288    /// Only the entries from 0 through numSrcRegs()-1 are valid.
289    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
290
291    /// Pointer to a statically allocated "null" instruction object.
292    /// Used to give eaCompInst() and memAccInst() something to return
293    /// when called on non-memory instructions.
294    static StaticInstPtr nullStaticInstPtr;
295
296    /**
297     * Memory references only: returns "fake" instruction representing
298     * the effective address part of the memory operation.  Used to
299     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
300     * just the EA computation.
301     */
302    virtual const
303    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
304
305    /**
306     * Memory references only: returns "fake" instruction representing
307     * the memory access part of the memory operation.  Used to
308     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
309     * just the memory access (not the EA computation).
310     */
311    virtual const
312    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
313
314    /// The binary machine instruction.
315    const ExtMachInst machInst;
316
317  protected:
318
319    /// See destRegIdx().
320    RegIndex _destRegIdx[MaxInstDestRegs];
321    /// See srcRegIdx().
322    RegIndex _srcRegIdx[MaxInstSrcRegs];
323
324    /**
325     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
326     * methods.  Also useful to readily identify instructions from
327     * within the debugger when #cachedDisassembly has not been
328     * initialized.
329     */
330    const char *mnemonic;
331
332    /**
333     * String representation of disassembly (lazily evaluated via
334     * disassemble()).
335     */
336    mutable std::string *cachedDisassembly;
337
338    /**
339     * Internal function to generate disassembly string.
340     */
341    virtual std::string
342    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
343
344    /// Constructor.
345    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
346        : StaticInstBase(__opClass),
347          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
348    {
349    }
350
351  public:
352
353    virtual ~StaticInst()
354    {
355        if (cachedDisassembly)
356            delete cachedDisassembly;
357    }
358
359/**
360 * The execute() signatures are auto-generated by scons based on the
361 * set of CPU models we are compiling in today.
362 */
363#include "cpu/static_inst_exec_sigs.hh"
364
365    /**
366     * Return the microop that goes with a particular micropc. This should
367     * only be defined/used in macroops which will contain microops
368     */
369    virtual StaticInstPtr fetchMicroOp(MicroPC micropc);
370
371    /**
372     * Return the target address for a PC-relative branch.
373     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
374     * should be true).
375     */
376    virtual Addr branchTarget(Addr branchPC) const
377    {
378        panic("StaticInst::branchTarget() called on instruction "
379              "that is not a PC-relative branch.");
380    }
381
382    /**
383     * Return the target address for an indirect branch (jump).  The
384     * register value is read from the supplied thread context, so
385     * the result is valid only if the thread context is about to
386     * execute the branch in question.  Invalid if not an indirect
387     * branch (i.e. isIndirectCtrl() should be true).
388     */
389    virtual Addr branchTarget(ThreadContext *tc) const
390    {
391        panic("StaticInst::branchTarget() called on instruction "
392              "that is not an indirect branch.");
393    }
394
395    /**
396     * Return true if the instruction is a control transfer, and if so,
397     * return the target address as well.
398     */
399    bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
400
401    /**
402     * Return string representation of disassembled instruction.
403     * The default version of this function will call the internal
404     * virtual generateDisassembly() function to get the string,
405     * then cache it in #cachedDisassembly.  If the disassembly
406     * should not be cached, this function should be overridden directly.
407     */
408    virtual const std::string &disassemble(Addr pc,
409                                           const SymbolTable *symtab = 0) const
410    {
411        if (!cachedDisassembly)
412            cachedDisassembly =
413                new std::string(generateDisassembly(pc, symtab));
414
415        return *cachedDisassembly;
416    }
417
418    /// Decoded instruction cache type.
419    /// For now we're using a generic hash_map; this seems to work
420    /// pretty well.
421    typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
422
423    /// A cache of decoded instruction objects.
424    static DecodeCache decodeCache;
425
426    /**
427     * Dump some basic stats on the decode cache hash map.
428     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
429     */
430    static void dumpDecodeCacheStats();
431
432    /// Decode a machine instruction.
433    /// @param mach_inst The binary instruction to decode.
434    /// @retval A pointer to the corresponding StaticInst object.
435    //This is defined as inline below.
436    static StaticInstPtr decode(ExtMachInst mach_inst);
437
438    /// Return opcode of machine instruction
439    uint32_t getOpcode() { return bits(machInst, 31, 26);}
440
441    /// Return name of machine instruction
442    std::string getName() { return mnemonic; }
443};
444
445typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
446
447/// Reference-counted pointer to a StaticInst object.
448/// This type should be used instead of "StaticInst *" so that
449/// StaticInst objects can be properly reference-counted.
450class StaticInstPtr : public RefCountingPtr<StaticInst>
451{
452  public:
453    /// Constructor.
454    StaticInstPtr()
455        : RefCountingPtr<StaticInst>()
456    {
457    }
458
459    /// Conversion from "StaticInst *".
460    StaticInstPtr(StaticInst *p)
461        : RefCountingPtr<StaticInst>(p)
462    {
463    }
464
465    /// Copy constructor.
466    StaticInstPtr(const StaticInstPtr &r)
467        : RefCountingPtr<StaticInst>(r)
468    {
469    }
470
471    /// Construct directly from machine instruction.
472    /// Calls StaticInst::decode().
473    StaticInstPtr(TheISA::ExtMachInst mach_inst)
474        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
475    {
476    }
477
478    /// Convert to pointer to StaticInstBase class.
479    operator const StaticInstBasePtr()
480    {
481        return this->get();
482    }
483};
484
485inline StaticInstPtr
486StaticInst::decode(StaticInst::ExtMachInst mach_inst)
487{
488#ifdef DECODE_CACHE_HASH_STATS
489    // Simple stats on decode hash_map.  Turns out the default
490    // hash function is as good as anything I could come up with.
491    const int dump_every_n = 10000000;
492    static int decodes_til_dump = dump_every_n;
493
494    if (--decodes_til_dump == 0) {
495        dumpDecodeCacheStats();
496        decodes_til_dump = dump_every_n;
497    }
498#endif
499
500    DecodeCache::iterator iter = decodeCache.find(mach_inst);
501    if (iter != decodeCache.end()) {
502        return iter->second;
503    }
504
505    StaticInstPtr si = TheISA::decodeInst(mach_inst);
506    decodeCache[mach_inst] = si;
507    return si;
508}
509
510#endif // __CPU_STATIC_INST_HH__
511