static_inst.hh revision 2741:a73a50764b86 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#ifndef __CPU_STATIC_INST_HH__
32#define __CPU_STATIC_INST_HH__
33
34#include <bitset>
35#include <string>
36
37#include "base/bitfield.hh"
38#include "base/hashmap.hh"
39#include "base/misc.hh"
40#include "base/refcnt.hh"
41#include "cpu/op_class.hh"
42#include "sim/host.hh"
43#include "arch/isa_traits.hh"
44
45// forward declarations
46struct AlphaSimpleImpl;
47struct OzoneImpl;
48struct SimpleImpl;
49class ThreadContext;
50class DynInst;
51class Packet;
52
53template <class Impl>
54class AlphaDynInst;
55
56template <class Impl>
57class OzoneDynInst;
58
59class CheckerCPU;
60class FastCPU;
61class AtomicSimpleCPU;
62class TimingSimpleCPU;
63class InorderCPU;
64class SymbolTable;
65
66namespace Trace {
67    class InstRecord;
68}
69
70/**
71 * Base, ISA-independent static instruction class.
72 *
73 * The main component of this class is the vector of flags and the
74 * associated methods for reading them.  Any object that can rely
75 * solely on these flags can process instructions without being
76 * recompiled for multiple ISAs.
77 */
78class StaticInstBase : public RefCounted
79{
80  protected:
81
82    /// Set of boolean static instruction properties.
83    ///
84    /// Notes:
85    /// - The IsInteger and IsFloating flags are based on the class of
86    /// registers accessed by the instruction.  Although most
87    /// instructions will have exactly one of these two flags set, it
88    /// is possible for an instruction to have neither (e.g., direct
89    /// unconditional branches, memory barriers) or both (e.g., an
90    /// FP/int conversion).
91    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
92    /// will be set.
93    /// - If IsControl is set, then exactly one of IsDirectControl or
94    /// IsIndirect Control will be set, and exactly one of
95    /// IsCondControl or IsUncondControl will be set.
96    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
97    /// implemented as flags since in the current model there's no
98    /// other way for instructions to inject behavior into the
99    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
100    /// model we should be able to get rid of these flags and
101    /// implement this behavior via the execute() methods.
102    ///
103    enum Flags {
104        IsNop,		///< Is a no-op (no effect at all).
105
106        IsInteger,	///< References integer regs.
107        IsFloating,	///< References FP regs.
108
109        IsMemRef,	///< References memory (load, store, or prefetch).
110        IsLoad,		///< Reads from memory (load or prefetch).
111        IsStore,	///< Writes to memory.
112        IsStoreConditional,    ///< Store conditional instruction.
113        IsInstPrefetch,	///< Instruction-cache prefetch.
114        IsDataPrefetch,	///< Data-cache prefetch.
115        IsCopy,         ///< Fast Cache block copy
116
117        IsControl,		///< Control transfer instruction.
118        IsDirectControl,	///< PC relative control transfer.
119        IsIndirectControl,	///< Register indirect control transfer.
120        IsCondControl,		///< Conditional control transfer.
121        IsUncondControl,	///< Unconditional control transfer.
122        IsCall,			///< Subroutine call.
123        IsReturn,		///< Subroutine return.
124
125        IsCondDelaySlot,///< Conditional Delay-Slot Instruction
126
127        IsThreadSync,	///< Thread synchronization operation.
128
129        IsSerializing,	///< Serializes pipeline: won't execute until all
130                        /// older instructions have committed.
131        IsSerializeBefore,
132        IsSerializeAfter,
133        IsMemBarrier,	///< Is a memory barrier
134        IsWriteBarrier,	///< Is a write barrier
135
136        IsNonSpeculative, ///< Should not be executed speculatively
137        IsQuiesce,      ///< Is a quiesce instruction
138
139        IsIprAccess,    ///< Accesses IPRs
140        IsUnverifiable, ///< Can't be verified by a checker
141
142        NumFlags
143    };
144
145    /// Flag values for this instruction.
146    std::bitset<NumFlags> flags;
147
148    /// See opClass().
149    OpClass _opClass;
150
151    /// See numSrcRegs().
152    int8_t _numSrcRegs;
153
154    /// See numDestRegs().
155    int8_t _numDestRegs;
156
157    /// The following are used to track physical register usage
158    /// for machines with separate int & FP reg files.
159    //@{
160    int8_t _numFPDestRegs;
161    int8_t _numIntDestRegs;
162    //@}
163
164    /// Constructor.
165    /// It's important to initialize everything here to a sane
166    /// default, since the decoder generally only overrides
167    /// the fields that are meaningful for the particular
168    /// instruction.
169    StaticInstBase(OpClass __opClass)
170        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
171          _numFPDestRegs(0), _numIntDestRegs(0)
172    {
173    }
174
175  public:
176
177    /// @name Register information.
178    /// The sum of numFPDestRegs() and numIntDestRegs() equals
179    /// numDestRegs().  The former two functions are used to track
180    /// physical register usage for machines with separate int & FP
181    /// reg files.
182    //@{
183    /// Number of source registers.
184    int8_t numSrcRegs()  const { return _numSrcRegs; }
185    /// Number of destination registers.
186    int8_t numDestRegs() const { return _numDestRegs; }
187    /// Number of floating-point destination regs.
188    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
189    /// Number of integer destination regs.
190    int8_t numIntDestRegs() const { return _numIntDestRegs; }
191    //@}
192
193    /// @name Flag accessors.
194    /// These functions are used to access the values of the various
195    /// instruction property flags.  See StaticInstBase::Flags for descriptions
196    /// of the individual flags.
197    //@{
198
199    bool isNop() 	  const { return flags[IsNop]; }
200
201    bool isMemRef()    	  const { return flags[IsMemRef]; }
202    bool isLoad()	  const { return flags[IsLoad]; }
203    bool isStore()	  const { return flags[IsStore]; }
204    bool isStoreConditional()	  const { return flags[IsStoreConditional]; }
205    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
206    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
207    bool isCopy()         const { return flags[IsCopy];}
208
209    bool isInteger()	  const { return flags[IsInteger]; }
210    bool isFloating()	  const { return flags[IsFloating]; }
211
212    bool isControl()	  const { return flags[IsControl]; }
213    bool isCall()	  const { return flags[IsCall]; }
214    bool isReturn()	  const { return flags[IsReturn]; }
215    bool isDirectCtrl()	  const { return flags[IsDirectControl]; }
216    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
217    bool isCondCtrl()	  const { return flags[IsCondControl]; }
218    bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
219
220    bool isThreadSync()   const { return flags[IsThreadSync]; }
221    bool isSerializing()  const { return flags[IsSerializing] ||
222                                      flags[IsSerializeBefore] ||
223                                      flags[IsSerializeAfter]; }
224    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
225    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
226    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
227    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
228    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
229    bool isQuiesce() const { return flags[IsQuiesce]; }
230    bool isIprAccess() const { return flags[IsIprAccess]; }
231    bool isUnverifiable() const { return flags[IsUnverifiable]; }
232    //@}
233
234    /// Operation class.  Used to select appropriate function unit in issue.
235    OpClass opClass()     const { return _opClass; }
236};
237
238
239// forward declaration
240class StaticInstPtr;
241
242/**
243 * Generic yet ISA-dependent static instruction class.
244 *
245 * This class builds on StaticInstBase, defining fields and interfaces
246 * that are generic across all ISAs but that differ in details
247 * according to the specific ISA being used.
248 */
249class StaticInst : public StaticInstBase
250{
251  public:
252
253    /// Binary machine instruction type.
254    typedef TheISA::MachInst MachInst;
255    /// Binary extended machine instruction type.
256    typedef TheISA::ExtMachInst ExtMachInst;
257    /// Logical register index type.
258    typedef TheISA::RegIndex RegIndex;
259
260    enum {
261        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
262        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
263    };
264
265
266    /// Return logical index (architectural reg num) of i'th destination reg.
267    /// Only the entries from 0 through numDestRegs()-1 are valid.
268    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
269
270    /// Return logical index (architectural reg num) of i'th source reg.
271    /// Only the entries from 0 through numSrcRegs()-1 are valid.
272    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
273
274    /// Pointer to a statically allocated "null" instruction object.
275    /// Used to give eaCompInst() and memAccInst() something to return
276    /// when called on non-memory instructions.
277    static StaticInstPtr nullStaticInstPtr;
278
279    /**
280     * Memory references only: returns "fake" instruction representing
281     * the effective address part of the memory operation.  Used to
282     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
283     * just the EA computation.
284     */
285    virtual const
286    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
287
288    /**
289     * Memory references only: returns "fake" instruction representing
290     * the memory access part of the memory operation.  Used to
291     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
292     * just the memory access (not the EA computation).
293     */
294    virtual const
295    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
296
297    /// The binary machine instruction.
298    const ExtMachInst machInst;
299
300  protected:
301
302    /// See destRegIdx().
303    RegIndex _destRegIdx[MaxInstDestRegs];
304    /// See srcRegIdx().
305    RegIndex _srcRegIdx[MaxInstSrcRegs];
306
307    /**
308     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
309     * methods.  Also useful to readily identify instructions from
310     * within the debugger when #cachedDisassembly has not been
311     * initialized.
312     */
313    const char *mnemonic;
314
315    /**
316     * String representation of disassembly (lazily evaluated via
317     * disassemble()).
318     */
319    mutable std::string *cachedDisassembly;
320
321    /**
322     * Internal function to generate disassembly string.
323     */
324    virtual std::string
325    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
326
327    /// Constructor.
328    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
329        : StaticInstBase(__opClass),
330          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
331    {
332    }
333
334  public:
335
336    virtual ~StaticInst()
337    {
338        if (cachedDisassembly)
339            delete cachedDisassembly;
340    }
341
342/**
343 * The execute() signatures are auto-generated by scons based on the
344 * set of CPU models we are compiling in today.
345 */
346#include "cpu/static_inst_exec_sigs.hh"
347
348    /**
349     * Return the target address for a PC-relative branch.
350     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
351     * should be true).
352     */
353    virtual Addr branchTarget(Addr branchPC) const
354    {
355        panic("StaticInst::branchTarget() called on instruction "
356              "that is not a PC-relative branch.");
357    }
358
359    /**
360     * Return the target address for an indirect branch (jump).  The
361     * register value is read from the supplied thread context, so
362     * the result is valid only if the thread context is about to
363     * execute the branch in question.  Invalid if not an indirect
364     * branch (i.e. isIndirectCtrl() should be true).
365     */
366    virtual Addr branchTarget(ThreadContext *tc) const
367    {
368        panic("StaticInst::branchTarget() called on instruction "
369              "that is not an indirect branch.");
370    }
371
372    /**
373     * Return true if the instruction is a control transfer, and if so,
374     * return the target address as well.
375     */
376    bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
377
378    /**
379     * Return string representation of disassembled instruction.
380     * The default version of this function will call the internal
381     * virtual generateDisassembly() function to get the string,
382     * then cache it in #cachedDisassembly.  If the disassembly
383     * should not be cached, this function should be overridden directly.
384     */
385    virtual const std::string &disassemble(Addr pc,
386                                           const SymbolTable *symtab = 0) const
387    {
388        if (!cachedDisassembly)
389            cachedDisassembly =
390                new std::string(generateDisassembly(pc, symtab));
391
392        return *cachedDisassembly;
393    }
394
395    /// Decoded instruction cache type.
396    /// For now we're using a generic hash_map; this seems to work
397    /// pretty well.
398    typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
399
400    /// A cache of decoded instruction objects.
401    static DecodeCache decodeCache;
402
403    /**
404     * Dump some basic stats on the decode cache hash map.
405     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
406     */
407    static void dumpDecodeCacheStats();
408
409    /// Decode a machine instruction.
410    /// @param mach_inst The binary instruction to decode.
411    /// @retval A pointer to the corresponding StaticInst object.
412    //This is defined as inline below.
413    static StaticInstPtr decode(ExtMachInst mach_inst);
414
415    /// Return opcode of machine instruction
416    uint32_t getOpcode() { return bits(machInst, 31, 26);}
417
418    /// Return name of machine instruction
419    std::string getName() { return mnemonic; }
420};
421
422typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
423
424/// Reference-counted pointer to a StaticInst object.
425/// This type should be used instead of "StaticInst *" so that
426/// StaticInst objects can be properly reference-counted.
427class StaticInstPtr : public RefCountingPtr<StaticInst>
428{
429  public:
430    /// Constructor.
431    StaticInstPtr()
432        : RefCountingPtr<StaticInst>()
433    {
434    }
435
436    /// Conversion from "StaticInst *".
437    StaticInstPtr(StaticInst *p)
438        : RefCountingPtr<StaticInst>(p)
439    {
440    }
441
442    /// Copy constructor.
443    StaticInstPtr(const StaticInstPtr &r)
444        : RefCountingPtr<StaticInst>(r)
445    {
446    }
447
448    /// Construct directly from machine instruction.
449    /// Calls StaticInst::decode().
450    StaticInstPtr(TheISA::ExtMachInst mach_inst)
451        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
452    {
453    }
454
455    /// Convert to pointer to StaticInstBase class.
456    operator const StaticInstBasePtr()
457    {
458        return this->get();
459    }
460};
461
462inline StaticInstPtr
463StaticInst::decode(StaticInst::ExtMachInst mach_inst)
464{
465#ifdef DECODE_CACHE_HASH_STATS
466    // Simple stats on decode hash_map.  Turns out the default
467    // hash function is as good as anything I could come up with.
468    const int dump_every_n = 10000000;
469    static int decodes_til_dump = dump_every_n;
470
471    if (--decodes_til_dump == 0) {
472        dumpDecodeCacheStats();
473        decodes_til_dump = dump_every_n;
474    }
475#endif
476
477    DecodeCache::iterator iter = decodeCache.find(mach_inst);
478    if (iter != decodeCache.end()) {
479        return iter->second;
480    }
481
482    StaticInstPtr si = TheISA::decodeInst(mach_inst);
483    decodeCache[mach_inst] = si;
484    return si;
485}
486
487#endif // __CPU_STATIC_INST_HH__
488