static_inst.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/reg_class.hh"
46#include "cpu/reg_class_impl.hh"
47#include "cpu/static_inst_fwd.hh"
48#include "cpu/thread_context.hh"
49#include "enums/StaticInstFlags.hh"
50
51// forward declarations
52class Packet;
53
54class ExecContext;
55
56class SymbolTable;
57
58namespace Trace {
59    class InstRecord;
60}
61
62/**
63 * Base, ISA-independent static instruction class.
64 *
65 * The main component of this class is the vector of flags and the
66 * associated methods for reading them.  Any object that can rely
67 * solely on these flags can process instructions without being
68 * recompiled for multiple ISAs.
69 */
70class StaticInst : public RefCounted, public StaticInstFlags
71{
72  public:
73    /// Binary extended machine instruction type.
74    typedef TheISA::ExtMachInst ExtMachInst;
75
76    enum {
77        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
78        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
79    };
80
81  protected:
82
83    /// Flag values for this instruction.
84    std::bitset<Num_Flags> flags;
85
86    /// See opClass().
87    OpClass _opClass;
88
89    /// See numSrcRegs().
90    int8_t _numSrcRegs;
91
92    /// See numDestRegs().
93    int8_t _numDestRegs;
94
95    /// The following are used to track physical register usage
96    /// for machines with separate int & FP reg files.
97    //@{
98    int8_t _numFPDestRegs;
99    int8_t _numIntDestRegs;
100    int8_t _numCCDestRegs;
101    //@}
102
103  public:
104
105    /// @name Register information.
106    /// The sum of numFPDestRegs() and numIntDestRegs() equals
107    /// numDestRegs().  The former two functions are used to track
108    /// physical register usage for machines with separate int & FP
109    /// reg files.
110    //@{
111    /// Number of source registers.
112    int8_t numSrcRegs()  const { return _numSrcRegs; }
113    /// Number of destination registers.
114    int8_t numDestRegs() const { return _numDestRegs; }
115    /// Number of floating-point destination regs.
116    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
117    /// Number of integer destination regs.
118    int8_t numIntDestRegs() const { return _numIntDestRegs; }
119    //@}
120    /// Number of coprocesor destination regs.
121    int8_t numCCDestRegs() const { return _numCCDestRegs; }
122    //@}
123
124    /// @name Flag accessors.
125    /// These functions are used to access the values of the various
126    /// instruction property flags.  See StaticInst::Flags for descriptions
127    /// of the individual flags.
128    //@{
129
130    bool isNop()          const { return flags[IsNop]; }
131
132    bool isMemRef()       const { return flags[IsMemRef]; }
133    bool isLoad()         const { return flags[IsLoad]; }
134    bool isStore()        const { return flags[IsStore]; }
135    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
136    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
137    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
138    bool isPrefetch()     const { return isInstPrefetch() ||
139                                         isDataPrefetch(); }
140
141    bool isInteger()      const { return flags[IsInteger]; }
142    bool isFloating()     const { return flags[IsFloating]; }
143    bool isCC()           const { return flags[IsCC]; }
144
145    bool isControl()      const { return flags[IsControl]; }
146    bool isCall()         const { return flags[IsCall]; }
147    bool isReturn()       const { return flags[IsReturn]; }
148    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
149    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
150    bool isCondCtrl()     const { return flags[IsCondControl]; }
151    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
152    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
153
154    bool isThreadSync()   const { return flags[IsThreadSync]; }
155    bool isSerializing()  const { return flags[IsSerializing] ||
156                                      flags[IsSerializeBefore] ||
157                                      flags[IsSerializeAfter]; }
158    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
159    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
160    bool isSquashAfter() const { return flags[IsSquashAfter]; }
161    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
162    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
163    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
164    bool isQuiesce() const { return flags[IsQuiesce]; }
165    bool isIprAccess() const { return flags[IsIprAccess]; }
166    bool isUnverifiable() const { return flags[IsUnverifiable]; }
167    bool isSyscall() const { return flags[IsSyscall]; }
168    bool isMacroop() const { return flags[IsMacroop]; }
169    bool isMicroop() const { return flags[IsMicroop]; }
170    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
171    bool isLastMicroop() const { return flags[IsLastMicroop]; }
172    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
173    //This flag doesn't do anything yet
174    bool isMicroBranch() const { return flags[IsMicroBranch]; }
175    //@}
176
177    void setFirstMicroop() { flags[IsFirstMicroop] = true; }
178    void setLastMicroop() { flags[IsLastMicroop] = true; }
179    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
180    void setFlag(Flags f) { flags[f] = true; }
181
182    /// Operation class.  Used to select appropriate function unit in issue.
183    OpClass opClass()     const { return _opClass; }
184
185
186    /// Return logical index (architectural reg num) of i'th destination reg.
187    /// Only the entries from 0 through numDestRegs()-1 are valid.
188    const RegId& destRegIdx(int i) const { return _destRegIdx[i]; }
189
190    /// Return logical index (architectural reg num) of i'th source reg.
191    /// Only the entries from 0 through numSrcRegs()-1 are valid.
192    const RegId& srcRegIdx(int i)  const { return _srcRegIdx[i]; }
193
194    /// Pointer to a statically allocated "null" instruction object.
195    /// Used to give eaCompInst() and memAccInst() something to return
196    /// when called on non-memory instructions.
197    static StaticInstPtr nullStaticInstPtr;
198
199    /**
200     * Memory references only: returns "fake" instruction representing
201     * the effective address part of the memory operation.  Used to
202     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
203     * just the EA computation.
204     */
205    virtual const
206    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
207
208    /**
209     * Memory references only: returns "fake" instruction representing
210     * the memory access part of the memory operation.  Used to
211     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
212     * just the memory access (not the EA computation).
213     */
214    virtual const
215    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
216
217    /// The binary machine instruction.
218    const ExtMachInst machInst;
219
220  protected:
221
222    /// See destRegIdx().
223    RegId _destRegIdx[MaxInstDestRegs];
224    /// See srcRegIdx().
225    RegId _srcRegIdx[MaxInstSrcRegs];
226
227    /**
228     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
229     * methods.  Also useful to readily identify instructions from
230     * within the debugger when #cachedDisassembly has not been
231     * initialized.
232     */
233    const char *mnemonic;
234
235    /**
236     * String representation of disassembly (lazily evaluated via
237     * disassemble()).
238     */
239    mutable std::string *cachedDisassembly;
240
241    /**
242     * Internal function to generate disassembly string.
243     */
244    virtual std::string
245    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
246
247    /// Constructor.
248    /// It's important to initialize everything here to a sane
249    /// default, since the decoder generally only overrides
250    /// the fields that are meaningful for the particular
251    /// instruction.
252    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
253        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
254          _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
255          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
256    { }
257
258  public:
259    virtual ~StaticInst();
260
261    virtual Fault execute(ExecContext *xc,
262                          Trace::InstRecord *traceData) const = 0;
263    virtual Fault eaComp(ExecContext *xc,
264                         Trace::InstRecord *traceData) const
265    {
266        panic("eaComp not defined!");
267    }
268
269    virtual Fault initiateAcc(ExecContext *xc,
270                              Trace::InstRecord *traceData) const
271    {
272        panic("initiateAcc not defined!");
273    }
274
275    virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
276                              Trace::InstRecord *traceData) const
277    {
278        panic("completeAcc not defined!");
279    }
280
281    virtual void advancePC(TheISA::PCState &pcState) const = 0;
282
283    /**
284     * Return the microop that goes with a particular micropc. This should
285     * only be defined/used in macroops which will contain microops
286     */
287    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
288
289    /**
290     * Return the target address for a PC-relative branch.
291     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
292     * should be true).
293     */
294    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
295
296    /**
297     * Return the target address for an indirect branch (jump).  The
298     * register value is read from the supplied thread context, so
299     * the result is valid only if the thread context is about to
300     * execute the branch in question.  Invalid if not an indirect
301     * branch (i.e. isIndirectCtrl() should be true).
302     */
303    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
304
305    /**
306     * Return true if the instruction is a control transfer, and if so,
307     * return the target address as well.
308     */
309    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
310                         TheISA::PCState &tgt) const;
311
312    /**
313     * Return string representation of disassembled instruction.
314     * The default version of this function will call the internal
315     * virtual generateDisassembly() function to get the string,
316     * then cache it in #cachedDisassembly.  If the disassembly
317     * should not be cached, this function should be overridden directly.
318     */
319    virtual const std::string &disassemble(Addr pc,
320        const SymbolTable *symtab = 0) const;
321
322    /**
323     * Print a separator separated list of this instruction's set flag
324     * names on the given stream.
325     */
326    void printFlags(std::ostream &outs, const std::string &separator) const;
327
328    /// Return name of machine instruction
329    std::string getName() { return mnemonic; }
330};
331
332#endif // __CPU_STATIC_INST_HH__
333