static_inst.hh revision 1128
11689SN/A/* 22325SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292756Sksewell@umich.edu#ifndef __STATIC_INST_HH__ 301689SN/A#define __STATIC_INST_HH__ 311689SN/A 321858SN/A#include <bitset> 332733Sktlim@umich.edu#include <string> 341858SN/A 351858SN/A#include "sim/host.hh" 362356SN/A#include "base/hashmap.hh" 371060SN/A#include "base/refcnt.hh" 381060SN/A 391060SN/A#include "cpu/full_cpu/op_class.hh" 401060SN/A#include "targetarch/isa_traits.hh" 411060SN/A 422325SN/A// forward declarations 432683Sktlim@umich.educlass ExecContext; 442680Sktlim@umich.educlass DynInst; 452817Sksewell@umich.educlass FastCPU; 461717SN/Aclass SimpleCPU; 471060SN/Aclass InorderCPU; 484167Sbinkertn@umich.educlass SymbolTable; 492292SN/A 502292SN/Anamespace Trace { 512794Sktlim@umich.edu class InstRecord; 522794Sktlim@umich.edu} 532794Sktlim@umich.edu 542794Sktlim@umich.edu/** 551060SN/A * Base, ISA-independent static instruction class. 562669Sktlim@umich.edu * 571060SN/A * The main component of this class is the vector of flags and the 582733Sktlim@umich.edu * associated methods for reading them. Any object that can rely 592292SN/A * solely on these flags can process instructions without being 601060SN/A * recompiled for multiple ISAs. 611060SN/A */ 621060SN/Aclass StaticInstBase : public RefCounted 632292SN/A{ 642733Sktlim@umich.edu protected: 652292SN/A 662292SN/A /// Set of boolean static instruction properties. 672292SN/A /// 682292SN/A /// Notes: 691060SN/A /// - The IsInteger and IsFloating flags are based on the class of 701755SN/A /// registers accessed by the instruction. Although most 711060SN/A /// instructions will have exactly one of these two flags set, it 721060SN/A /// is possible for an instruction to have neither (e.g., direct 731060SN/A /// unconditional branches, memory barriers) or both (e.g., an 741060SN/A /// FP/int conversion). 751060SN/A /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 761060SN/A /// will be set. 771755SN/A /// - If IsControl is set, then exactly one of IsDirectControl or 781060SN/A /// IsIndirect Control will be set, and exactly one of 791060SN/A /// IsCondControl or IsUncondControl will be set. 801060SN/A /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 811060SN/A /// implemented as flags since in the current model there's no 821060SN/A /// other way for instructions to inject behavior into the 831060SN/A /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 841755SN/A /// model we should be able to get rid of these flags and 851060SN/A /// implement this behavior via the execute() methods. 861755SN/A /// 871060SN/A enum Flags { 881060SN/A IsNop, ///< Is a no-op (no effect at all). 891060SN/A 902829Sksewell@umich.edu IsInteger, ///< References integer regs. 913221Sktlim@umich.edu IsFloating, ///< References FP regs. 922829Sksewell@umich.edu 932829Sksewell@umich.edu IsMemRef, ///< References memory (load, store, or prefetch). 942829Sksewell@umich.edu IsLoad, ///< Reads from memory (load or prefetch). 952829Sksewell@umich.edu IsStore, ///< Writes to memory. 962829Sksewell@umich.edu IsInstPrefetch, ///< Instruction-cache prefetch. 972829Sksewell@umich.edu IsDataPrefetch, ///< Data-cache prefetch. 982829Sksewell@umich.edu IsCopy, ///< Fast Cache block copy 992829Sksewell@umich.edu 1002829Sksewell@umich.edu IsControl, ///< Control transfer instruction. 1012829Sksewell@umich.edu IsDirectControl, ///< PC relative control transfer. 1022829Sksewell@umich.edu IsIndirectControl, ///< Register indirect control transfer. 1032829Sksewell@umich.edu IsCondControl, ///< Conditional control transfer. 1042829Sksewell@umich.edu IsUncondControl, ///< Unconditional control transfer. 1052829Sksewell@umich.edu IsCall, ///< Subroutine call. 1062829Sksewell@umich.edu IsReturn, ///< Subroutine return. 1072829Sksewell@umich.edu 1082829Sksewell@umich.edu IsThreadSync, ///< Thread synchronization operation. 1092829Sksewell@umich.edu 1102829Sksewell@umich.edu IsSerializing, ///< Serializes pipeline: won't execute until all 1112829Sksewell@umich.edu /// older instructions have committed. 1122829Sksewell@umich.edu IsMemBarrier, ///< Is a memory barrier 1132829Sksewell@umich.edu IsWriteBarrier, ///< Is a write barrier 1142829Sksewell@umich.edu 1152829Sksewell@umich.edu IsNonSpeculative, ///< Should not be executed speculatively 1162829Sksewell@umich.edu 1172829Sksewell@umich.edu NumFlags 1182829Sksewell@umich.edu }; 1192875Sksewell@umich.edu 1203859Sbinkertn@umich.edu /// Flag values for this instruction. 1212875Sksewell@umich.edu std::bitset<NumFlags> flags; 1222875Sksewell@umich.edu 1232875Sksewell@umich.edu /// See opClass(). 1242875Sksewell@umich.edu OpClass _opClass; 1252875Sksewell@umich.edu 1262875Sksewell@umich.edu /// See numSrcRegs(). 1273859Sbinkertn@umich.edu int8_t _numSrcRegs; 1282875Sksewell@umich.edu 1292875Sksewell@umich.edu /// See numDestRegs(). 1302875Sksewell@umich.edu int8_t _numDestRegs; 1313859Sbinkertn@umich.edu 1322875Sksewell@umich.edu /// The following are used to track physical register usage 1332875Sksewell@umich.edu /// for machines with separate int & FP reg files. 1342875Sksewell@umich.edu //@{ 1352875Sksewell@umich.edu int8_t _numFPDestRegs; 1362875Sksewell@umich.edu int8_t _numIntDestRegs; 1372875Sksewell@umich.edu //@} 1382875Sksewell@umich.edu 1393221Sktlim@umich.edu /// Constructor. 1403221Sktlim@umich.edu /// It's important to initialize everything here to a sane 1412875Sksewell@umich.edu /// default, since the decoder generally only overrides 1422875Sksewell@umich.edu /// the fields that are meaningful for the particular 1432875Sksewell@umich.edu /// instruction. 1442875Sksewell@umich.edu StaticInstBase(OpClass __opClass) 1452875Sksewell@umich.edu : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 1462875Sksewell@umich.edu _numFPDestRegs(0), _numIntDestRegs(0) 1472875Sksewell@umich.edu { 1482875Sksewell@umich.edu } 1492875Sksewell@umich.edu 1502875Sksewell@umich.edu public: 1514329Sktlim@umich.edu 1522733Sktlim@umich.edu /// @name Register information. 1533781Sgblack@eecs.umich.edu /// The sum of numFPDestRegs() and numIntDestRegs() equals 1543781Sgblack@eecs.umich.edu /// numDestRegs(). The former two functions are used to track 1553781Sgblack@eecs.umich.edu /// physical register usage for machines with separate int & FP 1563781Sgblack@eecs.umich.edu /// reg files. 1571060SN/A //@{ 1582292SN/A /// Number of source registers. 1594329Sktlim@umich.edu int8_t numSrcRegs() const { return _numSrcRegs; } 1604329Sktlim@umich.edu /// Number of destination registers. 1614329Sktlim@umich.edu int8_t numDestRegs() const { return _numDestRegs; } 1624329Sktlim@umich.edu /// Number of floating-point destination regs. 1634329Sktlim@umich.edu int8_t numFPDestRegs() const { return _numFPDestRegs; } 1641060SN/A /// Number of integer destination regs. 1654329Sktlim@umich.edu int8_t numIntDestRegs() const { return _numIntDestRegs; } 1664329Sktlim@umich.edu //@} 1671060SN/A 1682831Sksewell@umich.edu /// @name Flag accessors. 1692292SN/A /// These functions are used to access the values of the various 1702292SN/A /// instruction property flags. See StaticInstBase::Flags for descriptions 1711060SN/A /// of the individual flags. 1724329Sktlim@umich.edu //@{ 1734329Sktlim@umich.edu 1742292SN/A bool isNop() const { return flags[IsNop]; } 1752292SN/A 1761060SN/A bool isMemRef() const { return flags[IsMemRef]; } 1772831Sksewell@umich.edu bool isLoad() const { return flags[IsLoad]; } 1782292SN/A bool isStore() const { return flags[IsStore]; } 1792292SN/A bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 1802292SN/A bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 1812292SN/A bool isCopy() const { return flags[IsCopy];} 1821060SN/A 1832873Sktlim@umich.edu bool isInteger() const { return flags[IsInteger]; } 1842873Sktlim@umich.edu bool isFloating() const { return flags[IsFloating]; } 1852873Sktlim@umich.edu 1862873Sktlim@umich.edu bool isControl() const { return flags[IsControl]; } 1872873Sktlim@umich.edu bool isCall() const { return flags[IsCall]; } 1882873Sktlim@umich.edu bool isReturn() const { return flags[IsReturn]; } 1892873Sktlim@umich.edu bool isDirectCtrl() const { return flags[IsDirectControl]; } 1902873Sktlim@umich.edu bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 1911060SN/A bool isCondCtrl() const { return flags[IsCondControl]; } 1921060SN/A bool isUncondCtrl() const { return flags[IsUncondControl]; } 1931858SN/A 1942292SN/A bool isThreadSync() const { return flags[IsThreadSync]; } 1951060SN/A bool isSerializing() const { return flags[IsSerializing]; } 1961060SN/A bool isMemBarrier() const { return flags[IsMemBarrier]; } 1972843Sktlim@umich.edu bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 1982316SN/A bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 1992316SN/A //@} 2001060SN/A 2013221Sktlim@umich.edu /// Operation class. Used to select appropriate function unit in issue. 2023221Sktlim@umich.edu OpClass opClass() const { return _opClass; } 2033221Sktlim@umich.edu}; 2043221Sktlim@umich.edu 2053221Sktlim@umich.edu 2061681SN/A// forward declaration 2072733Sktlim@umich.edutemplate <class ISA> 2082733Sktlim@umich.educlass StaticInstPtr; 2092794Sktlim@umich.edu 2102733Sktlim@umich.edu/** 2112316SN/A * Generic yet ISA-dependent static instruction class. 2122316SN/A * 2132316SN/A * This class builds on StaticInstBase, defining fields and interfaces 2142316SN/A * that are generic across all ISAs but that differ in details 2152316SN/A * according to the specific ISA being used. 2162794Sktlim@umich.edu */ 2172794Sktlim@umich.edutemplate <class ISA> 2182794Sktlim@umich.educlass StaticInst : public StaticInstBase 2192316SN/A{ 2202316SN/A public: 2211858SN/A 2222292SN/A /// Binary machine instruction type. 2232292SN/A typedef typename ISA::MachInst MachInst; 2241681SN/A /// Memory address type. 2251681SN/A typedef typename ISA::Addr Addr; 2262325SN/A /// Logical register index type. 2272325SN/A typedef typename ISA::RegIndex RegIndex; 2282325SN/A 2291060SN/A enum { 2302292SN/A MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs 2312292SN/A MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs 2322292SN/A }; 2332292SN/A 2342292SN/A 2352292SN/A /// Return logical index (architectural reg num) of i'th destination reg. 2361060SN/A /// Only the entries from 0 through numDestRegs()-1 are valid. 2371060SN/A RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 2381060SN/A 2391060SN/A /// Return logical index (architectural reg num) of i'th source reg. 2401060SN/A /// Only the entries from 0 through numSrcRegs()-1 are valid. 2411060SN/A RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 2421060SN/A 2431060SN/A /// Pointer to a statically allocated "null" instruction object. 2441060SN/A /// Used to give eaCompInst() and memAccInst() something to return 2451060SN/A /// when called on non-memory instructions. 2461060SN/A static StaticInstPtr<ISA> nullStaticInstPtr; 2472292SN/A 2481060SN/A /** 2491060SN/A * Memory references only: returns "fake" instruction representing 2501060SN/A * the effective address part of the memory operation. Used to 2511060SN/A * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 2521060SN/A * just the EA computation. 2531060SN/A */ 2541060SN/A virtual const 2551060SN/A StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; } 2562292SN/A 2572292SN/A /** 2582292SN/A * Memory references only: returns "fake" instruction representing 2592292SN/A * the memory access part of the memory operation. Used to 2602292SN/A * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 2612307SN/A * just the memory access (not the EA computation). 2622831Sksewell@umich.edu */ 2632831Sksewell@umich.edu virtual const 2642831Sksewell@umich.edu StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; } 2652831Sksewell@umich.edu 2662831Sksewell@umich.edu /// The binary machine instruction. 2672831Sksewell@umich.edu const MachInst machInst; 2682292SN/A 2692307SN/A protected: 2702292SN/A 2712292SN/A /// See destRegIdx(). 2722316SN/A RegIndex _destRegIdx[MaxInstDestRegs]; 2732292SN/A /// See srcRegIdx(). 2742292SN/A RegIndex _srcRegIdx[MaxInstSrcRegs]; 2752292SN/A 2762292SN/A /** 2772292SN/A * Base mnemonic (e.g., "add"). Used by generateDisassembly() 2782292SN/A * methods. Also useful to readily identify instructions from 2791060SN/A * within the debugger when #cachedDisassembly has not been 2802292SN/A * initialized. 2812292SN/A */ 2821060SN/A const char *mnemonic; 2832292SN/A 2842307SN/A /** 2852292SN/A * String representation of disassembly (lazily evaluated via 2862292SN/A * disassemble()). 2872292SN/A */ 2882325SN/A std::string *cachedDisassembly; 2892292SN/A 2902292SN/A /** 2912292SN/A * Internal function to generate disassembly string. 2922325SN/A */ 2932292SN/A virtual std::string generateDisassembly(Addr pc, 2942292SN/A const SymbolTable *symtab) = 0; 2952292SN/A 2962292SN/A /// Constructor. 2972292SN/A StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass) 2982292SN/A : StaticInstBase(__opClass), 2992292SN/A machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 3002292SN/A { 3012292SN/A } 3022292SN/A 3032292SN/A public: 3042325SN/A 3052292SN/A virtual ~StaticInst() 3062292SN/A { 3072292SN/A if (cachedDisassembly) 3082325SN/A delete cachedDisassembly; 3092292SN/A } 3102292SN/A 3112292SN/A /** 3122292SN/A * Execute this instruction under SimpleCPU model. 3132292SN/A */ 3142292SN/A virtual Fault execute(SimpleCPU *xc, Trace::InstRecord *traceData) = 0; 3152292SN/A 3162292SN/A /** 3173221Sktlim@umich.edu * Execute this instruction under InorderCPU model. 3183221Sktlim@umich.edu */ 3193221Sktlim@umich.edu virtual Fault execute(InorderCPU *xc, Trace::InstRecord *traceData) = 0; 3202292SN/A 3212292SN/A 3222292SN/A /** 3232292SN/A * Execute this instruction under FastCPU model. 3242292SN/A */ 3252292SN/A virtual Fault execute(FastCPU *xc, Trace::InstRecord *traceData) = 0; 3262292SN/A 3272292SN/A /** 3282292SN/A * Execute this instruction under detailed FullCPU model. 3291060SN/A */ 3302292SN/A virtual Fault execute(DynInst *xc, Trace::InstRecord *traceData) = 0; 3311060SN/A 3321060SN/A /** 3332292SN/A * Return the target address for a PC-relative branch. 3342292SN/A * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 3352292SN/A * should be true). 3362829Sksewell@umich.edu */ 3372829Sksewell@umich.edu virtual Addr branchTarget(Addr branchPC) const 3383093Sksewell@umich.edu { 3393093Sksewell@umich.edu panic("StaticInst::branchTarget() called on instruction " 3403093Sksewell@umich.edu "that is not a PC-relative branch."); 3413093Sksewell@umich.edu } 3423093Sksewell@umich.edu 3432292SN/A /** 3441060SN/A * Return the target address for an indirect branch (jump). The 3451060SN/A * register value is read from the supplied execution context, so 3461060SN/A * the result is valid only if the execution context is about to 3471755SN/A * execute the branch in question. Invalid if not an indirect 3481060SN/A * branch (i.e. isIndirectCtrl() should be true). 3491060SN/A */ 3501060SN/A virtual Addr branchTarget(ExecContext *xc) const 3511060SN/A { 3521060SN/A panic("StaticInst::branchTarget() called on instruction " 3531755SN/A "that is not an indirect branch."); 3541062SN/A } 3552733Sktlim@umich.edu 3562292SN/A /** 3572733Sktlim@umich.edu * Return true if the instruction is a control transfer, and if so, 3582292SN/A * return the target address as well. 3592292SN/A */ 3602292SN/A bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt); 3612292SN/A 3622292SN/A /** 3632292SN/A * Return string representation of disassembled instruction. 3642292SN/A * The default version of this function will call the internal 3652292SN/A * virtual generateDisassembly() function to get the string, 3662292SN/A * then cache it in #cachedDisassembly. If the disassembly 3672292SN/A * should not be cached, this function should be overridden directly. 3682292SN/A */ 3692292SN/A virtual const std::string &disassemble(Addr pc, 3702292SN/A const SymbolTable *symtab = 0) 3712292SN/A { 3722292SN/A if (!cachedDisassembly) 3732292SN/A cachedDisassembly = 3742292SN/A new std::string(generateDisassembly(pc, symtab)); 3752292SN/A 3762292SN/A return *cachedDisassembly; 3772292SN/A } 3782292SN/A 3792292SN/A /// Decoded instruction cache type. 3802292SN/A /// For now we're using a generic hash_map; this seems to work 3812292SN/A /// pretty well. 3822292SN/A typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache; 3832292SN/A 3842292SN/A /// A cache of decoded instruction objects. 3852292SN/A static DecodeCache decodeCache; 3862292SN/A 3872292SN/A /** 3882292SN/A * Dump some basic stats on the decode cache hash map. 3892292SN/A * Only gets called if DECODE_CACHE_HASH_STATS is defined. 3902292SN/A */ 3912292SN/A static void dumpDecodeCacheStats(); 3922292SN/A 3932292SN/A /// Decode a machine instruction. 3942292SN/A /// @param mach_inst The binary instruction to decode. 3952292SN/A /// @retval A pointer to the corresponding StaticInst object. 3962292SN/A static 3972292SN/A StaticInstPtr<ISA> decode(MachInst mach_inst) 3982292SN/A { 3992292SN/A#ifdef DECODE_CACHE_HASH_STATS 4002292SN/A // Simple stats on decode hash_map. Turns out the default 4012292SN/A // hash function is as good as anything I could come up with. 4022292SN/A const int dump_every_n = 10000000; 4032292SN/A static int decodes_til_dump = dump_every_n; 4042292SN/A 4052292SN/A if (--decodes_til_dump == 0) { 4062292SN/A dumpDecodeCacheStats(); 4071062SN/A decodes_til_dump = dump_every_n; 4081062SN/A } 4091062SN/A#endif 4102871Sktlim@umich.edu 4112871Sktlim@umich.edu typename DecodeCache::iterator iter = decodeCache.find(mach_inst); 4122871Sktlim@umich.edu if (iter != decodeCache.end()) { 4132871Sktlim@umich.edu return iter->second; 4142871Sktlim@umich.edu } 4152871Sktlim@umich.edu 4162871Sktlim@umich.edu StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst); 4172871Sktlim@umich.edu decodeCache[mach_inst] = si; 4182871Sktlim@umich.edu return si; 4192871Sktlim@umich.edu } 4202871Sktlim@umich.edu}; 4212871Sktlim@umich.edu 4221062SN/Atypedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 4231755SN/A 4241060SN/A/// Reference-counted pointer to a StaticInst object. 4252733Sktlim@umich.edu/// This type should be used instead of "StaticInst<ISA> *" so that 4261060SN/A/// StaticInst objects can be properly reference-counted. 4272292SN/Atemplate <class ISA> 4282292SN/Aclass StaticInstPtr : public RefCountingPtr<StaticInst<ISA> > 4292325SN/A{ 4302292SN/A public: 4312292SN/A /// Constructor. 4321060SN/A StaticInstPtr() 4331060SN/A : RefCountingPtr<StaticInst<ISA> >() 4341060SN/A { 4351060SN/A } 4361060SN/A 4371060SN/A /// Conversion from "StaticInst<ISA> *". 4381060SN/A StaticInstPtr(StaticInst<ISA> *p) 4391060SN/A : RefCountingPtr<StaticInst<ISA> >(p) 4401060SN/A { 4411060SN/A } 4422292SN/A 4432292SN/A /// Copy constructor. 4442292SN/A StaticInstPtr(const StaticInstPtr &r) 4452292SN/A : RefCountingPtr<StaticInst<ISA> >(r) 4462292SN/A { 4471060SN/A } 4481060SN/A 4491060SN/A /// Construct directly from machine instruction. 4501060SN/A /// Calls StaticInst<ISA>::decode(). 4511060SN/A StaticInstPtr(typename ISA::MachInst mach_inst) 4521060SN/A : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst)) 4531060SN/A { 4542325SN/A } 4552292SN/A 4562292SN/A /// Convert to pointer to StaticInstBase class. 4572292SN/A operator const StaticInstBasePtr() 4582292SN/A { 4592292SN/A return get(); 4602325SN/A } 4612867Sktlim@umich.edu}; 4622905Sktlim@umich.edu 4633226Sktlim@umich.edu#endif // __STATIC_INST_HH__ 4642325SN/A