static_inst.hh revision 10934:5af8f40d8f2c 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48
49// forward declarations
50class Packet;
51
52class ExecContext;
53
54class SymbolTable;
55
56namespace Trace {
57    class InstRecord;
58}
59
60/**
61 * Base, ISA-independent static instruction class.
62 *
63 * The main component of this class is the vector of flags and the
64 * associated methods for reading them.  Any object that can rely
65 * solely on these flags can process instructions without being
66 * recompiled for multiple ISAs.
67 */
68class StaticInst : public RefCounted, public StaticInstFlags
69{
70  public:
71    /// Binary extended machine instruction type.
72    typedef TheISA::ExtMachInst ExtMachInst;
73    /// Logical register index type.
74    typedef TheISA::RegIndex RegIndex;
75
76    enum {
77        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
78        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
79    };
80
81  protected:
82
83    /// Flag values for this instruction.
84    std::bitset<Num_Flags> flags;
85
86    /// See opClass().
87    OpClass _opClass;
88
89    /// See numSrcRegs().
90    int8_t _numSrcRegs;
91
92    /// See numDestRegs().
93    int8_t _numDestRegs;
94
95    /// The following are used to track physical register usage
96    /// for machines with separate int & FP reg files.
97    //@{
98    int8_t _numFPDestRegs;
99    int8_t _numIntDestRegs;
100    int8_t _numCCDestRegs;
101    int8_t _numVectorDestRegs;
102    //@}
103
104  public:
105
106    /// @name Register information.
107    /// The sum of numFPDestRegs() and numIntDestRegs() equals
108    /// numDestRegs().  The former two functions are used to track
109    /// physical register usage for machines with separate int & FP
110    /// reg files.
111    //@{
112    /// Number of source registers.
113    int8_t numSrcRegs()  const { return _numSrcRegs; }
114    /// Number of destination registers.
115    int8_t numDestRegs() const { return _numDestRegs; }
116    /// Number of floating-point destination regs.
117    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
118    /// Number of integer destination regs.
119    int8_t numIntDestRegs() const { return _numIntDestRegs; }
120    /// Number of condition code destination regs.
121    int8_t numCCDestRegs() const { return _numCCDestRegs; }
122    /// Number of vector destination regs.
123    int8_t numVectorDestRegs() const { return _numVectorDestRegs; }
124    //@}
125
126    /// @name Flag accessors.
127    /// These functions are used to access the values of the various
128    /// instruction property flags.  See StaticInst::Flags for descriptions
129    /// of the individual flags.
130    //@{
131
132    bool isNop()          const { return flags[IsNop]; }
133
134    bool isMemRef()       const { return flags[IsMemRef]; }
135    bool isLoad()         const { return flags[IsLoad]; }
136    bool isStore()        const { return flags[IsStore]; }
137    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
138    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
139    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
140    bool isPrefetch()     const { return isInstPrefetch() ||
141                                         isDataPrefetch(); }
142
143    bool isInteger()      const { return flags[IsInteger]; }
144    bool isFloating()     const { return flags[IsFloating]; }
145    bool isVector() const { return flags[IsVector]; }
146    bool isCC()           const { return flags[IsCC]; }
147
148    bool isControl()      const { return flags[IsControl]; }
149    bool isCall()         const { return flags[IsCall]; }
150    bool isReturn()       const { return flags[IsReturn]; }
151    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
152    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
153    bool isCondCtrl()     const { return flags[IsCondControl]; }
154    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
155    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
156
157    bool isThreadSync()   const { return flags[IsThreadSync]; }
158    bool isSerializing()  const { return flags[IsSerializing] ||
159                                      flags[IsSerializeBefore] ||
160                                      flags[IsSerializeAfter]; }
161    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
162    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
163    bool isSquashAfter() const { return flags[IsSquashAfter]; }
164    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
165    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
166    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
167    bool isQuiesce() const { return flags[IsQuiesce]; }
168    bool isIprAccess() const { return flags[IsIprAccess]; }
169    bool isUnverifiable() const { return flags[IsUnverifiable]; }
170    bool isSyscall() const { return flags[IsSyscall]; }
171    bool isMacroop() const { return flags[IsMacroop]; }
172    bool isMicroop() const { return flags[IsMicroop]; }
173    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
174    bool isLastMicroop() const { return flags[IsLastMicroop]; }
175    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
176    //This flag doesn't do anything yet
177    bool isMicroBranch() const { return flags[IsMicroBranch]; }
178    //@}
179
180    void setFirstMicroop() { flags[IsFirstMicroop] = true; }
181    void setLastMicroop() { flags[IsLastMicroop] = true; }
182    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
183    void setFlag(Flags f) { flags[f] = true; }
184
185    /// Operation class.  Used to select appropriate function unit in issue.
186    OpClass opClass()     const { return _opClass; }
187
188
189    /// Return logical index (architectural reg num) of i'th destination reg.
190    /// Only the entries from 0 through numDestRegs()-1 are valid.
191    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
192
193    /// Return logical index (architectural reg num) of i'th source reg.
194    /// Only the entries from 0 through numSrcRegs()-1 are valid.
195    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
196
197    /// Pointer to a statically allocated "null" instruction object.
198    /// Used to give eaCompInst() and memAccInst() something to return
199    /// when called on non-memory instructions.
200    static StaticInstPtr nullStaticInstPtr;
201
202    /**
203     * Memory references only: returns "fake" instruction representing
204     * the effective address part of the memory operation.  Used to
205     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
206     * just the EA computation.
207     */
208    virtual const
209    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
210
211    /**
212     * Memory references only: returns "fake" instruction representing
213     * the memory access part of the memory operation.  Used to
214     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
215     * just the memory access (not the EA computation).
216     */
217    virtual const
218    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
219
220    /// The binary machine instruction.
221    const ExtMachInst machInst;
222
223  protected:
224
225    /// See destRegIdx().
226    RegIndex _destRegIdx[MaxInstDestRegs];
227    /// See srcRegIdx().
228    RegIndex _srcRegIdx[MaxInstSrcRegs];
229
230    /**
231     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
232     * methods.  Also useful to readily identify instructions from
233     * within the debugger when #cachedDisassembly has not been
234     * initialized.
235     */
236    const char *mnemonic;
237
238    /**
239     * String representation of disassembly (lazily evaluated via
240     * disassemble()).
241     */
242    mutable std::string *cachedDisassembly;
243
244    /**
245     * Internal function to generate disassembly string.
246     */
247    virtual std::string
248    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
249
250    /// Constructor.
251    /// It's important to initialize everything here to a sane
252    /// default, since the decoder generally only overrides
253    /// the fields that are meaningful for the particular
254    /// instruction.
255    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
256        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
257          _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0),
258          _numVectorDestRegs(0), machInst(_machInst), mnemonic(_mnemonic),
259          cachedDisassembly(0)
260    { }
261
262  public:
263    virtual ~StaticInst();
264
265    virtual Fault execute(ExecContext *xc,
266                          Trace::InstRecord *traceData) const = 0;
267    virtual Fault eaComp(ExecContext *xc,
268                         Trace::InstRecord *traceData) const
269    {
270        panic("eaComp not defined!");
271    }
272
273    virtual Fault initiateAcc(ExecContext *xc,
274                              Trace::InstRecord *traceData) const
275    {
276        panic("initiateAcc not defined!");
277    }
278
279    virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
280                              Trace::InstRecord *traceData) const
281    {
282        panic("completeAcc not defined!");
283    }
284
285    virtual void advancePC(TheISA::PCState &pcState) const = 0;
286
287    /**
288     * Return the microop that goes with a particular micropc. This should
289     * only be defined/used in macroops which will contain microops
290     */
291    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
292
293    /**
294     * Return the target address for a PC-relative branch.
295     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
296     * should be true).
297     */
298    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
299
300    /**
301     * Return the target address for an indirect branch (jump).  The
302     * register value is read from the supplied thread context, so
303     * the result is valid only if the thread context is about to
304     * execute the branch in question.  Invalid if not an indirect
305     * branch (i.e. isIndirectCtrl() should be true).
306     */
307    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
308
309    /**
310     * Return true if the instruction is a control transfer, and if so,
311     * return the target address as well.
312     */
313    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
314                         TheISA::PCState &tgt) const;
315
316    /**
317     * Return string representation of disassembled instruction.
318     * The default version of this function will call the internal
319     * virtual generateDisassembly() function to get the string,
320     * then cache it in #cachedDisassembly.  If the disassembly
321     * should not be cached, this function should be overridden directly.
322     */
323    virtual const std::string &disassemble(Addr pc,
324        const SymbolTable *symtab = 0) const;
325
326    /**
327     * Print a separator separated list of this instruction's set flag
328     * names on the given stream.
329     */
330    void printFlags(std::ostream &outs, const std::string &separator) const;
331
332    /// Return name of machine instruction
333    std::string getName() const { return mnemonic; }
334};
335
336#endif // __CPU_STATIC_INST_HH__
337