static_inst.hh revision 10666:3c42be107634
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * Copyright (c) 2013 Advanced Micro Devices, Inc. 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292SN/A * Authors: Steve Reinhardt 302SN/A */ 315584Snate@binkert.org 322SN/A#ifndef __CPU_STATIC_INST_HH__ 338229Snate@binkert.org#define __CPU_STATIC_INST_HH__ 3456SN/A 352SN/A#include <bitset> 365584Snate@binkert.org#include <string> 372SN/A 3810055Sola.jeppsson@gmail.com#include "arch/registers.hh" 3910055Sola.jeppsson@gmail.com#include "arch/types.hh" 402SN/A#include "base/misc.hh" 412SN/A#include "base/refcnt.hh" 422SN/A#include "base/types.hh" 432SN/A#include "config/the_isa.hh" 442SN/A#include "cpu/op_class.hh" 452SN/A#include "cpu/static_inst_fwd.hh" 462SN/A#include "cpu/thread_context.hh" 472SN/A#include "enums/StaticInstFlags.hh" 482SN/A 492SN/A// forward declarations 502SN/Aclass Packet; 512SN/A 522SN/Aclass ExecContext; 532SN/A 542SN/Aclass SymbolTable; 552SN/A 562SN/Anamespace Trace { 572SN/A class InstRecord; 582SN/A} 592SN/A 602SN/A/** 612SN/A * Base, ISA-independent static instruction class. 622SN/A * 632SN/A * The main component of this class is the vector of flags and the 642SN/A * associated methods for reading them. Any object that can rely 652SN/A * solely on these flags can process instructions without being 662SN/A * recompiled for multiple ISAs. 672SN/A */ 682SN/Aclass StaticInst : public RefCounted, public StaticInstFlags 692SN/A{ 702SN/A public: 712SN/A /// Binary extended machine instruction type. 722SN/A typedef TheISA::ExtMachInst ExtMachInst; 732SN/A /// Logical register index type. 742SN/A typedef TheISA::RegIndex RegIndex; 752SN/A 762SN/A enum { 772SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 782SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 792SN/A }; 802SN/A 812SN/A protected: 82 83 /// Flag values for this instruction. 84 std::bitset<Num_Flags> flags; 85 86 /// See opClass(). 87 OpClass _opClass; 88 89 /// See numSrcRegs(). 90 int8_t _numSrcRegs; 91 92 /// See numDestRegs(). 93 int8_t _numDestRegs; 94 95 /// The following are used to track physical register usage 96 /// for machines with separate int & FP reg files. 97 //@{ 98 int8_t _numFPDestRegs; 99 int8_t _numIntDestRegs; 100 int8_t _numCCDestRegs; 101 //@} 102 103 public: 104 105 /// @name Register information. 106 /// The sum of numFPDestRegs() and numIntDestRegs() equals 107 /// numDestRegs(). The former two functions are used to track 108 /// physical register usage for machines with separate int & FP 109 /// reg files. 110 //@{ 111 /// Number of source registers. 112 int8_t numSrcRegs() const { return _numSrcRegs; } 113 /// Number of destination registers. 114 int8_t numDestRegs() const { return _numDestRegs; } 115 /// Number of floating-point destination regs. 116 int8_t numFPDestRegs() const { return _numFPDestRegs; } 117 /// Number of integer destination regs. 118 int8_t numIntDestRegs() const { return _numIntDestRegs; } 119 //@} 120 121 /// @name Flag accessors. 122 /// These functions are used to access the values of the various 123 /// instruction property flags. See StaticInst::Flags for descriptions 124 /// of the individual flags. 125 //@{ 126 127 bool isNop() const { return flags[IsNop]; } 128 129 bool isMemRef() const { return flags[IsMemRef]; } 130 bool isLoad() const { return flags[IsLoad]; } 131 bool isStore() const { return flags[IsStore]; } 132 bool isStoreConditional() const { return flags[IsStoreConditional]; } 133 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 134 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 135 bool isPrefetch() const { return isInstPrefetch() || 136 isDataPrefetch(); } 137 138 bool isInteger() const { return flags[IsInteger]; } 139 bool isFloating() const { return flags[IsFloating]; } 140 bool isCC() const { return flags[IsCC]; } 141 142 bool isControl() const { return flags[IsControl]; } 143 bool isCall() const { return flags[IsCall]; } 144 bool isReturn() const { return flags[IsReturn]; } 145 bool isDirectCtrl() const { return flags[IsDirectControl]; } 146 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 147 bool isCondCtrl() const { return flags[IsCondControl]; } 148 bool isUncondCtrl() const { return flags[IsUncondControl]; } 149 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 150 151 bool isThreadSync() const { return flags[IsThreadSync]; } 152 bool isSerializing() const { return flags[IsSerializing] || 153 flags[IsSerializeBefore] || 154 flags[IsSerializeAfter]; } 155 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 156 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 157 bool isSquashAfter() const { return flags[IsSquashAfter]; } 158 bool isMemBarrier() const { return flags[IsMemBarrier]; } 159 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 160 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 161 bool isQuiesce() const { return flags[IsQuiesce]; } 162 bool isIprAccess() const { return flags[IsIprAccess]; } 163 bool isUnverifiable() const { return flags[IsUnverifiable]; } 164 bool isSyscall() const { return flags[IsSyscall]; } 165 bool isMacroop() const { return flags[IsMacroop]; } 166 bool isMicroop() const { return flags[IsMicroop]; } 167 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 168 bool isLastMicroop() const { return flags[IsLastMicroop]; } 169 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 170 //This flag doesn't do anything yet 171 bool isMicroBranch() const { return flags[IsMicroBranch]; } 172 //@} 173 174 void setFirstMicroop() { flags[IsFirstMicroop] = true; } 175 void setLastMicroop() { flags[IsLastMicroop] = true; } 176 void setDelayedCommit() { flags[IsDelayedCommit] = true; } 177 void setFlag(Flags f) { flags[f] = true; } 178 179 /// Operation class. Used to select appropriate function unit in issue. 180 OpClass opClass() const { return _opClass; } 181 182 183 /// Return logical index (architectural reg num) of i'th destination reg. 184 /// Only the entries from 0 through numDestRegs()-1 are valid. 185 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 186 187 /// Return logical index (architectural reg num) of i'th source reg. 188 /// Only the entries from 0 through numSrcRegs()-1 are valid. 189 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 190 191 /// Pointer to a statically allocated "null" instruction object. 192 /// Used to give eaCompInst() and memAccInst() something to return 193 /// when called on non-memory instructions. 194 static StaticInstPtr nullStaticInstPtr; 195 196 /** 197 * Memory references only: returns "fake" instruction representing 198 * the effective address part of the memory operation. Used to 199 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 200 * just the EA computation. 201 */ 202 virtual const 203 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 204 205 /** 206 * Memory references only: returns "fake" instruction representing 207 * the memory access part of the memory operation. Used to 208 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 209 * just the memory access (not the EA computation). 210 */ 211 virtual const 212 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 213 214 /// The binary machine instruction. 215 const ExtMachInst machInst; 216 217 protected: 218 219 /// See destRegIdx(). 220 RegIndex _destRegIdx[MaxInstDestRegs]; 221 /// See srcRegIdx(). 222 RegIndex _srcRegIdx[MaxInstSrcRegs]; 223 224 /** 225 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 226 * methods. Also useful to readily identify instructions from 227 * within the debugger when #cachedDisassembly has not been 228 * initialized. 229 */ 230 const char *mnemonic; 231 232 /** 233 * String representation of disassembly (lazily evaluated via 234 * disassemble()). 235 */ 236 mutable std::string *cachedDisassembly; 237 238 /** 239 * Internal function to generate disassembly string. 240 */ 241 virtual std::string 242 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 243 244 /// Constructor. 245 /// It's important to initialize everything here to a sane 246 /// default, since the decoder generally only overrides 247 /// the fields that are meaningful for the particular 248 /// instruction. 249 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 250 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 251 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), 252 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 253 { } 254 255 public: 256 virtual ~StaticInst(); 257 258 virtual Fault execute(ExecContext *xc, 259 Trace::InstRecord *traceData) const = 0; 260 virtual Fault eaComp(ExecContext *xc, 261 Trace::InstRecord *traceData) const 262 { 263 panic("eaComp not defined!"); 264 } 265 266 virtual Fault initiateAcc(ExecContext *xc, 267 Trace::InstRecord *traceData) const 268 { 269 panic("initiateAcc not defined!"); 270 } 271 272 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, 273 Trace::InstRecord *traceData) const 274 { 275 panic("completeAcc not defined!"); 276 } 277 278 virtual void advancePC(TheISA::PCState &pcState) const = 0; 279 280 /** 281 * Return the microop that goes with a particular micropc. This should 282 * only be defined/used in macroops which will contain microops 283 */ 284 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 285 286 /** 287 * Return the target address for a PC-relative branch. 288 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 289 * should be true). 290 */ 291 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 292 293 /** 294 * Return the target address for an indirect branch (jump). The 295 * register value is read from the supplied thread context, so 296 * the result is valid only if the thread context is about to 297 * execute the branch in question. Invalid if not an indirect 298 * branch (i.e. isIndirectCtrl() should be true). 299 */ 300 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 301 302 /** 303 * Return true if the instruction is a control transfer, and if so, 304 * return the target address as well. 305 */ 306 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 307 TheISA::PCState &tgt) const; 308 309 /** 310 * Return string representation of disassembled instruction. 311 * The default version of this function will call the internal 312 * virtual generateDisassembly() function to get the string, 313 * then cache it in #cachedDisassembly. If the disassembly 314 * should not be cached, this function should be overridden directly. 315 */ 316 virtual const std::string &disassemble(Addr pc, 317 const SymbolTable *symtab = 0) const; 318 319 /** 320 * Print a separator separated list of this instruction's set flag 321 * names on the given stream. 322 */ 323 void printFlags(std::ostream &outs, const std::string &separator) const; 324 325 /// Return name of machine instruction 326 std::string getName() { return mnemonic; } 327}; 328 329#endif // __CPU_STATIC_INST_HH__ 330