static_inst.hh revision 10474:799c8ee4ecba 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48
49// forward declarations
50class Packet;
51
52class ExecContext;
53
54class SymbolTable;
55
56namespace Trace {
57    class InstRecord;
58}
59
60/**
61 * Base, ISA-independent static instruction class.
62 *
63 * The main component of this class is the vector of flags and the
64 * associated methods for reading them.  Any object that can rely
65 * solely on these flags can process instructions without being
66 * recompiled for multiple ISAs.
67 */
68class StaticInst : public RefCounted, public StaticInstFlags
69{
70  public:
71    /// Binary extended machine instruction type.
72    typedef TheISA::ExtMachInst ExtMachInst;
73    /// Logical register index type.
74    typedef TheISA::RegIndex RegIndex;
75
76    enum {
77        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
78        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
79    };
80
81  protected:
82
83    /// Flag values for this instruction.
84    std::bitset<Num_Flags> flags;
85
86    /// See opClass().
87    OpClass _opClass;
88
89    /// See numSrcRegs().
90    int8_t _numSrcRegs;
91
92    /// See numDestRegs().
93    int8_t _numDestRegs;
94
95    /// The following are used to track physical register usage
96    /// for machines with separate int & FP reg files.
97    //@{
98    int8_t _numFPDestRegs;
99    int8_t _numIntDestRegs;
100    int8_t _numCCDestRegs;
101    //@}
102
103  public:
104
105    /// @name Register information.
106    /// The sum of numFPDestRegs() and numIntDestRegs() equals
107    /// numDestRegs().  The former two functions are used to track
108    /// physical register usage for machines with separate int & FP
109    /// reg files.
110    //@{
111    /// Number of source registers.
112    int8_t numSrcRegs()  const { return _numSrcRegs; }
113    /// Number of destination registers.
114    int8_t numDestRegs() const { return _numDestRegs; }
115    /// Number of floating-point destination regs.
116    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
117    /// Number of integer destination regs.
118    int8_t numIntDestRegs() const { return _numIntDestRegs; }
119    //@}
120
121    /// @name Flag accessors.
122    /// These functions are used to access the values of the various
123    /// instruction property flags.  See StaticInst::Flags for descriptions
124    /// of the individual flags.
125    //@{
126
127    bool isNop()          const { return flags[IsNop]; }
128
129    bool isMemRef()       const { return flags[IsMemRef]; }
130    bool isLoad()         const { return flags[IsLoad]; }
131    bool isStore()        const { return flags[IsStore]; }
132    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
133    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
134    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
135    bool isPrefetch()     const { return isInstPrefetch() ||
136                                         isDataPrefetch(); }
137
138    bool isInteger()      const { return flags[IsInteger]; }
139    bool isFloating()     const { return flags[IsFloating]; }
140    bool isCC()           const { return flags[IsCC]; }
141
142    bool isControl()      const { return flags[IsControl]; }
143    bool isCall()         const { return flags[IsCall]; }
144    bool isReturn()       const { return flags[IsReturn]; }
145    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
146    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
147    bool isCondCtrl()     const { return flags[IsCondControl]; }
148    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
149    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
150
151    bool isThreadSync()   const { return flags[IsThreadSync]; }
152    bool isSerializing()  const { return flags[IsSerializing] ||
153                                      flags[IsSerializeBefore] ||
154                                      flags[IsSerializeAfter]; }
155    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
156    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
157    bool isSquashAfter() const { return flags[IsSquashAfter]; }
158    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
159    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
160    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
161    bool isQuiesce() const { return flags[IsQuiesce]; }
162    bool isIprAccess() const { return flags[IsIprAccess]; }
163    bool isUnverifiable() const { return flags[IsUnverifiable]; }
164    bool isSyscall() const { return flags[IsSyscall]; }
165    bool isMacroop() const { return flags[IsMacroop]; }
166    bool isMicroop() const { return flags[IsMicroop]; }
167    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
168    bool isLastMicroop() const { return flags[IsLastMicroop]; }
169    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
170    //This flag doesn't do anything yet
171    bool isMicroBranch() const { return flags[IsMicroBranch]; }
172    //@}
173
174    void setLastMicroop() { flags[IsLastMicroop] = true; }
175    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
176    void setFlag(Flags f) { flags[f] = true; }
177
178    /// Operation class.  Used to select appropriate function unit in issue.
179    OpClass opClass()     const { return _opClass; }
180
181
182    /// Return logical index (architectural reg num) of i'th destination reg.
183    /// Only the entries from 0 through numDestRegs()-1 are valid.
184    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
185
186    /// Return logical index (architectural reg num) of i'th source reg.
187    /// Only the entries from 0 through numSrcRegs()-1 are valid.
188    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
189
190    /// Pointer to a statically allocated "null" instruction object.
191    /// Used to give eaCompInst() and memAccInst() something to return
192    /// when called on non-memory instructions.
193    static StaticInstPtr nullStaticInstPtr;
194
195    /**
196     * Memory references only: returns "fake" instruction representing
197     * the effective address part of the memory operation.  Used to
198     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
199     * just the EA computation.
200     */
201    virtual const
202    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
203
204    /**
205     * Memory references only: returns "fake" instruction representing
206     * the memory access part of the memory operation.  Used to
207     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
208     * just the memory access (not the EA computation).
209     */
210    virtual const
211    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
212
213    /// The binary machine instruction.
214    const ExtMachInst machInst;
215
216  protected:
217
218    /// See destRegIdx().
219    RegIndex _destRegIdx[MaxInstDestRegs];
220    /// See srcRegIdx().
221    RegIndex _srcRegIdx[MaxInstSrcRegs];
222
223    /**
224     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
225     * methods.  Also useful to readily identify instructions from
226     * within the debugger when #cachedDisassembly has not been
227     * initialized.
228     */
229    const char *mnemonic;
230
231    /**
232     * String representation of disassembly (lazily evaluated via
233     * disassemble()).
234     */
235    mutable std::string *cachedDisassembly;
236
237    /**
238     * Internal function to generate disassembly string.
239     */
240    virtual std::string
241    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
242
243    /// Constructor.
244    /// It's important to initialize everything here to a sane
245    /// default, since the decoder generally only overrides
246    /// the fields that are meaningful for the particular
247    /// instruction.
248    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
249        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
250          _numFPDestRegs(0), _numIntDestRegs(0),
251          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
252    { }
253
254  public:
255    virtual ~StaticInst();
256
257    virtual Fault execute(ExecContext *xc,
258                          Trace::InstRecord *traceData) const = 0;
259    virtual Fault eaComp(ExecContext *xc,
260                         Trace::InstRecord *traceData) const
261    {
262        panic("eaComp not defined!");
263    }
264
265    virtual Fault initiateAcc(ExecContext *xc,
266                              Trace::InstRecord *traceData) const
267    {
268        panic("initiateAcc not defined!");
269    }
270
271    virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
272                              Trace::InstRecord *traceData) const
273    {
274        panic("completeAcc not defined!");
275    }
276
277    virtual void advancePC(TheISA::PCState &pcState) const = 0;
278
279    /**
280     * Return the microop that goes with a particular micropc. This should
281     * only be defined/used in macroops which will contain microops
282     */
283    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
284
285    /**
286     * Return the target address for a PC-relative branch.
287     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
288     * should be true).
289     */
290    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
291
292    /**
293     * Return the target address for an indirect branch (jump).  The
294     * register value is read from the supplied thread context, so
295     * the result is valid only if the thread context is about to
296     * execute the branch in question.  Invalid if not an indirect
297     * branch (i.e. isIndirectCtrl() should be true).
298     */
299    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
300
301    /**
302     * Return true if the instruction is a control transfer, and if so,
303     * return the target address as well.
304     */
305    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
306                         TheISA::PCState &tgt) const;
307
308    /**
309     * Return string representation of disassembled instruction.
310     * The default version of this function will call the internal
311     * virtual generateDisassembly() function to get the string,
312     * then cache it in #cachedDisassembly.  If the disassembly
313     * should not be cached, this function should be overridden directly.
314     */
315    virtual const std::string &disassemble(Addr pc,
316        const SymbolTable *symtab = 0) const;
317
318    /**
319     * Print a separator separated list of this instruction's set flag
320     * names on the given stream.
321     */
322    void printFlags(std::ostream &outs, const std::string &separator) const;
323
324    /// Return name of machine instruction
325    std::string getName() { return mnemonic; }
326};
327
328#endif // __CPU_STATIC_INST_HH__
329