static_inst.hh revision 10319 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48#include "sim/fault_fwd.hh"
49
50// forward declarations
51class Packet;
52
53class ExecContext;
54
55class SymbolTable;
56
57namespace Trace {
58    class InstRecord;
59}
60
61/**
62 * Base, ISA-independent static instruction class.
63 *
64 * The main component of this class is the vector of flags and the
65 * associated methods for reading them.  Any object that can rely
66 * solely on these flags can process instructions without being
67 * recompiled for multiple ISAs.
68 */
69class StaticInst : public RefCounted, public StaticInstFlags
70{
71  public:
72    /// Binary extended machine instruction type.
73    typedef TheISA::ExtMachInst ExtMachInst;
74    /// Logical register index type.
75    typedef TheISA::RegIndex RegIndex;
76
77    enum {
78        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
79        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
80    };
81
82  protected:
83
84    /// Flag values for this instruction.
85    std::bitset<Num_Flags> flags;
86
87    /// See opClass().
88    OpClass _opClass;
89
90    /// See numSrcRegs().
91    int8_t _numSrcRegs;
92
93    /// See numDestRegs().
94    int8_t _numDestRegs;
95
96    /// The following are used to track physical register usage
97    /// for machines with separate int & FP reg files.
98    //@{
99    int8_t _numFPDestRegs;
100    int8_t _numIntDestRegs;
101    int8_t _numCCDestRegs;
102    //@}
103
104  public:
105
106    /// @name Register information.
107    /// The sum of numFPDestRegs() and numIntDestRegs() equals
108    /// numDestRegs().  The former two functions are used to track
109    /// physical register usage for machines with separate int & FP
110    /// reg files.
111    //@{
112    /// Number of source registers.
113    int8_t numSrcRegs()  const { return _numSrcRegs; }
114    /// Number of destination registers.
115    int8_t numDestRegs() const { return _numDestRegs; }
116    /// Number of floating-point destination regs.
117    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
118    /// Number of integer destination regs.
119    int8_t numIntDestRegs() const { return _numIntDestRegs; }
120    //@}
121
122    /// @name Flag accessors.
123    /// These functions are used to access the values of the various
124    /// instruction property flags.  See StaticInst::Flags for descriptions
125    /// of the individual flags.
126    //@{
127
128    bool isNop()          const { return flags[IsNop]; }
129
130    bool isMemRef()       const { return flags[IsMemRef]; }
131    bool isLoad()         const { return flags[IsLoad]; }
132    bool isStore()        const { return flags[IsStore]; }
133    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
134    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
135    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
136    bool isPrefetch()     const { return isInstPrefetch() ||
137                                         isDataPrefetch(); }
138
139    bool isInteger()      const { return flags[IsInteger]; }
140    bool isFloating()     const { return flags[IsFloating]; }
141    bool isCC()           const { return flags[IsCC]; }
142
143    bool isControl()      const { return flags[IsControl]; }
144    bool isCall()         const { return flags[IsCall]; }
145    bool isReturn()       const { return flags[IsReturn]; }
146    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
147    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
148    bool isCondCtrl()     const { return flags[IsCondControl]; }
149    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
150    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
151
152    bool isThreadSync()   const { return flags[IsThreadSync]; }
153    bool isSerializing()  const { return flags[IsSerializing] ||
154                                      flags[IsSerializeBefore] ||
155                                      flags[IsSerializeAfter]; }
156    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
157    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
158    bool isSquashAfter() const { return flags[IsSquashAfter]; }
159    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
160    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
161    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
162    bool isQuiesce() const { return flags[IsQuiesce]; }
163    bool isIprAccess() const { return flags[IsIprAccess]; }
164    bool isUnverifiable() const { return flags[IsUnverifiable]; }
165    bool isSyscall() const { return flags[IsSyscall]; }
166    bool isMacroop() const { return flags[IsMacroop]; }
167    bool isMicroop() const { return flags[IsMicroop]; }
168    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
169    bool isLastMicroop() const { return flags[IsLastMicroop]; }
170    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
171    //This flag doesn't do anything yet
172    bool isMicroBranch() const { return flags[IsMicroBranch]; }
173    //@}
174
175    void setLastMicroop() { flags[IsLastMicroop] = true; }
176    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
177    void setFlag(Flags f) { flags[f] = true; }
178
179    /// Operation class.  Used to select appropriate function unit in issue.
180    OpClass opClass()     const { return _opClass; }
181
182
183    /// Return logical index (architectural reg num) of i'th destination reg.
184    /// Only the entries from 0 through numDestRegs()-1 are valid.
185    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
186
187    /// Return logical index (architectural reg num) of i'th source reg.
188    /// Only the entries from 0 through numSrcRegs()-1 are valid.
189    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
190
191    /// Pointer to a statically allocated "null" instruction object.
192    /// Used to give eaCompInst() and memAccInst() something to return
193    /// when called on non-memory instructions.
194    static StaticInstPtr nullStaticInstPtr;
195
196    /**
197     * Memory references only: returns "fake" instruction representing
198     * the effective address part of the memory operation.  Used to
199     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
200     * just the EA computation.
201     */
202    virtual const
203    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
204
205    /**
206     * Memory references only: returns "fake" instruction representing
207     * the memory access part of the memory operation.  Used to
208     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
209     * just the memory access (not the EA computation).
210     */
211    virtual const
212    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
213
214    /// The binary machine instruction.
215    const ExtMachInst machInst;
216
217  protected:
218
219    /// See destRegIdx().
220    RegIndex _destRegIdx[MaxInstDestRegs];
221    /// See srcRegIdx().
222    RegIndex _srcRegIdx[MaxInstSrcRegs];
223
224    /**
225     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
226     * methods.  Also useful to readily identify instructions from
227     * within the debugger when #cachedDisassembly has not been
228     * initialized.
229     */
230    const char *mnemonic;
231
232    /**
233     * String representation of disassembly (lazily evaluated via
234     * disassemble()).
235     */
236    mutable std::string *cachedDisassembly;
237
238    /**
239     * Internal function to generate disassembly string.
240     */
241    virtual std::string
242    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
243
244    /// Constructor.
245    /// It's important to initialize everything here to a sane
246    /// default, since the decoder generally only overrides
247    /// the fields that are meaningful for the particular
248    /// instruction.
249    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
250        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
251          _numFPDestRegs(0), _numIntDestRegs(0),
252          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
253    { }
254
255  public:
256    virtual ~StaticInst();
257
258    virtual Fault execute(ExecContext *xc,
259                          Trace::InstRecord *traceData) const = 0;
260    virtual Fault eaComp(ExecContext *xc,
261                         Trace::InstRecord *traceData) const
262    {
263        panic("eaComp not defined!");
264    }
265
266    virtual Fault initiateAcc(ExecContext *xc,
267                              Trace::InstRecord *traceData) const
268    {
269        panic("initiateAcc not defined!");
270    }
271
272    virtual Fault completeAcc(Packet *pkt, ExecContext *xc,
273                              Trace::InstRecord *traceData) const
274    {
275        panic("completeAcc not defined!");
276    }
277
278    virtual void advancePC(TheISA::PCState &pcState) const = 0;
279
280    /**
281     * Return the microop that goes with a particular micropc. This should
282     * only be defined/used in macroops which will contain microops
283     */
284    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
285
286    /**
287     * Return the target address for a PC-relative branch.
288     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
289     * should be true).
290     */
291    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
292
293    /**
294     * Return the target address for an indirect branch (jump).  The
295     * register value is read from the supplied thread context, so
296     * the result is valid only if the thread context is about to
297     * execute the branch in question.  Invalid if not an indirect
298     * branch (i.e. isIndirectCtrl() should be true).
299     */
300    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
301
302    /**
303     * Return true if the instruction is a control transfer, and if so,
304     * return the target address as well.
305     */
306    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
307                         TheISA::PCState &tgt) const;
308
309    /**
310     * Return string representation of disassembled instruction.
311     * The default version of this function will call the internal
312     * virtual generateDisassembly() function to get the string,
313     * then cache it in #cachedDisassembly.  If the disassembly
314     * should not be cached, this function should be overridden directly.
315     */
316    virtual const std::string &disassemble(Addr pc,
317        const SymbolTable *symtab = 0) const;
318
319    /**
320     * Print a separator separated list of this instruction's set flag
321     * names on the given stream.
322     */
323    void printFlags(std::ostream &outs, const std::string &separator) const;
324
325    /// Return name of machine instruction
326    std::string getName() { return mnemonic; }
327};
328
329#endif // __CPU_STATIC_INST_HH__
330