static_inst.hh revision 10201:30a20d2072c1 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 */
31
32#ifndef __CPU_STATIC_INST_HH__
33#define __CPU_STATIC_INST_HH__
34
35#include <bitset>
36#include <string>
37
38#include "arch/registers.hh"
39#include "arch/types.hh"
40#include "base/misc.hh"
41#include "base/refcnt.hh"
42#include "base/types.hh"
43#include "config/the_isa.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst_fwd.hh"
46#include "cpu/thread_context.hh"
47#include "enums/StaticInstFlags.hh"
48#include "sim/fault_fwd.hh"
49
50// forward declarations
51class Packet;
52
53struct O3CPUImpl;
54template <class Impl> class BaseO3DynInst;
55typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
56class InOrderDynInst;
57
58class CheckerCPU;
59class AtomicSimpleCPU;
60class TimingSimpleCPU;
61class InorderCPU;
62class SymbolTable;
63
64namespace Trace {
65    class InstRecord;
66}
67
68/**
69 * Base, ISA-independent static instruction class.
70 *
71 * The main component of this class is the vector of flags and the
72 * associated methods for reading them.  Any object that can rely
73 * solely on these flags can process instructions without being
74 * recompiled for multiple ISAs.
75 */
76class StaticInst : public RefCounted, public StaticInstFlags
77{
78  public:
79    /// Binary extended machine instruction type.
80    typedef TheISA::ExtMachInst ExtMachInst;
81    /// Logical register index type.
82    typedef TheISA::RegIndex RegIndex;
83
84    enum {
85        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
86        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
87    };
88
89  protected:
90
91    /// Flag values for this instruction.
92    std::bitset<Num_Flags> flags;
93
94    /// See opClass().
95    OpClass _opClass;
96
97    /// See numSrcRegs().
98    int8_t _numSrcRegs;
99
100    /// See numDestRegs().
101    int8_t _numDestRegs;
102
103    /// The following are used to track physical register usage
104    /// for machines with separate int & FP reg files.
105    //@{
106    int8_t _numFPDestRegs;
107    int8_t _numIntDestRegs;
108    int8_t _numCCDestRegs;
109    //@}
110
111  public:
112
113    /// @name Register information.
114    /// The sum of numFPDestRegs() and numIntDestRegs() equals
115    /// numDestRegs().  The former two functions are used to track
116    /// physical register usage for machines with separate int & FP
117    /// reg files.
118    //@{
119    /// Number of source registers.
120    int8_t numSrcRegs()  const { return _numSrcRegs; }
121    /// Number of destination registers.
122    int8_t numDestRegs() const { return _numDestRegs; }
123    /// Number of floating-point destination regs.
124    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
125    /// Number of integer destination regs.
126    int8_t numIntDestRegs() const { return _numIntDestRegs; }
127    //@}
128
129    /// @name Flag accessors.
130    /// These functions are used to access the values of the various
131    /// instruction property flags.  See StaticInst::Flags for descriptions
132    /// of the individual flags.
133    //@{
134
135    bool isNop()          const { return flags[IsNop]; }
136
137    bool isMemRef()       const { return flags[IsMemRef]; }
138    bool isLoad()         const { return flags[IsLoad]; }
139    bool isStore()        const { return flags[IsStore]; }
140    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
141    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
142    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
143    bool isPrefetch()     const { return isInstPrefetch() ||
144                                         isDataPrefetch(); }
145
146    bool isInteger()      const { return flags[IsInteger]; }
147    bool isFloating()     const { return flags[IsFloating]; }
148    bool isCC()           const { return flags[IsCC]; }
149
150    bool isControl()      const { return flags[IsControl]; }
151    bool isCall()         const { return flags[IsCall]; }
152    bool isReturn()       const { return flags[IsReturn]; }
153    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
154    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
155    bool isCondCtrl()     const { return flags[IsCondControl]; }
156    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
157    bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; }
158
159    bool isThreadSync()   const { return flags[IsThreadSync]; }
160    bool isSerializing()  const { return flags[IsSerializing] ||
161                                      flags[IsSerializeBefore] ||
162                                      flags[IsSerializeAfter]; }
163    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
164    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
165    bool isSquashAfter() const { return flags[IsSquashAfter]; }
166    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
167    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
168    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
169    bool isQuiesce() const { return flags[IsQuiesce]; }
170    bool isIprAccess() const { return flags[IsIprAccess]; }
171    bool isUnverifiable() const { return flags[IsUnverifiable]; }
172    bool isSyscall() const { return flags[IsSyscall]; }
173    bool isMacroop() const { return flags[IsMacroop]; }
174    bool isMicroop() const { return flags[IsMicroop]; }
175    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
176    bool isLastMicroop() const { return flags[IsLastMicroop]; }
177    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
178    //This flag doesn't do anything yet
179    bool isMicroBranch() const { return flags[IsMicroBranch]; }
180    //@}
181
182    void setLastMicroop() { flags[IsLastMicroop] = true; }
183    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
184    void setFlag(Flags f) { flags[f] = true; }
185
186    /// Operation class.  Used to select appropriate function unit in issue.
187    OpClass opClass()     const { return _opClass; }
188
189
190    /// Return logical index (architectural reg num) of i'th destination reg.
191    /// Only the entries from 0 through numDestRegs()-1 are valid.
192    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
193
194    /// Return logical index (architectural reg num) of i'th source reg.
195    /// Only the entries from 0 through numSrcRegs()-1 are valid.
196    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
197
198    /// Pointer to a statically allocated "null" instruction object.
199    /// Used to give eaCompInst() and memAccInst() something to return
200    /// when called on non-memory instructions.
201    static StaticInstPtr nullStaticInstPtr;
202
203    /**
204     * Memory references only: returns "fake" instruction representing
205     * the effective address part of the memory operation.  Used to
206     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
207     * just the EA computation.
208     */
209    virtual const
210    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
211
212    /**
213     * Memory references only: returns "fake" instruction representing
214     * the memory access part of the memory operation.  Used to
215     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
216     * just the memory access (not the EA computation).
217     */
218    virtual const
219    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
220
221    /// The binary machine instruction.
222    const ExtMachInst machInst;
223
224  protected:
225
226    /// See destRegIdx().
227    RegIndex _destRegIdx[MaxInstDestRegs];
228    /// See srcRegIdx().
229    RegIndex _srcRegIdx[MaxInstSrcRegs];
230
231    /**
232     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
233     * methods.  Also useful to readily identify instructions from
234     * within the debugger when #cachedDisassembly has not been
235     * initialized.
236     */
237    const char *mnemonic;
238
239    /**
240     * String representation of disassembly (lazily evaluated via
241     * disassemble()).
242     */
243    mutable std::string *cachedDisassembly;
244
245    /**
246     * Internal function to generate disassembly string.
247     */
248    virtual std::string
249    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
250
251    /// Constructor.
252    /// It's important to initialize everything here to a sane
253    /// default, since the decoder generally only overrides
254    /// the fields that are meaningful for the particular
255    /// instruction.
256    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
257        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
258          _numFPDestRegs(0), _numIntDestRegs(0),
259          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
260    { }
261
262  public:
263    virtual ~StaticInst();
264
265/**
266 * The execute() signatures are auto-generated by scons based on the
267 * set of CPU models we are compiling in today.
268 */
269#include "cpu/static_inst_exec_sigs.hh"
270
271    virtual void advancePC(TheISA::PCState &pcState) const = 0;
272
273    /**
274     * Return the microop that goes with a particular micropc. This should
275     * only be defined/used in macroops which will contain microops
276     */
277    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
278
279    /**
280     * Return the target address for a PC-relative branch.
281     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
282     * should be true).
283     */
284    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
285
286    /**
287     * Return the target address for an indirect branch (jump).  The
288     * register value is read from the supplied thread context, so
289     * the result is valid only if the thread context is about to
290     * execute the branch in question.  Invalid if not an indirect
291     * branch (i.e. isIndirectCtrl() should be true).
292     */
293    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
294
295    /**
296     * Return true if the instruction is a control transfer, and if so,
297     * return the target address as well.
298     */
299    bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
300                         TheISA::PCState &tgt) const;
301
302    /**
303     * Return string representation of disassembled instruction.
304     * The default version of this function will call the internal
305     * virtual generateDisassembly() function to get the string,
306     * then cache it in #cachedDisassembly.  If the disassembly
307     * should not be cached, this function should be overridden directly.
308     */
309    virtual const std::string &disassemble(Addr pc,
310        const SymbolTable *symtab = 0) const;
311
312    /**
313     * Print a separator separated list of this instruction's set flag
314     * names on the given stream.
315     */
316    void printFlags(std::ostream &outs, const std::string &separator) const;
317
318    /// Return name of machine instruction
319    std::string getName() { return mnemonic; }
320};
321
322#endif // __CPU_STATIC_INST_HH__
323