static_inst.hh revision 2336 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_STATIC_INST_HH__
30#define __CPU_STATIC_INST_HH__
31
32#include <bitset>
33#include <string>
34
35#include "base/hashmap.hh"
36#include "base/refcnt.hh"
37#include "encumbered/cpu/full/op_class.hh"
38#include "sim/host.hh"
39#include "arch/isa_traits.hh"
40
41// forward declarations
42struct AlphaSimpleImpl;
43struct OzoneImpl;
44struct SimpleImpl;
45class ExecContext;
46class DynInst;
47
48template <class Impl>
49class AlphaDynInst;
50
51template <class Impl>
52class OzoneDynInst;
53
54class CheckerCPU;
55class FastCPU;
56class SimpleCPU;
57class InorderCPU;
58class SymbolTable;
59
60namespace Trace {
61    class InstRecord;
62}
63
64/**
65 * Base, ISA-independent static instruction class.
66 *
67 * The main component of this class is the vector of flags and the
68 * associated methods for reading them.  Any object that can rely
69 * solely on these flags can process instructions without being
70 * recompiled for multiple ISAs.
71 */
72class StaticInstBase : public RefCounted
73{
74  protected:
75
76    /// Set of boolean static instruction properties.
77    ///
78    /// Notes:
79    /// - The IsInteger and IsFloating flags are based on the class of
80    /// registers accessed by the instruction.  Although most
81    /// instructions will have exactly one of these two flags set, it
82    /// is possible for an instruction to have neither (e.g., direct
83    /// unconditional branches, memory barriers) or both (e.g., an
84    /// FP/int conversion).
85    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
86    /// will be set.
87    /// - If IsControl is set, then exactly one of IsDirectControl or
88    /// IsIndirect Control will be set, and exactly one of
89    /// IsCondControl or IsUncondControl will be set.
90    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
91    /// implemented as flags since in the current model there's no
92    /// other way for instructions to inject behavior into the
93    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
94    /// model we should be able to get rid of these flags and
95    /// implement this behavior via the execute() methods.
96    ///
97    enum Flags {
98        IsNop,		///< Is a no-op (no effect at all).
99
100        IsInteger,	///< References integer regs.
101        IsFloating,	///< References FP regs.
102
103        IsMemRef,	///< References memory (load, store, or prefetch).
104        IsLoad,		///< Reads from memory (load or prefetch).
105        IsStore,	///< Writes to memory.
106        IsStoreConditional,    ///< Store conditional instruction.
107        IsInstPrefetch,	///< Instruction-cache prefetch.
108        IsDataPrefetch,	///< Data-cache prefetch.
109        IsCopy,         ///< Fast Cache block copy
110
111        IsControl,		///< Control transfer instruction.
112        IsDirectControl,	///< PC relative control transfer.
113        IsIndirectControl,	///< Register indirect control transfer.
114        IsCondControl,		///< Conditional control transfer.
115        IsUncondControl,	///< Unconditional control transfer.
116        IsCall,			///< Subroutine call.
117        IsReturn,		///< Subroutine return.
118
119        IsCondDelaySlot,///< Conditional Delay-Slot Instruction
120
121        IsThreadSync,	///< Thread synchronization operation.
122
123        IsSerializing,	///< Serializes pipeline: won't execute until all
124                        /// older instructions have committed.
125        IsSerializeBefore,
126        IsSerializeAfter,
127        IsMemBarrier,	///< Is a memory barrier
128        IsWriteBarrier,	///< Is a write barrier
129
130        IsNonSpeculative, ///< Should not be executed speculatively
131        IsQuiesce,      ///< Is a quiesce instruction
132
133        IsIprAccess,    ///< Accesses IPRs
134        IsUnverifiable, ///< Can't be verified by a checker
135
136        NumFlags
137    };
138
139    /// Flag values for this instruction.
140    std::bitset<NumFlags> flags;
141
142    /// See opClass().
143    OpClass _opClass;
144
145    /// See numSrcRegs().
146    int8_t _numSrcRegs;
147
148    /// See numDestRegs().
149    int8_t _numDestRegs;
150
151    /// The following are used to track physical register usage
152    /// for machines with separate int & FP reg files.
153    //@{
154    int8_t _numFPDestRegs;
155    int8_t _numIntDestRegs;
156    //@}
157
158    /// Constructor.
159    /// It's important to initialize everything here to a sane
160    /// default, since the decoder generally only overrides
161    /// the fields that are meaningful for the particular
162    /// instruction.
163    StaticInstBase(OpClass __opClass)
164        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
165          _numFPDestRegs(0), _numIntDestRegs(0)
166    {
167    }
168
169  public:
170
171    /// @name Register information.
172    /// The sum of numFPDestRegs() and numIntDestRegs() equals
173    /// numDestRegs().  The former two functions are used to track
174    /// physical register usage for machines with separate int & FP
175    /// reg files.
176    //@{
177    /// Number of source registers.
178    int8_t numSrcRegs()  const { return _numSrcRegs; }
179    /// Number of destination registers.
180    int8_t numDestRegs() const { return _numDestRegs; }
181    /// Number of floating-point destination regs.
182    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
183    /// Number of integer destination regs.
184    int8_t numIntDestRegs() const { return _numIntDestRegs; }
185    //@}
186
187    /// @name Flag accessors.
188    /// These functions are used to access the values of the various
189    /// instruction property flags.  See StaticInstBase::Flags for descriptions
190    /// of the individual flags.
191    //@{
192
193    bool isNop() 	  const { return flags[IsNop]; }
194
195    bool isMemRef()    	  const { return flags[IsMemRef]; }
196    bool isLoad()	  const { return flags[IsLoad]; }
197    bool isStore()	  const { return flags[IsStore]; }
198    bool isStoreConditional()	  const { return flags[IsStoreConditional]; }
199    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
200    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
201    bool isCopy()         const { return flags[IsCopy];}
202
203    bool isInteger()	  const { return flags[IsInteger]; }
204    bool isFloating()	  const { return flags[IsFloating]; }
205
206    bool isControl()	  const { return flags[IsControl]; }
207    bool isCall()	  const { return flags[IsCall]; }
208    bool isReturn()	  const { return flags[IsReturn]; }
209    bool isDirectCtrl()	  const { return flags[IsDirectControl]; }
210    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
211    bool isCondCtrl()	  const { return flags[IsCondControl]; }
212    bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
213
214    bool isThreadSync()   const { return flags[IsThreadSync]; }
215    bool isSerializing()  const { return flags[IsSerializing] ||
216                                      flags[IsSerializeBefore] ||
217                                      flags[IsSerializeAfter]; }
218    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
219    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
220    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
221    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
222    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
223    bool isQuiesce() const { return flags[IsQuiesce]; }
224    bool isIprAccess() const { return flags[IsIprAccess]; }
225    bool isUnverifiable() const { return flags[IsUnverifiable]; }
226    //@}
227
228    /// Operation class.  Used to select appropriate function unit in issue.
229    OpClass opClass()     const { return _opClass; }
230};
231
232
233// forward declaration
234class StaticInstPtr;
235
236/**
237 * Generic yet ISA-dependent static instruction class.
238 *
239 * This class builds on StaticInstBase, defining fields and interfaces
240 * that are generic across all ISAs but that differ in details
241 * according to the specific ISA being used.
242 */
243class StaticInst : public StaticInstBase
244{
245  public:
246
247    /// Binary machine instruction type.
248    typedef TheISA::MachInst MachInst;
249    /// Binary extended machine instruction type.
250    typedef TheISA::ExtMachInst ExtMachInst;
251    /// Logical register index type.
252    typedef TheISA::RegIndex RegIndex;
253
254    enum {
255        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
256        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
257    };
258
259
260    /// Return logical index (architectural reg num) of i'th destination reg.
261    /// Only the entries from 0 through numDestRegs()-1 are valid.
262    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
263
264    /// Return logical index (architectural reg num) of i'th source reg.
265    /// Only the entries from 0 through numSrcRegs()-1 are valid.
266    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
267
268    /// Pointer to a statically allocated "null" instruction object.
269    /// Used to give eaCompInst() and memAccInst() something to return
270    /// when called on non-memory instructions.
271    static StaticInstPtr nullStaticInstPtr;
272
273    /**
274     * Memory references only: returns "fake" instruction representing
275     * the effective address part of the memory operation.  Used to
276     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
277     * just the EA computation.
278     */
279    virtual const
280    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
281
282    /**
283     * Memory references only: returns "fake" instruction representing
284     * the memory access part of the memory operation.  Used to
285     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
286     * just the memory access (not the EA computation).
287     */
288    virtual const
289    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
290
291    /// The binary machine instruction.
292    const ExtMachInst machInst;
293
294  protected:
295
296    /// See destRegIdx().
297    RegIndex _destRegIdx[MaxInstDestRegs];
298    /// See srcRegIdx().
299    RegIndex _srcRegIdx[MaxInstSrcRegs];
300
301    /**
302     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
303     * methods.  Also useful to readily identify instructions from
304     * within the debugger when #cachedDisassembly has not been
305     * initialized.
306     */
307    const char *mnemonic;
308
309    /**
310     * String representation of disassembly (lazily evaluated via
311     * disassemble()).
312     */
313    mutable std::string *cachedDisassembly;
314
315    /**
316     * Internal function to generate disassembly string.
317     */
318    virtual std::string
319    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
320
321    /// Constructor.
322    StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
323        : StaticInstBase(__opClass),
324          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
325    {
326    }
327
328  public:
329
330    virtual ~StaticInst()
331    {
332        if (cachedDisassembly)
333            delete cachedDisassembly;
334    }
335
336/**
337 * The execute() signatures are auto-generated by scons based on the
338 * set of CPU models we are compiling in today.
339 */
340#include "cpu/static_inst_exec_sigs.hh"
341
342    /**
343     * Return the target address for a PC-relative branch.
344     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
345     * should be true).
346     */
347    virtual Addr branchTarget(Addr branchPC) const
348    {
349        panic("StaticInst::branchTarget() called on instruction "
350              "that is not a PC-relative branch.");
351    }
352
353    /**
354     * Return the target address for an indirect branch (jump).  The
355     * register value is read from the supplied execution context, so
356     * the result is valid only if the execution context is about to
357     * execute the branch in question.  Invalid if not an indirect
358     * branch (i.e. isIndirectCtrl() should be true).
359     */
360    virtual Addr branchTarget(ExecContext *xc) const
361    {
362        panic("StaticInst::branchTarget() called on instruction "
363              "that is not an indirect branch.");
364    }
365
366    /**
367     * Return true if the instruction is a control transfer, and if so,
368     * return the target address as well.
369     */
370    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
371
372    /**
373     * Return string representation of disassembled instruction.
374     * The default version of this function will call the internal
375     * virtual generateDisassembly() function to get the string,
376     * then cache it in #cachedDisassembly.  If the disassembly
377     * should not be cached, this function should be overridden directly.
378     */
379    virtual const std::string &disassemble(Addr pc,
380                                           const SymbolTable *symtab = 0) const
381    {
382        if (!cachedDisassembly)
383            cachedDisassembly =
384                new std::string(generateDisassembly(pc, symtab));
385
386        return *cachedDisassembly;
387    }
388
389    /// Decoded instruction cache type.
390    /// For now we're using a generic hash_map; this seems to work
391    /// pretty well.
392    typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache;
393
394    /// A cache of decoded instruction objects.
395    static DecodeCache decodeCache;
396
397    /**
398     * Dump some basic stats on the decode cache hash map.
399     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
400     */
401    static void dumpDecodeCacheStats();
402
403    /// Decode a machine instruction.
404    /// @param mach_inst The binary instruction to decode.
405    /// @retval A pointer to the corresponding StaticInst object.
406    //This is defined as inline below.
407    static StaticInstPtr decode(ExtMachInst mach_inst);
408};
409
410typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
411
412/// Reference-counted pointer to a StaticInst object.
413/// This type should be used instead of "StaticInst *" so that
414/// StaticInst objects can be properly reference-counted.
415class StaticInstPtr : public RefCountingPtr<StaticInst>
416{
417  public:
418    /// Constructor.
419    StaticInstPtr()
420        : RefCountingPtr<StaticInst>()
421    {
422    }
423
424    /// Conversion from "StaticInst *".
425    StaticInstPtr(StaticInst *p)
426        : RefCountingPtr<StaticInst>(p)
427    {
428    }
429
430    /// Copy constructor.
431    StaticInstPtr(const StaticInstPtr &r)
432        : RefCountingPtr<StaticInst>(r)
433    {
434    }
435
436    /// Construct directly from machine instruction.
437    /// Calls StaticInst::decode().
438    StaticInstPtr(TheISA::ExtMachInst mach_inst)
439        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
440    {
441    }
442
443    /// Convert to pointer to StaticInstBase class.
444    operator const StaticInstBasePtr()
445    {
446        return this->get();
447    }
448};
449
450inline StaticInstPtr
451StaticInst::decode(StaticInst::ExtMachInst mach_inst)
452{
453#ifdef DECODE_CACHE_HASH_STATS
454    // Simple stats on decode hash_map.  Turns out the default
455    // hash function is as good as anything I could come up with.
456    const int dump_every_n = 10000000;
457    static int decodes_til_dump = dump_every_n;
458
459    if (--decodes_til_dump == 0) {
460        dumpDecodeCacheStats();
461        decodes_til_dump = dump_every_n;
462    }
463#endif
464
465    DecodeCache::iterator iter = decodeCache.find(mach_inst);
466    if (iter != decodeCache.end()) {
467        return iter->second;
468    }
469
470    StaticInstPtr si = TheISA::decodeInst(mach_inst);
471    decodeCache[mach_inst] = si;
472    return si;
473}
474
475#endif // __CPU_STATIC_INST_HH__
476