static_inst.hh revision 2103
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_STATIC_INST_HH__ 30#define __CPU_STATIC_INST_HH__ 31 32#include <bitset> 33#include <string> 34 35#include "base/hashmap.hh" 36#include "base/refcnt.hh" 37#include "encumbered/cpu/full/op_class.hh" 38#include "sim/host.hh" 39#include "targetarch/isa_traits.hh" 40 41// forward declarations 42struct AlphaSimpleImpl; 43class ExecContext; 44class DynInst; 45 46template <class Impl> 47class AlphaDynInst; 48 49class FastCPU; 50class SimpleCPU; 51class InorderCPU; 52class SymbolTable; 53 54namespace Trace { 55 class InstRecord; 56} 57 58/** 59 * Base, ISA-independent static instruction class. 60 * 61 * The main component of this class is the vector of flags and the 62 * associated methods for reading them. Any object that can rely 63 * solely on these flags can process instructions without being 64 * recompiled for multiple ISAs. 65 */ 66class StaticInstBase : public RefCounted 67{ 68 protected: 69 70 /// Set of boolean static instruction properties. 71 /// 72 /// Notes: 73 /// - The IsInteger and IsFloating flags are based on the class of 74 /// registers accessed by the instruction. Although most 75 /// instructions will have exactly one of these two flags set, it 76 /// is possible for an instruction to have neither (e.g., direct 77 /// unconditional branches, memory barriers) or both (e.g., an 78 /// FP/int conversion). 79 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 80 /// will be set. 81 /// - If IsControl is set, then exactly one of IsDirectControl or 82 /// IsIndirect Control will be set, and exactly one of 83 /// IsCondControl or IsUncondControl will be set. 84 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 85 /// implemented as flags since in the current model there's no 86 /// other way for instructions to inject behavior into the 87 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 88 /// model we should be able to get rid of these flags and 89 /// implement this behavior via the execute() methods. 90 /// 91 enum Flags { 92 IsNop, ///< Is a no-op (no effect at all). 93 94 IsInteger, ///< References integer regs. 95 IsFloating, ///< References FP regs. 96 97 IsMemRef, ///< References memory (load, store, or prefetch). 98 IsLoad, ///< Reads from memory (load or prefetch). 99 IsStore, ///< Writes to memory. 100 IsInstPrefetch, ///< Instruction-cache prefetch. 101 IsDataPrefetch, ///< Data-cache prefetch. 102 IsCopy, ///< Fast Cache block copy 103 104 IsControl, ///< Control transfer instruction. 105 IsDirectControl, ///< PC relative control transfer. 106 IsIndirectControl, ///< Register indirect control transfer. 107 IsCondControl, ///< Conditional control transfer. 108 IsUncondControl, ///< Unconditional control transfer. 109 IsCall, ///< Subroutine call. 110 IsReturn, ///< Subroutine return. 111 112 IsThreadSync, ///< Thread synchronization operation. 113 114 IsSerializing, ///< Serializes pipeline: won't execute until all 115 /// older instructions have committed. 116 IsSerializeBefore, 117 IsSerializeAfter, 118 IsMemBarrier, ///< Is a memory barrier 119 IsWriteBarrier, ///< Is a write barrier 120 121 IsNonSpeculative, ///< Should not be executed speculatively 122 123 NumFlags 124 }; 125 126 /// Flag values for this instruction. 127 std::bitset<NumFlags> flags; 128 129 /// See opClass(). 130 OpClass _opClass; 131 132 /// See numSrcRegs(). 133 int8_t _numSrcRegs; 134 135 /// See numDestRegs(). 136 int8_t _numDestRegs; 137 138 /// The following are used to track physical register usage 139 /// for machines with separate int & FP reg files. 140 //@{ 141 int8_t _numFPDestRegs; 142 int8_t _numIntDestRegs; 143 //@} 144 145 /// Constructor. 146 /// It's important to initialize everything here to a sane 147 /// default, since the decoder generally only overrides 148 /// the fields that are meaningful for the particular 149 /// instruction. 150 StaticInstBase(OpClass __opClass) 151 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 152 _numFPDestRegs(0), _numIntDestRegs(0) 153 { 154 } 155 156 public: 157 158 /// @name Register information. 159 /// The sum of numFPDestRegs() and numIntDestRegs() equals 160 /// numDestRegs(). The former two functions are used to track 161 /// physical register usage for machines with separate int & FP 162 /// reg files. 163 //@{ 164 /// Number of source registers. 165 int8_t numSrcRegs() const { return _numSrcRegs; } 166 /// Number of destination registers. 167 int8_t numDestRegs() const { return _numDestRegs; } 168 /// Number of floating-point destination regs. 169 int8_t numFPDestRegs() const { return _numFPDestRegs; } 170 /// Number of integer destination regs. 171 int8_t numIntDestRegs() const { return _numIntDestRegs; } 172 //@} 173 174 /// @name Flag accessors. 175 /// These functions are used to access the values of the various 176 /// instruction property flags. See StaticInstBase::Flags for descriptions 177 /// of the individual flags. 178 //@{ 179 180 bool isNop() const { return flags[IsNop]; } 181 182 bool isMemRef() const { return flags[IsMemRef]; } 183 bool isLoad() const { return flags[IsLoad]; } 184 bool isStore() const { return flags[IsStore]; } 185 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 186 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 187 bool isCopy() const { return flags[IsCopy];} 188 189 bool isInteger() const { return flags[IsInteger]; } 190 bool isFloating() const { return flags[IsFloating]; } 191 192 bool isControl() const { return flags[IsControl]; } 193 bool isCall() const { return flags[IsCall]; } 194 bool isReturn() const { return flags[IsReturn]; } 195 bool isDirectCtrl() const { return flags[IsDirectControl]; } 196 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 197 bool isCondCtrl() const { return flags[IsCondControl]; } 198 bool isUncondCtrl() const { return flags[IsUncondControl]; } 199 200 bool isThreadSync() const { return flags[IsThreadSync]; } 201 bool isSerializing() const { return flags[IsSerializing] || 202 flags[IsSerializeBefore] || 203 flags[IsSerializeAfter]; } 204 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 205 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 206 bool isMemBarrier() const { return flags[IsMemBarrier]; } 207 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 208 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 209 //@} 210 211 /// Operation class. Used to select appropriate function unit in issue. 212 OpClass opClass() const { return _opClass; } 213}; 214 215 216// forward declaration 217template <class ISA> 218class StaticInstPtr; 219 220/** 221 * Generic yet ISA-dependent static instruction class. 222 * 223 * This class builds on StaticInstBase, defining fields and interfaces 224 * that are generic across all ISAs but that differ in details 225 * according to the specific ISA being used. 226 */ 227template <class ISA> 228class StaticInst : public StaticInstBase 229{ 230 public: 231 232 /// Binary machine instruction type. 233 typedef typename ISA::MachInst MachInst; 234 /// Memory address type. 235 typedef typename ISA::Addr Addr; 236 /// Logical register index type. 237 typedef typename ISA::RegIndex RegIndex; 238 239 enum { 240 MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs 241 MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs 242 }; 243 244 245 /// Return logical index (architectural reg num) of i'th destination reg. 246 /// Only the entries from 0 through numDestRegs()-1 are valid. 247 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 248 249 /// Return logical index (architectural reg num) of i'th source reg. 250 /// Only the entries from 0 through numSrcRegs()-1 are valid. 251 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 252 253 /// Pointer to a statically allocated "null" instruction object. 254 /// Used to give eaCompInst() and memAccInst() something to return 255 /// when called on non-memory instructions. 256 static StaticInstPtr<ISA> nullStaticInstPtr; 257 258 /** 259 * Memory references only: returns "fake" instruction representing 260 * the effective address part of the memory operation. Used to 261 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 262 * just the EA computation. 263 */ 264 virtual const 265 StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; } 266 267 /** 268 * Memory references only: returns "fake" instruction representing 269 * the memory access part of the memory operation. Used to 270 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 271 * just the memory access (not the EA computation). 272 */ 273 virtual const 274 StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; } 275 276 /// The binary machine instruction. 277 const MachInst machInst; 278 279 protected: 280 281 /// See destRegIdx(). 282 RegIndex _destRegIdx[MaxInstDestRegs]; 283 /// See srcRegIdx(). 284 RegIndex _srcRegIdx[MaxInstSrcRegs]; 285 286 /** 287 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 288 * methods. Also useful to readily identify instructions from 289 * within the debugger when #cachedDisassembly has not been 290 * initialized. 291 */ 292 const char *mnemonic; 293 294 /** 295 * String representation of disassembly (lazily evaluated via 296 * disassemble()). 297 */ 298 mutable std::string *cachedDisassembly; 299 300 /** 301 * Internal function to generate disassembly string. 302 */ 303 virtual std::string 304 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 305 306 /// Constructor. 307 StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass) 308 : StaticInstBase(__opClass), 309 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 310 { 311 } 312 313 public: 314 315 virtual ~StaticInst() 316 { 317 if (cachedDisassembly) 318 delete cachedDisassembly; 319 } 320 321#include "static_inst_impl.hh" 322 323 /** 324 * Return the target address for a PC-relative branch. 325 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 326 * should be true). 327 */ 328 virtual Addr branchTarget(Addr branchPC) const 329 { 330 panic("StaticInst::branchTarget() called on instruction " 331 "that is not a PC-relative branch."); 332 } 333 334 /** 335 * Return the target address for an indirect branch (jump). The 336 * register value is read from the supplied execution context, so 337 * the result is valid only if the execution context is about to 338 * execute the branch in question. Invalid if not an indirect 339 * branch (i.e. isIndirectCtrl() should be true). 340 */ 341 virtual Addr branchTarget(ExecContext *xc) const 342 { 343 panic("StaticInst::branchTarget() called on instruction " 344 "that is not an indirect branch."); 345 } 346 347 /** 348 * Return true if the instruction is a control transfer, and if so, 349 * return the target address as well. 350 */ 351 bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const; 352 353 /** 354 * Return string representation of disassembled instruction. 355 * The default version of this function will call the internal 356 * virtual generateDisassembly() function to get the string, 357 * then cache it in #cachedDisassembly. If the disassembly 358 * should not be cached, this function should be overridden directly. 359 */ 360 virtual const std::string &disassemble(Addr pc, 361 const SymbolTable *symtab = 0) const 362 { 363 if (!cachedDisassembly) 364 cachedDisassembly = 365 new std::string(generateDisassembly(pc, symtab)); 366 367 return *cachedDisassembly; 368 } 369 370 /// Decoded instruction cache type. 371 /// For now we're using a generic hash_map; this seems to work 372 /// pretty well. 373 typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache; 374 375 /// A cache of decoded instruction objects. 376 static DecodeCache decodeCache; 377 378 /** 379 * Dump some basic stats on the decode cache hash map. 380 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 381 */ 382 static void dumpDecodeCacheStats(); 383 384 /// Decode a machine instruction. 385 /// @param mach_inst The binary instruction to decode. 386 /// @retval A pointer to the corresponding StaticInst object. 387 static 388 StaticInstPtr<ISA> decode(MachInst mach_inst) 389 { 390#ifdef DECODE_CACHE_HASH_STATS 391 // Simple stats on decode hash_map. Turns out the default 392 // hash function is as good as anything I could come up with. 393 const int dump_every_n = 10000000; 394 static int decodes_til_dump = dump_every_n; 395 396 if (--decodes_til_dump == 0) { 397 dumpDecodeCacheStats(); 398 decodes_til_dump = dump_every_n; 399 } 400#endif 401 402 typename DecodeCache::iterator iter = decodeCache.find(mach_inst); 403 if (iter != decodeCache.end()) { 404 return iter->second; 405 } 406 407 StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst); 408 decodeCache[mach_inst] = si; 409 return si; 410 } 411}; 412 413typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 414 415/// Reference-counted pointer to a StaticInst object. 416/// This type should be used instead of "StaticInst<ISA> *" so that 417/// StaticInst objects can be properly reference-counted. 418template <class ISA> 419class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> > 420{ 421 public: 422 /// Constructor. 423 StaticInstPtr() 424 : RefCountingPtr<StaticInst<ISA> >() 425 { 426 } 427 428 /// Conversion from "StaticInst<ISA> *". 429 StaticInstPtr(StaticInst<ISA> *p) 430 : RefCountingPtr<StaticInst<ISA> >(p) 431 { 432 } 433 434 /// Copy constructor. 435 StaticInstPtr(const StaticInstPtr &r) 436 : RefCountingPtr<StaticInst<ISA> >(r) 437 { 438 } 439 440 /// Construct directly from machine instruction. 441 /// Calls StaticInst<ISA>::decode(). 442 StaticInstPtr(typename ISA::MachInst mach_inst) 443 : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst)) 444 { 445 } 446 447 /// Convert to pointer to StaticInstBase class. 448 operator const StaticInstBasePtr() 449 { 450 return this->get(); 451 } 452}; 453 454#endif // __CPU_STATIC_INST_HH__ 455