static_inst.cc revision 4539
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 322SN/A#include <iostream> 3356SN/A#include "cpu/static_inst.hh" 344167Sbinkertn@umich.edu#include "sim/core.hh" 352SN/A 362107SN/AStaticInstPtr StaticInst::nullStaticInstPtr; 372SN/A 382SN/A// Define the decode cache hash map. 392107SN/AStaticInst::DecodeCache StaticInst::decodeCache; 402SN/A 412SN/Avoid 422107SN/AStaticInst::dumpDecodeCacheStats() 432SN/A{ 442SN/A using namespace std; 452SN/A 462SN/A cerr << "Decode hash table stats @ " << curTick << ":" << endl; 472SN/A cerr << "\tnum entries = " << decodeCache.size() << endl; 482SN/A cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl; 492SN/A vector<int> hist(100, 0); 502SN/A int max_hist = 0; 512SN/A for (int i = 0; i < decodeCache.bucket_count(); ++i) { 522SN/A int count = decodeCache.elems_in_bucket(i); 532SN/A if (count > max_hist) 542SN/A max_hist = count; 552SN/A hist[count]++; 562SN/A } 572SN/A for (int i = 0; i <= max_hist; ++i) { 582SN/A cerr << "\tbuckets of size " << i << " = " << hist[i] << endl; 592SN/A } 602SN/A} 612SN/A 622SN/Abool 632680Sktlim@umich.eduStaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const 642SN/A{ 652SN/A if (isDirectCtrl()) { 662SN/A tgt = branchTarget(pc); 672SN/A return true; 682SN/A } 692SN/A 702SN/A if (isIndirectCtrl()) { 712680Sktlim@umich.edu tgt = branchTarget(tc); 722SN/A return true; 732SN/A } 742SN/A 752SN/A return false; 762SN/A} 772SN/A 783271Sgblack@eecs.umich.eduStaticInstPtr 794539Sgblack@eecs.umich.eduStaticInst::fetchMicroop(MicroPC micropc) 803271Sgblack@eecs.umich.edu{ 814539Sgblack@eecs.umich.edu panic("StaticInst::fetchMicroop() called on instruction " 823271Sgblack@eecs.umich.edu "that is not microcoded."); 833271Sgblack@eecs.umich.edu} 843271Sgblack@eecs.umich.edu 85