static_inst.cc revision 11793
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 292665Ssaidi@eecs.umich.edu * Nathan Binkert 302SN/A */ 312SN/A 3211793Sbrandon.potter@amd.com#include "cpu/static_inst.hh" 3311793Sbrandon.potter@amd.com 342SN/A#include <iostream> 358229Snate@binkert.org 364167Sbinkertn@umich.edu#include "sim/core.hh" 372SN/A 382107SN/AStaticInstPtr StaticInst::nullStaticInstPtr; 392SN/A 405870Snate@binkert.orgusing namespace std; 415870Snate@binkert.org 425870Snate@binkert.orgStaticInst::~StaticInst() 435870Snate@binkert.org{ 445870Snate@binkert.org if (cachedDisassembly) 455870Snate@binkert.org delete cachedDisassembly; 465870Snate@binkert.org} 475870Snate@binkert.org 482SN/Abool 497720Sgblack@eecs.umich.eduStaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 507720Sgblack@eecs.umich.edu TheISA::PCState &tgt) const 512SN/A{ 522SN/A if (isDirectCtrl()) { 532SN/A tgt = branchTarget(pc); 542SN/A return true; 552SN/A } 562SN/A 572SN/A if (isIndirectCtrl()) { 582680Sktlim@umich.edu tgt = branchTarget(tc); 592SN/A return true; 602SN/A } 612SN/A 622SN/A return false; 632SN/A} 642SN/A 653271Sgblack@eecs.umich.eduStaticInstPtr 667720Sgblack@eecs.umich.eduStaticInst::fetchMicroop(MicroPC upc) const 673271Sgblack@eecs.umich.edu{ 684539Sgblack@eecs.umich.edu panic("StaticInst::fetchMicroop() called on instruction " 695870Snate@binkert.org "that is not microcoded."); 703271Sgblack@eecs.umich.edu} 713271Sgblack@eecs.umich.edu 727720Sgblack@eecs.umich.eduTheISA::PCState 737720Sgblack@eecs.umich.eduStaticInst::branchTarget(const TheISA::PCState &pc) const 745870Snate@binkert.org{ 755870Snate@binkert.org panic("StaticInst::branchTarget() called on instruction " 765870Snate@binkert.org "that is not a PC-relative branch."); 775870Snate@binkert.org M5_DUMMY_RETURN; 785870Snate@binkert.org} 795870Snate@binkert.org 807720Sgblack@eecs.umich.eduTheISA::PCState 815870Snate@binkert.orgStaticInst::branchTarget(ThreadContext *tc) const 825870Snate@binkert.org{ 835870Snate@binkert.org panic("StaticInst::branchTarget() called on instruction " 845870Snate@binkert.org "that is not an indirect branch."); 855870Snate@binkert.org M5_DUMMY_RETURN; 865870Snate@binkert.org} 875870Snate@binkert.org 885870Snate@binkert.orgconst string & 895870Snate@binkert.orgStaticInst::disassemble(Addr pc, const SymbolTable *symtab) const 905870Snate@binkert.org{ 915870Snate@binkert.org if (!cachedDisassembly) 925870Snate@binkert.org cachedDisassembly = new string(generateDisassembly(pc, symtab)); 935870Snate@binkert.org 945870Snate@binkert.org return *cachedDisassembly; 955870Snate@binkert.org} 9610201SAndrew.Bardsley@arm.com 9710201SAndrew.Bardsley@arm.comvoid 9810201SAndrew.Bardsley@arm.comStaticInst::printFlags(std::ostream &outs, 9910201SAndrew.Bardsley@arm.com const std::string &separator) const 10010201SAndrew.Bardsley@arm.com{ 10110201SAndrew.Bardsley@arm.com bool printed_a_flag = false; 10210201SAndrew.Bardsley@arm.com 10310201SAndrew.Bardsley@arm.com for (unsigned int flag = IsNop; flag < Num_Flags; flag++) { 10410201SAndrew.Bardsley@arm.com if (flags[flag]) { 10510201SAndrew.Bardsley@arm.com if (printed_a_flag) 10610201SAndrew.Bardsley@arm.com outs << separator; 10710201SAndrew.Bardsley@arm.com 10810201SAndrew.Bardsley@arm.com outs << FlagsStrings[flag]; 10910201SAndrew.Bardsley@arm.com printed_a_flag = true; 11010201SAndrew.Bardsley@arm.com } 11110201SAndrew.Bardsley@arm.com } 11210201SAndrew.Bardsley@arm.com} 113