12SN/A/*
21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert
292SN/A */
302SN/A
312SN/A/**
322SN/A * @file
33381SN/A * Defines SMT_MAX_THREADS.
342SN/A */
352SN/A
362SN/A#ifndef __SMT_HH__
372SN/A#define __SMT_HH__
382SN/A
398230Snate@binkert.org#include "base/types.hh"
408230Snate@binkert.org
412SN/A#ifndef SMT_MAX_THREADS
422SN/A/** The number of TPUs in any processor. */
432SN/A#define SMT_MAX_THREADS 4
442SN/A#endif
452SN/A
462SN/A/**
472SN/A * The maximum number of active threads across all cpus. Used to
482SN/A * initialize per-thread statistics in the cache.
492SN/A *
502SN/A * NB: Be careful to only use it once all the CPUs that you care about
512SN/A *     have been initialized
522SN/A */
532SN/Aextern int maxThreadsPerCPU;
542SN/A
552SN/A/**
562SN/A * Changes the status and priority of the thread with the given number.
576221Snate@binkert.org * @param tid The thread to change.
582SN/A * @param activate The new active status.
592SN/A * @param priority The new priority.
602SN/A */
616221Snate@binkert.orgvoid change_thread_state(ThreadID tid, int activate, int priority);
622SN/A
632SN/A#endif // __SMT_HH__
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