simple_thread.hh revision 8794:e2ac2b7164dd
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa.hh" 36#include "arch/isa_traits.hh" 37#include "arch/registers.hh" 38#include "arch/tlb.hh" 39#include "arch/types.hh" 40#include "base/types.hh" 41#include "config/the_isa.hh" 42#include "cpu/decode.hh" 43#include "cpu/thread_context.hh" 44#include "cpu/thread_state.hh" 45#include "debug/FloatRegs.hh" 46#include "debug/IntRegs.hh" 47#include "mem/page_table.hh" 48#include "mem/request.hh" 49#include "sim/byteswap.hh" 50#include "sim/eventq.hh" 51#include "sim/process.hh" 52#include "sim/serialize.hh" 53#include "sim/system.hh" 54 55class BaseCPU; 56 57 58class FunctionProfile; 59class ProfileNode; 60class FunctionalPort; 61class PhysicalPort; 62class TranslatingPort; 63 64namespace TheISA { 65 namespace Kernel { 66 class Statistics; 67 }; 68}; 69 70/** 71 * The SimpleThread object provides a combination of the ThreadState 72 * object and the ThreadContext interface. It implements the 73 * ThreadContext interface so that a ProxyThreadContext class can be 74 * made using SimpleThread as the template parameter (see 75 * thread_context.hh). It adds to the ThreadState object by adding all 76 * the objects needed for simple functional execution, including a 77 * simple architectural register file, and pointers to the ITB and DTB 78 * in full system mode. For CPU models that do not need more advanced 79 * ways to hold state (i.e. a separate physical register file, or 80 * separate fetch and commit PC's), this SimpleThread class provides 81 * all the necessary state for full architecture-level functional 82 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 83 * examples. 84 */ 85 86class SimpleThread : public ThreadState 87{ 88 protected: 89 typedef TheISA::MachInst MachInst; 90 typedef TheISA::MiscReg MiscReg; 91 typedef TheISA::FloatReg FloatReg; 92 typedef TheISA::FloatRegBits FloatRegBits; 93 public: 94 typedef ThreadContext::Status Status; 95 96 protected: 97 union { 98 FloatReg f[TheISA::NumFloatRegs]; 99 FloatRegBits i[TheISA::NumFloatRegs]; 100 } floatRegs; 101 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 102 TheISA::ISA isa; // one "instance" of the current ISA. 103 104 TheISA::PCState _pcState; 105 106 /** Did this instruction execute or is it predicated false */ 107 bool predicate; 108 109 public: 110 std::string name() const 111 { 112 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 113 } 114 115 // pointer to CPU associated with this SimpleThread 116 BaseCPU *cpu; 117 118 ProxyThreadContext<SimpleThread> *tc; 119 120 System *system; 121 122 TheISA::TLB *itb; 123 TheISA::TLB *dtb; 124 125 Decoder decoder; 126 127 // constructor: initialize SimpleThread from given process structure 128 // FS 129 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 130 TheISA::TLB *_itb, TheISA::TLB *_dtb, 131 bool use_kernel_stats = true); 132 // SE 133 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 134 TheISA::TLB *_itb, TheISA::TLB *_dtb); 135 136 SimpleThread(); 137 138 virtual ~SimpleThread(); 139 140 virtual void takeOverFrom(ThreadContext *oldContext); 141 142 void regStats(const std::string &name); 143 144 void copyTC(ThreadContext *context); 145 146 void copyState(ThreadContext *oldContext); 147 148 void serialize(std::ostream &os); 149 void unserialize(Checkpoint *cp, const std::string §ion); 150 151 /*************************************************************** 152 * SimpleThread functions to provide CPU with access to various 153 * state. 154 **************************************************************/ 155 156 /** Returns the pointer to this SimpleThread's ThreadContext. Used 157 * when a ThreadContext must be passed to objects outside of the 158 * CPU. 159 */ 160 ThreadContext *getTC() { return tc; } 161 162 void demapPage(Addr vaddr, uint64_t asn) 163 { 164 itb->demapPage(vaddr, asn); 165 dtb->demapPage(vaddr, asn); 166 } 167 168 void demapInstPage(Addr vaddr, uint64_t asn) 169 { 170 itb->demapPage(vaddr, asn); 171 } 172 173 void demapDataPage(Addr vaddr, uint64_t asn) 174 { 175 dtb->demapPage(vaddr, asn); 176 } 177 178 void dumpFuncProfile(); 179 180 Fault hwrei(); 181 182 bool simPalCheck(int palFunc); 183 184 /******************************************* 185 * ThreadContext interface functions. 186 ******************************************/ 187 188 BaseCPU *getCpuPtr() { return cpu; } 189 190 TheISA::TLB *getITBPtr() { return itb; } 191 192 TheISA::TLB *getDTBPtr() { return dtb; } 193 194 Decoder *getDecoderPtr() { return &decoder; } 195 196 System *getSystemPtr() { return system; } 197 198 FunctionalPort *getPhysPort() { return physPort; } 199 200 /** Return a virtual port. This port cannot be cached locally in an object. 201 * After a CPU switch it may point to the wrong memory object which could 202 * mean stale data. 203 */ 204 VirtualPort *getVirtPort() { return virtPort; } 205 206 Status status() const { return _status; } 207 208 void setStatus(Status newStatus) { _status = newStatus; } 209 210 /// Set the status to Active. Optional delay indicates number of 211 /// cycles to wait before beginning execution. 212 void activate(int delay = 1); 213 214 /// Set the status to Suspended. 215 void suspend(); 216 217 /// Set the status to Halted. 218 void halt(); 219 220 virtual bool misspeculating(); 221 222 void copyArchRegs(ThreadContext *tc); 223 224 void clearArchRegs() 225 { 226 _pcState = 0; 227 memset(intRegs, 0, sizeof(intRegs)); 228 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 229 isa.clear(); 230 } 231 232 // 233 // New accessors for new decoder. 234 // 235 uint64_t readIntReg(int reg_idx) 236 { 237 int flatIndex = isa.flattenIntIndex(reg_idx); 238 assert(flatIndex < TheISA::NumIntRegs); 239 uint64_t regVal = intRegs[flatIndex]; 240 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 241 reg_idx, flatIndex, regVal); 242 return regVal; 243 } 244 245 FloatReg readFloatReg(int reg_idx) 246 { 247 int flatIndex = isa.flattenFloatIndex(reg_idx); 248 assert(flatIndex < TheISA::NumFloatRegs); 249 FloatReg regVal = floatRegs.f[flatIndex]; 250 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 251 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 252 return regVal; 253 } 254 255 FloatRegBits readFloatRegBits(int reg_idx) 256 { 257 int flatIndex = isa.flattenFloatIndex(reg_idx); 258 assert(flatIndex < TheISA::NumFloatRegs); 259 FloatRegBits regVal = floatRegs.i[flatIndex]; 260 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 261 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 262 return regVal; 263 } 264 265 void setIntReg(int reg_idx, uint64_t val) 266 { 267 int flatIndex = isa.flattenIntIndex(reg_idx); 268 assert(flatIndex < TheISA::NumIntRegs); 269 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 270 reg_idx, flatIndex, val); 271 intRegs[flatIndex] = val; 272 } 273 274 void setFloatReg(int reg_idx, FloatReg val) 275 { 276 int flatIndex = isa.flattenFloatIndex(reg_idx); 277 assert(flatIndex < TheISA::NumFloatRegs); 278 floatRegs.f[flatIndex] = val; 279 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 280 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 281 } 282 283 void setFloatRegBits(int reg_idx, FloatRegBits val) 284 { 285 int flatIndex = isa.flattenFloatIndex(reg_idx); 286 assert(flatIndex < TheISA::NumFloatRegs); 287 floatRegs.i[flatIndex] = val; 288 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 289 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 290 } 291 292 TheISA::PCState 293 pcState() 294 { 295 return _pcState; 296 } 297 298 void 299 pcState(const TheISA::PCState &val) 300 { 301 _pcState = val; 302 } 303 304 Addr 305 instAddr() 306 { 307 return _pcState.instAddr(); 308 } 309 310 Addr 311 nextInstAddr() 312 { 313 return _pcState.nextInstAddr(); 314 } 315 316 MicroPC 317 microPC() 318 { 319 return _pcState.microPC(); 320 } 321 322 bool readPredicate() 323 { 324 return predicate; 325 } 326 327 void setPredicate(bool val) 328 { 329 predicate = val; 330 } 331 332 MiscReg 333 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 334 { 335 return isa.readMiscRegNoEffect(misc_reg); 336 } 337 338 MiscReg 339 readMiscReg(int misc_reg, ThreadID tid = 0) 340 { 341 return isa.readMiscReg(misc_reg, tc); 342 } 343 344 void 345 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 346 { 347 return isa.setMiscRegNoEffect(misc_reg, val); 348 } 349 350 void 351 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 352 { 353 return isa.setMiscReg(misc_reg, val, tc); 354 } 355 356 int 357 flattenIntIndex(int reg) 358 { 359 return isa.flattenIntIndex(reg); 360 } 361 362 int 363 flattenFloatIndex(int reg) 364 { 365 return isa.flattenFloatIndex(reg); 366 } 367 368 unsigned readStCondFailures() { return storeCondFailures; } 369 370 void setStCondFailures(unsigned sc_failures) 371 { storeCondFailures = sc_failures; } 372 373 void syscall(int64_t callnum) 374 { 375 process->syscall(callnum, tc); 376 } 377}; 378 379 380// for non-speculative execution context, spec_mode is always false 381inline bool 382SimpleThread::misspeculating() 383{ 384 return false; 385} 386 387#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 388