simple_thread.hh revision 8735:dd20a8139788
1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __CPU_SIMPLE_THREAD_HH__ 45#define __CPU_SIMPLE_THREAD_HH__ 46 47#include "arch/isa.hh" 48#include "arch/isa_traits.hh" 49#include "arch/registers.hh" 50#include "arch/tlb.hh" 51#include "arch/types.hh" 52#include "base/types.hh" 53#include "config/full_system.hh" 54#include "config/the_isa.hh" 55#include "config/use_checker.hh" 56#include "cpu/decode.hh" 57#include "cpu/thread_context.hh" 58#include "cpu/thread_state.hh" 59#include "debug/FloatRegs.hh" 60#include "debug/IntRegs.hh" 61#include "mem/request.hh" 62#include "sim/byteswap.hh" 63#include "sim/eventq.hh" 64#include "sim/serialize.hh" 65 66class BaseCPU; 67 68#if FULL_SYSTEM 69 70#include "sim/system.hh" 71 72class FunctionProfile; 73class ProfileNode; 74 75namespace TheISA { 76 namespace Kernel { 77 class Statistics; 78 }; 79}; 80 81#else // !FULL_SYSTEM 82 83#include "mem/page_table.hh" 84#include "sim/process.hh" 85 86#endif // FULL_SYSTEM 87 88/** 89 * The SimpleThread object provides a combination of the ThreadState 90 * object and the ThreadContext interface. It implements the 91 * ThreadContext interface so that a ProxyThreadContext class can be 92 * made using SimpleThread as the template parameter (see 93 * thread_context.hh). It adds to the ThreadState object by adding all 94 * the objects needed for simple functional execution, including a 95 * simple architectural register file, and pointers to the ITB and DTB 96 * in full system mode. For CPU models that do not need more advanced 97 * ways to hold state (i.e. a separate physical register file, or 98 * separate fetch and commit PC's), this SimpleThread class provides 99 * all the necessary state for full architecture-level functional 100 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 101 * examples. 102 */ 103 104class SimpleThread : public ThreadState 105{ 106 protected: 107 typedef TheISA::MachInst MachInst; 108 typedef TheISA::MiscReg MiscReg; 109 typedef TheISA::FloatReg FloatReg; 110 typedef TheISA::FloatRegBits FloatRegBits; 111 public: 112 typedef ThreadContext::Status Status; 113 114 protected: 115 union { 116 FloatReg f[TheISA::NumFloatRegs]; 117 FloatRegBits i[TheISA::NumFloatRegs]; 118 } floatRegs; 119 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 120 TheISA::ISA isa; // one "instance" of the current ISA. 121 122 TheISA::PCState _pcState; 123 124 /** Did this instruction execute or is it predicated false */ 125 bool predicate; 126 127 public: 128 std::string name() const 129 { 130 return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 131 } 132 133 ProxyThreadContext<SimpleThread> *tc; 134 135 System *system; 136 137 TheISA::TLB *itb; 138 TheISA::TLB *dtb; 139 140 Decoder decoder; 141 142 // constructor: initialize SimpleThread from given process structure 143#if FULL_SYSTEM 144 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 145 TheISA::TLB *_itb, TheISA::TLB *_dtb, 146 bool use_kernel_stats = true); 147#else 148 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 149 TheISA::TLB *_itb, TheISA::TLB *_dtb); 150#endif 151 152 SimpleThread(); 153 154 virtual ~SimpleThread(); 155 156 virtual void takeOverFrom(ThreadContext *oldContext); 157 158 void regStats(const std::string &name); 159 160 void copyTC(ThreadContext *context); 161 162 void copyState(ThreadContext *oldContext); 163 164 void serialize(std::ostream &os); 165 void unserialize(Checkpoint *cp, const std::string §ion); 166 167 /*************************************************************** 168 * SimpleThread functions to provide CPU with access to various 169 * state. 170 **************************************************************/ 171 172 /** Returns the pointer to this SimpleThread's ThreadContext. Used 173 * when a ThreadContext must be passed to objects outside of the 174 * CPU. 175 */ 176 ThreadContext *getTC() { return tc; } 177 178 void demapPage(Addr vaddr, uint64_t asn) 179 { 180 itb->demapPage(vaddr, asn); 181 dtb->demapPage(vaddr, asn); 182 } 183 184 void demapInstPage(Addr vaddr, uint64_t asn) 185 { 186 itb->demapPage(vaddr, asn); 187 } 188 189 void demapDataPage(Addr vaddr, uint64_t asn) 190 { 191 dtb->demapPage(vaddr, asn); 192 } 193 194#if FULL_SYSTEM 195 void dumpFuncProfile(); 196 197 Fault hwrei(); 198 199 bool simPalCheck(int palFunc); 200 201#endif 202 203 /******************************************* 204 * ThreadContext interface functions. 205 ******************************************/ 206 207 BaseCPU *getCpuPtr() { return baseCpu; } 208 209 TheISA::TLB *getITBPtr() { return itb; } 210 211 TheISA::TLB *getDTBPtr() { return dtb; } 212 213#if USE_CHECKER 214 BaseCPU *getCheckerCpuPtr() { return NULL; } 215#endif 216 217 Decoder *getDecoderPtr() { return &decoder; } 218 219 System *getSystemPtr() { return system; } 220 221#if FULL_SYSTEM 222 PortProxy* getPhysProxy() { return physProxy; } 223 224 /** Return a virtual port. This port cannot be cached locally in an object. 225 * After a CPU switch it may point to the wrong memory object which could 226 * mean stale data. 227 */ 228 FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 229#endif 230 231 Status status() const { return _status; } 232 233 void setStatus(Status newStatus) { _status = newStatus; } 234 235 /// Set the status to Active. Optional delay indicates number of 236 /// cycles to wait before beginning execution. 237 void activate(int delay = 1); 238 239 /// Set the status to Suspended. 240 void suspend(); 241 242 /// Set the status to Halted. 243 void halt(); 244 245 virtual bool misspeculating(); 246 247 void copyArchRegs(ThreadContext *tc); 248 249 void clearArchRegs() 250 { 251 _pcState = 0; 252 memset(intRegs, 0, sizeof(intRegs)); 253 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 254 isa.clear(); 255 } 256 257 // 258 // New accessors for new decoder. 259 // 260 uint64_t readIntReg(int reg_idx) 261 { 262 int flatIndex = isa.flattenIntIndex(reg_idx); 263 assert(flatIndex < TheISA::NumIntRegs); 264 uint64_t regVal = intRegs[flatIndex]; 265 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 266 reg_idx, flatIndex, regVal); 267 return regVal; 268 } 269 270 FloatReg readFloatReg(int reg_idx) 271 { 272 int flatIndex = isa.flattenFloatIndex(reg_idx); 273 assert(flatIndex < TheISA::NumFloatRegs); 274 FloatReg regVal = floatRegs.f[flatIndex]; 275 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 276 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 277 return regVal; 278 } 279 280 FloatRegBits readFloatRegBits(int reg_idx) 281 { 282 int flatIndex = isa.flattenFloatIndex(reg_idx); 283 assert(flatIndex < TheISA::NumFloatRegs); 284 FloatRegBits regVal = floatRegs.i[flatIndex]; 285 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 286 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 287 return regVal; 288 } 289 290 void setIntReg(int reg_idx, uint64_t val) 291 { 292 int flatIndex = isa.flattenIntIndex(reg_idx); 293 assert(flatIndex < TheISA::NumIntRegs); 294 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 295 reg_idx, flatIndex, val); 296 intRegs[flatIndex] = val; 297 } 298 299 void setFloatReg(int reg_idx, FloatReg val) 300 { 301 int flatIndex = isa.flattenFloatIndex(reg_idx); 302 assert(flatIndex < TheISA::NumFloatRegs); 303 floatRegs.f[flatIndex] = val; 304 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 305 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 306 } 307 308 void setFloatRegBits(int reg_idx, FloatRegBits val) 309 { 310 int flatIndex = isa.flattenFloatIndex(reg_idx); 311 assert(flatIndex < TheISA::NumFloatRegs); 312 // XXX: Fix array out of bounds compiler error for gem5.fast 313 // when checkercpu enabled 314 if (flatIndex < TheISA::NumFloatRegs) 315 floatRegs.i[flatIndex] = val; 316 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 317 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 318 } 319 320 TheISA::PCState 321 pcState() 322 { 323 return _pcState; 324 } 325 326 void 327 pcState(const TheISA::PCState &val) 328 { 329 _pcState = val; 330 } 331 332#if USE_CHECKER 333 void 334 pcStateNoRecord(const TheISA::PCState &val) 335 { 336 _pcState = val; 337 } 338#endif 339 340 Addr 341 instAddr() 342 { 343 return _pcState.instAddr(); 344 } 345 346 Addr 347 nextInstAddr() 348 { 349 return _pcState.nextInstAddr(); 350 } 351 352 MicroPC 353 microPC() 354 { 355 return _pcState.microPC(); 356 } 357 358 bool readPredicate() 359 { 360 return predicate; 361 } 362 363 void setPredicate(bool val) 364 { 365 predicate = val; 366 } 367 368 MiscReg 369 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 370 { 371 return isa.readMiscRegNoEffect(misc_reg); 372 } 373 374 MiscReg 375 readMiscReg(int misc_reg, ThreadID tid = 0) 376 { 377 return isa.readMiscReg(misc_reg, tc); 378 } 379 380 void 381 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 382 { 383 return isa.setMiscRegNoEffect(misc_reg, val); 384 } 385 386 void 387 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 388 { 389 return isa.setMiscReg(misc_reg, val, tc); 390 } 391 392 int 393 flattenIntIndex(int reg) 394 { 395 return isa.flattenIntIndex(reg); 396 } 397 398 int 399 flattenFloatIndex(int reg) 400 { 401 return isa.flattenFloatIndex(reg); 402 } 403 404 unsigned readStCondFailures() { return storeCondFailures; } 405 406 void setStCondFailures(unsigned sc_failures) 407 { storeCondFailures = sc_failures; } 408 409#if !FULL_SYSTEM 410 void syscall(int64_t callnum) 411 { 412 process->syscall(callnum, tc); 413 } 414#endif 415}; 416 417 418// for non-speculative execution context, spec_mode is always false 419inline bool 420SimpleThread::misspeculating() 421{ 422 return false; 423} 424 425#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 426