simple_thread.hh revision 8730:0a742249f76b
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa.hh" 36#include "arch/isa_traits.hh" 37#include "arch/registers.hh" 38#include "arch/tlb.hh" 39#include "arch/types.hh" 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "config/the_isa.hh" 43#include "cpu/decode.hh" 44#include "cpu/thread_context.hh" 45#include "cpu/thread_state.hh" 46#include "debug/FloatRegs.hh" 47#include "debug/IntRegs.hh" 48#include "mem/request.hh" 49#include "sim/byteswap.hh" 50#include "sim/eventq.hh" 51#include "sim/serialize.hh" 52 53class BaseCPU; 54 55#if FULL_SYSTEM 56 57#include "sim/system.hh" 58 59class FunctionProfile; 60class ProfileNode; 61 62namespace TheISA { 63 namespace Kernel { 64 class Statistics; 65 }; 66}; 67 68#else // !FULL_SYSTEM 69 70#include "mem/page_table.hh" 71#include "sim/process.hh" 72 73#endif // FULL_SYSTEM 74 75/** 76 * The SimpleThread object provides a combination of the ThreadState 77 * object and the ThreadContext interface. It implements the 78 * ThreadContext interface so that a ProxyThreadContext class can be 79 * made using SimpleThread as the template parameter (see 80 * thread_context.hh). It adds to the ThreadState object by adding all 81 * the objects needed for simple functional execution, including a 82 * simple architectural register file, and pointers to the ITB and DTB 83 * in full system mode. For CPU models that do not need more advanced 84 * ways to hold state (i.e. a separate physical register file, or 85 * separate fetch and commit PC's), this SimpleThread class provides 86 * all the necessary state for full architecture-level functional 87 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 88 * examples. 89 */ 90 91class SimpleThread : public ThreadState 92{ 93 protected: 94 typedef TheISA::MachInst MachInst; 95 typedef TheISA::MiscReg MiscReg; 96 typedef TheISA::FloatReg FloatReg; 97 typedef TheISA::FloatRegBits FloatRegBits; 98 public: 99 typedef ThreadContext::Status Status; 100 101 protected: 102 union { 103 FloatReg f[TheISA::NumFloatRegs]; 104 FloatRegBits i[TheISA::NumFloatRegs]; 105 } floatRegs; 106 TheISA::IntReg intRegs[TheISA::NumIntRegs]; 107 TheISA::ISA isa; // one "instance" of the current ISA. 108 109 TheISA::PCState _pcState; 110 111 /** Did this instruction execute or is it predicated false */ 112 bool predicate; 113 114 public: 115 std::string name() const 116 { 117 return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 118 } 119 120 // pointer to CPU associated with this SimpleThread 121 BaseCPU *cpu; 122 123 ProxyThreadContext<SimpleThread> *tc; 124 125 System *system; 126 127 TheISA::TLB *itb; 128 TheISA::TLB *dtb; 129 130 Decoder decoder; 131 132 // constructor: initialize SimpleThread from given process structure 133#if FULL_SYSTEM 134 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 135 TheISA::TLB *_itb, TheISA::TLB *_dtb, 136 bool use_kernel_stats = true); 137#else 138 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 139 TheISA::TLB *_itb, TheISA::TLB *_dtb); 140#endif 141 142 SimpleThread(); 143 144 virtual ~SimpleThread(); 145 146 virtual void takeOverFrom(ThreadContext *oldContext); 147 148 void regStats(const std::string &name); 149 150 void copyTC(ThreadContext *context); 151 152 void copyState(ThreadContext *oldContext); 153 154 void serialize(std::ostream &os); 155 void unserialize(Checkpoint *cp, const std::string §ion); 156 157 /*************************************************************** 158 * SimpleThread functions to provide CPU with access to various 159 * state. 160 **************************************************************/ 161 162 /** Returns the pointer to this SimpleThread's ThreadContext. Used 163 * when a ThreadContext must be passed to objects outside of the 164 * CPU. 165 */ 166 ThreadContext *getTC() { return tc; } 167 168 void demapPage(Addr vaddr, uint64_t asn) 169 { 170 itb->demapPage(vaddr, asn); 171 dtb->demapPage(vaddr, asn); 172 } 173 174 void demapInstPage(Addr vaddr, uint64_t asn) 175 { 176 itb->demapPage(vaddr, asn); 177 } 178 179 void demapDataPage(Addr vaddr, uint64_t asn) 180 { 181 dtb->demapPage(vaddr, asn); 182 } 183 184#if FULL_SYSTEM 185 void dumpFuncProfile(); 186 187 Fault hwrei(); 188 189 bool simPalCheck(int palFunc); 190 191#endif 192 193 /******************************************* 194 * ThreadContext interface functions. 195 ******************************************/ 196 197 BaseCPU *getCpuPtr() { return cpu; } 198 199 TheISA::TLB *getITBPtr() { return itb; } 200 201 TheISA::TLB *getDTBPtr() { return dtb; } 202 203 Decoder *getDecoderPtr() { return &decoder; } 204 205 System *getSystemPtr() { return system; } 206 207#if FULL_SYSTEM 208 PortProxy* getPhysProxy() { return physProxy; } 209 210 /** Return a virtual port. This port cannot be cached locally in an object. 211 * After a CPU switch it may point to the wrong memory object which could 212 * mean stale data. 213 */ 214 FSTranslatingPortProxy* getVirtProxy() { return virtProxy; } 215#endif 216 217 Status status() const { return _status; } 218 219 void setStatus(Status newStatus) { _status = newStatus; } 220 221 /// Set the status to Active. Optional delay indicates number of 222 /// cycles to wait before beginning execution. 223 void activate(int delay = 1); 224 225 /// Set the status to Suspended. 226 void suspend(); 227 228 /// Set the status to Halted. 229 void halt(); 230 231 virtual bool misspeculating(); 232 233 void copyArchRegs(ThreadContext *tc); 234 235 void clearArchRegs() 236 { 237 _pcState = 0; 238 memset(intRegs, 0, sizeof(intRegs)); 239 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 240 isa.clear(); 241 } 242 243 // 244 // New accessors for new decoder. 245 // 246 uint64_t readIntReg(int reg_idx) 247 { 248 int flatIndex = isa.flattenIntIndex(reg_idx); 249 assert(flatIndex < TheISA::NumIntRegs); 250 uint64_t regVal = intRegs[flatIndex]; 251 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 252 reg_idx, flatIndex, regVal); 253 return regVal; 254 } 255 256 FloatReg readFloatReg(int reg_idx) 257 { 258 int flatIndex = isa.flattenFloatIndex(reg_idx); 259 assert(flatIndex < TheISA::NumFloatRegs); 260 FloatReg regVal = floatRegs.f[flatIndex]; 261 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 262 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 263 return regVal; 264 } 265 266 FloatRegBits readFloatRegBits(int reg_idx) 267 { 268 int flatIndex = isa.flattenFloatIndex(reg_idx); 269 assert(flatIndex < TheISA::NumFloatRegs); 270 FloatRegBits regVal = floatRegs.i[flatIndex]; 271 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 272 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 273 return regVal; 274 } 275 276 void setIntReg(int reg_idx, uint64_t val) 277 { 278 int flatIndex = isa.flattenIntIndex(reg_idx); 279 assert(flatIndex < TheISA::NumIntRegs); 280 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 281 reg_idx, flatIndex, val); 282 intRegs[flatIndex] = val; 283 } 284 285 void setFloatReg(int reg_idx, FloatReg val) 286 { 287 int flatIndex = isa.flattenFloatIndex(reg_idx); 288 assert(flatIndex < TheISA::NumFloatRegs); 289 floatRegs.f[flatIndex] = val; 290 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 291 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 292 } 293 294 void setFloatRegBits(int reg_idx, FloatRegBits val) 295 { 296 int flatIndex = isa.flattenFloatIndex(reg_idx); 297 assert(flatIndex < TheISA::NumFloatRegs); 298 floatRegs.i[flatIndex] = val; 299 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 300 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 301 } 302 303 TheISA::PCState 304 pcState() 305 { 306 return _pcState; 307 } 308 309 void 310 pcState(const TheISA::PCState &val) 311 { 312 _pcState = val; 313 } 314 315 Addr 316 instAddr() 317 { 318 return _pcState.instAddr(); 319 } 320 321 Addr 322 nextInstAddr() 323 { 324 return _pcState.nextInstAddr(); 325 } 326 327 MicroPC 328 microPC() 329 { 330 return _pcState.microPC(); 331 } 332 333 bool readPredicate() 334 { 335 return predicate; 336 } 337 338 void setPredicate(bool val) 339 { 340 predicate = val; 341 } 342 343 MiscReg 344 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 345 { 346 return isa.readMiscRegNoEffect(misc_reg); 347 } 348 349 MiscReg 350 readMiscReg(int misc_reg, ThreadID tid = 0) 351 { 352 return isa.readMiscReg(misc_reg, tc); 353 } 354 355 void 356 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 357 { 358 return isa.setMiscRegNoEffect(misc_reg, val); 359 } 360 361 void 362 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 363 { 364 return isa.setMiscReg(misc_reg, val, tc); 365 } 366 367 int 368 flattenIntIndex(int reg) 369 { 370 return isa.flattenIntIndex(reg); 371 } 372 373 int 374 flattenFloatIndex(int reg) 375 { 376 return isa.flattenFloatIndex(reg); 377 } 378 379 unsigned readStCondFailures() { return storeCondFailures; } 380 381 void setStCondFailures(unsigned sc_failures) 382 { storeCondFailures = sc_failures; } 383 384#if !FULL_SYSTEM 385 void syscall(int64_t callnum) 386 { 387 process->syscall(callnum, tc); 388 } 389#endif 390}; 391 392 393// for non-speculative execution context, spec_mode is always false 394inline bool 395SimpleThread::misspeculating() 396{ 397 return false; 398} 399 400#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 401