simple_thread.hh revision 5222:bb733a878f85
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/regfile.hh"
37#include "arch/syscallreturn.hh"
38#include "arch/tlb.hh"
39#include "config/full_system.hh"
40#include "cpu/thread_context.hh"
41#include "cpu/thread_state.hh"
42#include "mem/request.hh"
43#include "sim/byteswap.hh"
44#include "sim/eventq.hh"
45#include "sim/host.hh"
46#include "sim/serialize.hh"
47
48class BaseCPU;
49
50#if FULL_SYSTEM
51
52#include "sim/system.hh"
53
54class FunctionProfile;
55class ProfileNode;
56class FunctionalPort;
57class PhysicalPort;
58
59namespace TheISA {
60    namespace Kernel {
61        class Statistics;
62    };
63};
64
65#else // !FULL_SYSTEM
66
67#include "sim/process.hh"
68#include "mem/page_table.hh"
69class TranslatingPort;
70
71#endif // FULL_SYSTEM
72
73/**
74 * The SimpleThread object provides a combination of the ThreadState
75 * object and the ThreadContext interface. It implements the
76 * ThreadContext interface so that a ProxyThreadContext class can be
77 * made using SimpleThread as the template parameter (see
78 * thread_context.hh). It adds to the ThreadState object by adding all
79 * the objects needed for simple functional execution, including a
80 * simple architectural register file, and pointers to the ITB and DTB
81 * in full system mode. For CPU models that do not need more advanced
82 * ways to hold state (i.e. a separate physical register file, or
83 * separate fetch and commit PC's), this SimpleThread class provides
84 * all the necessary state for full architecture-level functional
85 * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
86 * examples.
87 */
88
89class SimpleThread : public ThreadState
90{
91  protected:
92    typedef TheISA::RegFile RegFile;
93    typedef TheISA::MachInst MachInst;
94    typedef TheISA::MiscRegFile MiscRegFile;
95    typedef TheISA::MiscReg MiscReg;
96    typedef TheISA::FloatReg FloatReg;
97    typedef TheISA::FloatRegBits FloatRegBits;
98  public:
99    typedef ThreadContext::Status Status;
100
101  protected:
102    RegFile regs;	// correct-path register context
103
104  public:
105    // pointer to CPU associated with this SimpleThread
106    BaseCPU *cpu;
107
108    ProxyThreadContext<SimpleThread> *tc;
109
110    System *system;
111
112    TheISA::ITB *itb;
113    TheISA::DTB *dtb;
114
115    // constructor: initialize SimpleThread from given process structure
116#if FULL_SYSTEM
117    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
118                 TheISA::ITB *_itb, TheISA::DTB *_dtb,
119                 bool use_kernel_stats = true);
120#else
121    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
122                 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
123#endif
124
125    SimpleThread();
126
127    virtual ~SimpleThread();
128
129    virtual void takeOverFrom(ThreadContext *oldContext);
130
131    void regStats(const std::string &name);
132
133    void copyTC(ThreadContext *context);
134
135    void copyState(ThreadContext *oldContext);
136
137    void serialize(std::ostream &os);
138    void unserialize(Checkpoint *cp, const std::string &section);
139
140    /***************************************************************
141     *  SimpleThread functions to provide CPU with access to various
142     *  state, and to provide address translation methods.
143     **************************************************************/
144
145    /** Returns the pointer to this SimpleThread's ThreadContext. Used
146     *  when a ThreadContext must be passed to objects outside of the
147     *  CPU.
148     */
149    ThreadContext *getTC() { return tc; }
150
151    Fault translateInstReq(RequestPtr &req)
152    {
153        return itb->translate(req, tc);
154    }
155
156    Fault translateDataReadReq(RequestPtr &req)
157    {
158        return dtb->translate(req, tc, false);
159    }
160
161    Fault translateDataWriteReq(RequestPtr &req)
162    {
163        return dtb->translate(req, tc, true);
164    }
165
166#if FULL_SYSTEM
167    int getInstAsid() { return regs.instAsid(); }
168    int getDataAsid() { return regs.dataAsid(); }
169
170    void dumpFuncProfile();
171
172    Fault hwrei();
173
174    bool simPalCheck(int palFunc);
175
176#endif
177
178    /*******************************************
179     * ThreadContext interface functions.
180     ******************************************/
181
182    BaseCPU *getCpuPtr() { return cpu; }
183
184    int getThreadNum() { return tid; }
185
186    TheISA::ITB *getITBPtr() { return itb; }
187
188    TheISA::DTB *getDTBPtr() { return dtb; }
189
190#if FULL_SYSTEM
191    System *getSystemPtr() { return system; }
192
193    FunctionalPort *getPhysPort() { return physPort; }
194
195    /** Return a virtual port. If no thread context is specified then a static
196     * port is returned. Otherwise a port is created and returned. It must be
197     * deleted by deleteVirtPort(). */
198    VirtualPort *getVirtPort(ThreadContext *tc);
199
200    void delVirtPort(VirtualPort *vp);
201#endif
202
203    Status status() const { return _status; }
204
205    void setStatus(Status newStatus) { _status = newStatus; }
206
207    /// Set the status to Active.  Optional delay indicates number of
208    /// cycles to wait before beginning execution.
209    void activate(int delay = 1);
210
211    /// Set the status to Suspended.
212    void suspend();
213
214    /// Set the status to Unallocated.
215    void deallocate();
216
217    /// Set the status to Halted.
218    void halt();
219
220    virtual bool misspeculating();
221
222    Fault instRead(RequestPtr &req)
223    {
224        panic("instRead not implemented");
225        // return funcPhysMem->read(req, inst);
226        return NoFault;
227    }
228
229    void copyArchRegs(ThreadContext *tc);
230
231    void clearArchRegs() { regs.clear(); }
232
233    //
234    // New accessors for new decoder.
235    //
236    uint64_t readIntReg(int reg_idx)
237    {
238        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
239        return regs.readIntReg(flatIndex);
240    }
241
242    FloatReg readFloatReg(int reg_idx, int width)
243    {
244        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
245        return regs.readFloatReg(flatIndex, width);
246    }
247
248    FloatReg readFloatReg(int reg_idx)
249    {
250        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
251        return regs.readFloatReg(flatIndex);
252    }
253
254    FloatRegBits readFloatRegBits(int reg_idx, int width)
255    {
256        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
257        return regs.readFloatRegBits(flatIndex, width);
258    }
259
260    FloatRegBits readFloatRegBits(int reg_idx)
261    {
262        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
263        return regs.readFloatRegBits(flatIndex);
264    }
265
266    void setIntReg(int reg_idx, uint64_t val)
267    {
268        int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
269        regs.setIntReg(flatIndex, val);
270    }
271
272    void setFloatReg(int reg_idx, FloatReg val, int width)
273    {
274        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
275        regs.setFloatReg(flatIndex, val, width);
276    }
277
278    void setFloatReg(int reg_idx, FloatReg val)
279    {
280        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
281        regs.setFloatReg(flatIndex, val);
282    }
283
284    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
285    {
286        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
287        regs.setFloatRegBits(flatIndex, val, width);
288    }
289
290    void setFloatRegBits(int reg_idx, FloatRegBits val)
291    {
292        int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
293        regs.setFloatRegBits(flatIndex, val);
294    }
295
296    uint64_t readPC()
297    {
298        return regs.readPC();
299    }
300
301    void setPC(uint64_t val)
302    {
303        regs.setPC(val);
304    }
305
306    uint64_t readMicroPC()
307    {
308        return microPC;
309    }
310
311    void setMicroPC(uint64_t val)
312    {
313        microPC = val;
314    }
315
316    uint64_t readNextPC()
317    {
318        return regs.readNextPC();
319    }
320
321    void setNextPC(uint64_t val)
322    {
323        regs.setNextPC(val);
324    }
325
326    uint64_t readNextMicroPC()
327    {
328        return nextMicroPC;
329    }
330
331    void setNextMicroPC(uint64_t val)
332    {
333        nextMicroPC = val;
334    }
335
336    uint64_t readNextNPC()
337    {
338        return regs.readNextNPC();
339    }
340
341    void setNextNPC(uint64_t val)
342    {
343        regs.setNextNPC(val);
344    }
345
346    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
347    {
348        return regs.readMiscRegNoEffect(misc_reg);
349    }
350
351    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
352    {
353        return regs.readMiscReg(misc_reg, tc);
354    }
355
356    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
357    {
358        return regs.setMiscRegNoEffect(misc_reg, val);
359    }
360
361    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
362    {
363        return regs.setMiscReg(misc_reg, val, tc);
364    }
365
366    unsigned readStCondFailures() { return storeCondFailures; }
367
368    void setStCondFailures(unsigned sc_failures)
369    { storeCondFailures = sc_failures; }
370
371    void setShadowSet(int css, int tid=0) {
372      regs.setShadowSet(css);
373    }
374
375#if !FULL_SYSTEM
376    TheISA::IntReg getSyscallArg(int i)
377    {
378        assert(i < TheISA::NumArgumentRegs);
379        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
380                    TheISA::ArgumentReg[i]));
381    }
382
383    // used to shift args for indirect syscall
384    void setSyscallArg(int i, TheISA::IntReg val)
385    {
386        assert(i < TheISA::NumArgumentRegs);
387        regs.setIntReg(TheISA::flattenIntIndex(getTC(),
388                    TheISA::ArgumentReg[i]), val);
389    }
390
391    void setSyscallReturn(SyscallReturn return_value)
392    {
393        TheISA::setSyscallReturn(return_value, getTC());
394    }
395
396    void syscall(int64_t callnum)
397    {
398        process->syscall(callnum, tc);
399    }
400#endif
401
402    void changeRegFileContext(TheISA::RegContextParam param,
403            TheISA::RegContextVal val)
404    {
405        regs.changeContext(param, val);
406    }
407};
408
409
410// for non-speculative execution context, spec_mode is always false
411inline bool
412SimpleThread::misspeculating()
413{
414    return false;
415}
416
417#endif // __CPU_CPU_EXEC_CONTEXT_HH__
418