simple_thread.hh revision 4997:e7380529bd2d
11689SN/A/*
22326SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt
291689SN/A *          Nathan Binkert
301689SN/A */
311060SN/A
321060SN/A#ifndef __CPU_SIMPLE_THREAD_HH__
331689SN/A#define __CPU_SIMPLE_THREAD_HH__
341060SN/A
351060SN/A#include "arch/isa_traits.hh"
361060SN/A#include "arch/regfile.hh"
371060SN/A#include "arch/syscallreturn.hh"
382292SN/A#include "arch/tlb.hh"
391717SN/A#include "config/full_system.hh"
401060SN/A#include "cpu/thread_context.hh"
411681SN/A#include "cpu/thread_state.hh"
422292SN/A#include "mem/request.hh"
432873Sktlim@umich.edu#include "sim/byteswap.hh"
441060SN/A#include "sim/eventq.hh"
451061SN/A#include "sim/host.hh"
462292SN/A#include "sim/serialize.hh"
472292SN/A
482292SN/Aclass BaseCPU;
492292SN/A
502820Sktlim@umich.edu#if FULL_SYSTEM
512292SN/A
522820Sktlim@umich.edu#include "sim/system.hh"
532820Sktlim@umich.edu
542307SN/Aclass FunctionProfile;
552307SN/Aclass ProfileNode;
561060SN/Aclass FunctionalPort;
572292SN/Aclass PhysicalPort;
582292SN/A
592292SN/Anamespace TheISA {
601060SN/A    namespace Kernel {
611060SN/A        class Statistics;
621060SN/A    };
631060SN/A};
641060SN/A
651060SN/A#else // !FULL_SYSTEM
661681SN/A
672292SN/A#include "sim/process.hh"
681681SN/A#include "mem/page_table.hh"
692292SN/Aclass TranslatingPort;
702292SN/A
712292SN/A#endif // FULL_SYSTEM
722292SN/A
732292SN/A/**
742935Sksewell@umich.edu * The SimpleThread object provides a combination of the ThreadState
752292SN/A * object and the ThreadContext interface. It implements the
762292SN/A * ThreadContext interface so that a ProxyThreadContext class can be
772820Sktlim@umich.edu * made using SimpleThread as the template parameter (see
782820Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all
792292SN/A * the objects needed for simple functional execution, including a
802292SN/A * simple architectural register file, and pointers to the ITB and DTB
812820Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced
822820Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or
832292SN/A * separate fetch and commit PC's), this SimpleThread class provides
842292SN/A * all the necessary state for full architecture-level functional
852292SN/A * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
862292SN/A * examples.
872292SN/A */
882292SN/A
892292SN/Aclass SimpleThread : public ThreadState
902292SN/A{
911060SN/A  protected:
921060SN/A    typedef TheISA::RegFile RegFile;
931681SN/A    typedef TheISA::MachInst MachInst;
941062SN/A    typedef TheISA::MiscRegFile MiscRegFile;
952292SN/A    typedef TheISA::MiscReg MiscReg;
961062SN/A    typedef TheISA::FloatReg FloatReg;
972301SN/A    typedef TheISA::FloatRegBits FloatRegBits;
982301SN/A  public:
991062SN/A    typedef ThreadContext::Status Status;
1002727Sktlim@umich.edu
1011062SN/A  protected:
1021062SN/A    RegFile regs;	// correct-path register context
1031062SN/A
1041062SN/A  public:
1051062SN/A    // pointer to CPU associated with this SimpleThread
1061062SN/A    BaseCPU *cpu;
1071062SN/A
1081062SN/A    ProxyThreadContext<SimpleThread> *tc;
1091062SN/A
1101062SN/A    System *system;
1111062SN/A
1121062SN/A    TheISA::ITB *itb;
1131062SN/A    TheISA::DTB *dtb;
1141062SN/A
1151062SN/A    // constructor: initialize SimpleThread from given process structure
1161062SN/A#if FULL_SYSTEM
1171062SN/A    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
1181062SN/A                 TheISA::ITB *_itb, TheISA::DTB *_dtb,
1191062SN/A                 bool use_kernel_stats = true);
1201062SN/A#else
1211062SN/A    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
1221062SN/A                 TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
1231062SN/A#endif
1241062SN/A
1251062SN/A    SimpleThread();
1261062SN/A
1271062SN/A    virtual ~SimpleThread();
1281062SN/A
1291062SN/A    virtual void takeOverFrom(ThreadContext *oldContext);
1301062SN/A
1311062SN/A    void regStats(const std::string &name);
1321062SN/A
1331062SN/A    void copyTC(ThreadContext *context);
1341062SN/A
1351062SN/A    void copyState(ThreadContext *oldContext);
1361062SN/A
1371062SN/A    void serialize(std::ostream &os);
1381062SN/A    void unserialize(Checkpoint *cp, const std::string &section);
1391062SN/A
1401062SN/A    /***************************************************************
1411062SN/A     *  SimpleThread functions to provide CPU with access to various
1422292SN/A     *  state, and to provide address translation methods.
1432292SN/A     **************************************************************/
1442292SN/A
1452292SN/A    /** Returns the pointer to this SimpleThread's ThreadContext. Used
1461062SN/A     *  when a ThreadContext must be passed to objects outside of the
1471062SN/A     *  CPU.
1481062SN/A     */
1491062SN/A    ThreadContext *getTC() { return tc; }
1501062SN/A
1511062SN/A    Fault translateInstReq(RequestPtr &req)
1521062SN/A    {
1532292SN/A        return itb->translate(req, tc);
1542292SN/A    }
1552292SN/A
1562292SN/A    Fault translateDataReadReq(RequestPtr &req)
1572292SN/A    {
1582292SN/A        return dtb->translate(req, tc, false);
1592292SN/A    }
1602292SN/A
1612292SN/A    Fault translateDataWriteReq(RequestPtr &req)
1622292SN/A    {
1632301SN/A        return dtb->translate(req, tc, true);
1642727Sktlim@umich.edu    }
1652353SN/A
1662727Sktlim@umich.edu#if FULL_SYSTEM
1672727Sktlim@umich.edu    int getInstAsid() { return regs.instAsid(); }
1682727Sktlim@umich.edu    int getDataAsid() { return regs.dataAsid(); }
1692727Sktlim@umich.edu
1702353SN/A    void dumpFuncProfile();
1712727Sktlim@umich.edu
1722727Sktlim@umich.edu    Fault hwrei();
1732727Sktlim@umich.edu
1742727Sktlim@umich.edu    bool simPalCheck(int palFunc);
1752353SN/A
1762727Sktlim@umich.edu#endif
1772727Sktlim@umich.edu
1782727Sktlim@umich.edu    /*******************************************
1792301SN/A     * ThreadContext interface functions.
1802301SN/A     ******************************************/
1812301SN/A
1822727Sktlim@umich.edu    BaseCPU *getCpuPtr() { return cpu; }
1832301SN/A
1842727Sktlim@umich.edu    int getThreadNum() { return tid; }
1852301SN/A
1862301SN/A    TheISA::ITB *getITBPtr() { return itb; }
1872301SN/A
1882727Sktlim@umich.edu    TheISA::DTB *getDTBPtr() { return dtb; }
1892301SN/A
1902727Sktlim@umich.edu#if FULL_SYSTEM
1912301SN/A    System *getSystemPtr() { return system; }
1922301SN/A
1932301SN/A    FunctionalPort *getPhysPort() { return physPort; }
1942727Sktlim@umich.edu
1952301SN/A    /** Return a virtual port. If no thread context is specified then a static
1962727Sktlim@umich.edu     * port is returned. Otherwise a port is created and returned. It must be
1972301SN/A     * deleted by deleteVirtPort(). */
1982301SN/A    VirtualPort *getVirtPort(ThreadContext *tc);
1992301SN/A
2002727Sktlim@umich.edu    void delVirtPort(VirtualPort *vp);
2012301SN/A#endif
2022301SN/A
2032301SN/A    Status status() const { return _status; }
2042301SN/A
2052727Sktlim@umich.edu    void setStatus(Status newStatus) { _status = newStatus; }
2062727Sktlim@umich.edu
2072727Sktlim@umich.edu    /// Set the status to Active.  Optional delay indicates number of
2082727Sktlim@umich.edu    /// cycles to wait before beginning execution.
2092727Sktlim@umich.edu    void activate(int delay = 1);
2102727Sktlim@umich.edu
2112727Sktlim@umich.edu    /// Set the status to Suspended.
2122727Sktlim@umich.edu    void suspend();
2132727Sktlim@umich.edu
2142301SN/A    /// Set the status to Unallocated.
2152301SN/A    void deallocate();
2162301SN/A
2172301SN/A    /// Set the status to Halted.
2182301SN/A    void halt();
2192727Sktlim@umich.edu
2202301SN/A    virtual bool misspeculating();
2212326SN/A
2222301SN/A    Fault instRead(RequestPtr &req)
2232301SN/A    {
2242301SN/A        panic("instRead not implemented");
2252727Sktlim@umich.edu        // return funcPhysMem->read(req, inst);
2262301SN/A        return NoFault;
2272326SN/A    }
2282301SN/A
2292301SN/A    void copyArchRegs(ThreadContext *tc);
2302301SN/A
2312727Sktlim@umich.edu    void clearArchRegs() { regs.clear(); }
2322301SN/A
2332326SN/A    //
2342301SN/A    // New accessors for new decoder.
2352301SN/A    //
2362301SN/A    uint64_t readIntReg(int reg_idx)
2372727Sktlim@umich.edu    {
2382301SN/A        return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
2392326SN/A    }
2402301SN/A
2412301SN/A    FloatReg readFloatReg(int reg_idx, int width)
2422301SN/A    {
2432727Sktlim@umich.edu        return regs.readFloatReg(reg_idx, width);
2442301SN/A    }
2452326SN/A
2462301SN/A    FloatReg readFloatReg(int reg_idx)
2472301SN/A    {
2482727Sktlim@umich.edu        return regs.readFloatReg(reg_idx);
2492301SN/A    }
2502326SN/A
2512301SN/A    FloatRegBits readFloatRegBits(int reg_idx, int width)
2522326SN/A    {
2532301SN/A        return regs.readFloatRegBits(reg_idx, width);
2542301SN/A    }
2552727Sktlim@umich.edu
2562301SN/A    FloatRegBits readFloatRegBits(int reg_idx)
2572326SN/A    {
2582301SN/A        return regs.readFloatRegBits(reg_idx);
2592326SN/A    }
2602301SN/A
2612301SN/A    void setIntReg(int reg_idx, uint64_t val)
2622727Sktlim@umich.edu    {
2632326SN/A        regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
2641062SN/A    }
2651062SN/A
2661681SN/A    void setFloatReg(int reg_idx, FloatReg val, int width)
2671060SN/A    {
2682292SN/A        regs.setFloatReg(reg_idx, val, width);
2691060SN/A    }
2702292SN/A
2712292SN/A    void setFloatReg(int reg_idx, FloatReg val)
2722292SN/A    {
2732292SN/A        regs.setFloatReg(reg_idx, val);
2742292SN/A    }
2752292SN/A
2762292SN/A    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
2772292SN/A    {
2782292SN/A        regs.setFloatRegBits(reg_idx, val, width);
2792292SN/A    }
2802292SN/A
2812292SN/A    void setFloatRegBits(int reg_idx, FloatRegBits val)
2822292SN/A    {
2832733Sktlim@umich.edu        regs.setFloatRegBits(reg_idx, val);
2842292SN/A    }
2852292SN/A
2861060SN/A    uint64_t readPC()
2871060SN/A    {
2881060SN/A        return regs.readPC();
2891061SN/A    }
2902292SN/A
2912733Sktlim@umich.edu    void setPC(uint64_t val)
2921060SN/A    {
2931060SN/A        regs.setPC(val);
2941681SN/A    }
2951060SN/A
2962292SN/A    uint64_t readMicroPC()
2971060SN/A    {
2982292SN/A        return microPC;
2991060SN/A    }
3001060SN/A
3011060SN/A    void setMicroPC(uint64_t val)
3021060SN/A    {
3031060SN/A        microPC = val;
3041060SN/A    }
3051060SN/A
3061060SN/A    uint64_t readNextPC()
3072292SN/A    {
3082292SN/A        return regs.readNextPC();
3091060SN/A    }
3101060SN/A
3111060SN/A    void setNextPC(uint64_t val)
3121060SN/A    {
3131681SN/A        regs.setNextPC(val);
3141060SN/A    }
3152292SN/A
3161060SN/A    uint64_t readNextMicroPC()
3172292SN/A    {
3181060SN/A        return nextMicroPC;
3191060SN/A    }
3201060SN/A
3211060SN/A    void setNextMicroPC(uint64_t val)
3221060SN/A    {
3231060SN/A        nextMicroPC = val;
3241681SN/A    }
3251060SN/A
3262292SN/A    uint64_t readNextNPC()
3271060SN/A    {
3282292SN/A        return regs.readNextNPC();
3291060SN/A    }
3301060SN/A
3311060SN/A    void setNextNPC(uint64_t val)
3321060SN/A    {
3331060SN/A        regs.setNextNPC(val);
3341060SN/A    }
3351681SN/A
3361060SN/A    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
3372980Sgblack@eecs.umich.edu    {
3381060SN/A        return regs.readMiscRegNoEffect(misc_reg);
3392292SN/A    }
3402292SN/A
3412292SN/A    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
3422292SN/A    {
3432292SN/A        return regs.readMiscReg(misc_reg, tc);
3441060SN/A    }
3451060SN/A
3461681SN/A    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
3471060SN/A    {
3482292SN/A        return regs.setMiscRegNoEffect(misc_reg, val);
3491060SN/A    }
3502292SN/A
3512292SN/A    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
3521060SN/A    {
3531060SN/A        return regs.setMiscReg(misc_reg, val, tc);
3542307SN/A    }
3552863Sktlim@umich.edu
3562843Sktlim@umich.edu    unsigned readStCondFailures() { return storeCondFailures; }
3572307SN/A
3582843Sktlim@umich.edu    void setStCondFailures(unsigned sc_failures)
3592843Sktlim@umich.edu    { storeCondFailures = sc_failures; }
3602863Sktlim@umich.edu
3611681SN/A#if !FULL_SYSTEM
3621681SN/A    TheISA::IntReg getSyscallArg(int i)
3632316SN/A    {
3641681SN/A        assert(i < TheISA::NumArgumentRegs);
3652843Sktlim@umich.edu        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
3662843Sktlim@umich.edu                    TheISA::ArgumentReg[i]));
3672843Sktlim@umich.edu    }
3682843Sktlim@umich.edu
3692843Sktlim@umich.edu    // used to shift args for indirect syscall
3702843Sktlim@umich.edu    void setSyscallArg(int i, TheISA::IntReg val)
3712843Sktlim@umich.edu    {
3721681SN/A        assert(i < TheISA::NumArgumentRegs);
3732348SN/A        regs.setIntReg(TheISA::flattenIntIndex(getTC(),
3742307SN/A                    TheISA::ArgumentReg[i]), val);
3752367SN/A    }
3762367SN/A
3771681SN/A    void setSyscallReturn(SyscallReturn return_value)
3782307SN/A    {
3792307SN/A        TheISA::setSyscallReturn(return_value, getTC());
3802307SN/A    }
3812307SN/A
3822307SN/A    void syscall(int64_t callnum)
3832307SN/A    {
3842307SN/A        process->syscall(callnum, tc);
3852307SN/A    }
3862307SN/A#endif
3872307SN/A
3881681SN/A    void changeRegFileContext(TheISA::RegContextParam param,
3891681SN/A            TheISA::RegContextVal val)
3902307SN/A    {
3911681SN/A        regs.changeContext(param, val);
3922307SN/A    }
3931060SN/A};
3942348SN/A
3952307SN/A
3962307SN/A// for non-speculative execution context, spec_mode is always false
3972307SN/Ainline bool
3982307SN/ASimpleThread::misspeculating()
3991060SN/A{
4002307SN/A    return false;
4012307SN/A}
4022307SN/A
4031060SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__
4042307SN/A