simple_thread.hh revision 4661:44458219add1
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 */
31
32#ifndef __CPU_SIMPLE_THREAD_HH__
33#define __CPU_SIMPLE_THREAD_HH__
34
35#include "arch/isa_traits.hh"
36#include "arch/regfile.hh"
37#include "arch/syscallreturn.hh"
38#include "config/full_system.hh"
39#include "cpu/thread_context.hh"
40#include "cpu/thread_state.hh"
41#include "mem/request.hh"
42#include "sim/byteswap.hh"
43#include "sim/eventq.hh"
44#include "sim/host.hh"
45#include "sim/serialize.hh"
46
47class BaseCPU;
48
49#if FULL_SYSTEM
50
51#include "sim/system.hh"
52#include "arch/tlb.hh"
53
54class FunctionProfile;
55class ProfileNode;
56class FunctionalPort;
57class PhysicalPort;
58
59namespace TheISA {
60    namespace Kernel {
61        class Statistics;
62    };
63};
64
65#else // !FULL_SYSTEM
66
67#include "sim/process.hh"
68#include "mem/page_table.hh"
69class TranslatingPort;
70
71#endif // FULL_SYSTEM
72
73/**
74 * The SimpleThread object provides a combination of the ThreadState
75 * object and the ThreadContext interface. It implements the
76 * ThreadContext interface so that a ProxyThreadContext class can be
77 * made using SimpleThread as the template parameter (see
78 * thread_context.hh). It adds to the ThreadState object by adding all
79 * the objects needed for simple functional execution, including a
80 * simple architectural register file, and pointers to the ITB and DTB
81 * in full system mode. For CPU models that do not need more advanced
82 * ways to hold state (i.e. a separate physical register file, or
83 * separate fetch and commit PC's), this SimpleThread class provides
84 * all the necessary state for full architecture-level functional
85 * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
86 * examples.
87 */
88
89class SimpleThread : public ThreadState
90{
91  protected:
92    typedef TheISA::RegFile RegFile;
93    typedef TheISA::MachInst MachInst;
94    typedef TheISA::MiscRegFile MiscRegFile;
95    typedef TheISA::MiscReg MiscReg;
96    typedef TheISA::FloatReg FloatReg;
97    typedef TheISA::FloatRegBits FloatRegBits;
98  public:
99    typedef ThreadContext::Status Status;
100
101  protected:
102    RegFile regs;	// correct-path register context
103
104  public:
105    // pointer to CPU associated with this SimpleThread
106    BaseCPU *cpu;
107
108    ProxyThreadContext<SimpleThread> *tc;
109
110    System *system;
111
112#if FULL_SYSTEM
113    TheISA::ITB *itb;
114    TheISA::DTB *dtb;
115#endif
116
117    // constructor: initialize SimpleThread from given process structure
118#if FULL_SYSTEM
119    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
120                 TheISA::ITB *_itb, TheISA::DTB *_dtb,
121                 bool use_kernel_stats = true);
122#else
123    SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
124#endif
125
126    SimpleThread();
127
128    virtual ~SimpleThread();
129
130    virtual void takeOverFrom(ThreadContext *oldContext);
131
132    void regStats(const std::string &name);
133
134    void copyTC(ThreadContext *context);
135
136    void copyState(ThreadContext *oldContext);
137
138    void serialize(std::ostream &os);
139    void unserialize(Checkpoint *cp, const std::string &section);
140
141    /***************************************************************
142     *  SimpleThread functions to provide CPU with access to various
143     *  state, and to provide address translation methods.
144     **************************************************************/
145
146    /** Returns the pointer to this SimpleThread's ThreadContext. Used
147     *  when a ThreadContext must be passed to objects outside of the
148     *  CPU.
149     */
150    ThreadContext *getTC() { return tc; }
151
152#if FULL_SYSTEM
153    int getInstAsid() { return regs.instAsid(); }
154    int getDataAsid() { return regs.dataAsid(); }
155
156    Fault translateInstReq(RequestPtr &req)
157    {
158        return itb->translate(req, tc);
159    }
160
161    Fault translateDataReadReq(RequestPtr &req)
162    {
163        return dtb->translate(req, tc, false);
164    }
165
166    Fault translateDataWriteReq(RequestPtr &req)
167    {
168        return dtb->translate(req, tc, true);
169    }
170
171    void dumpFuncProfile();
172
173    Fault hwrei();
174
175    bool simPalCheck(int palFunc);
176#else
177
178    Fault translateInstReq(RequestPtr &req)
179    {
180        return process->pTable->translate(req);
181    }
182
183    Fault translateDataReadReq(RequestPtr &req)
184    {
185        return process->pTable->translate(req);
186    }
187
188    Fault translateDataWriteReq(RequestPtr &req)
189    {
190        return process->pTable->translate(req);
191    }
192#endif
193
194    /*******************************************
195     * ThreadContext interface functions.
196     ******************************************/
197
198    BaseCPU *getCpuPtr() { return cpu; }
199
200    int getThreadNum() { return tid; }
201
202#if FULL_SYSTEM
203    System *getSystemPtr() { return system; }
204
205    TheISA::ITB *getITBPtr() { return itb; }
206
207    TheISA::DTB *getDTBPtr() { return dtb; }
208
209    FunctionalPort *getPhysPort() { return physPort; }
210
211    /** Return a virtual port. If no thread context is specified then a static
212     * port is returned. Otherwise a port is created and returned. It must be
213     * deleted by deleteVirtPort(). */
214    VirtualPort *getVirtPort(ThreadContext *tc);
215
216    void delVirtPort(VirtualPort *vp);
217#endif
218
219    Status status() const { return _status; }
220
221    void setStatus(Status newStatus) { _status = newStatus; }
222
223    /// Set the status to Active.  Optional delay indicates number of
224    /// cycles to wait before beginning execution.
225    void activate(int delay = 1);
226
227    /// Set the status to Suspended.
228    void suspend();
229
230    /// Set the status to Unallocated.
231    void deallocate();
232
233    /// Set the status to Halted.
234    void halt();
235
236    virtual bool misspeculating();
237
238    Fault instRead(RequestPtr &req)
239    {
240        panic("instRead not implemented");
241        // return funcPhysMem->read(req, inst);
242        return NoFault;
243    }
244
245    void copyArchRegs(ThreadContext *tc);
246
247    void clearArchRegs() { regs.clear(); }
248
249    //
250    // New accessors for new decoder.
251    //
252    uint64_t readIntReg(int reg_idx)
253    {
254        return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
255    }
256
257    FloatReg readFloatReg(int reg_idx, int width)
258    {
259        return regs.readFloatReg(reg_idx, width);
260    }
261
262    FloatReg readFloatReg(int reg_idx)
263    {
264        return regs.readFloatReg(reg_idx);
265    }
266
267    FloatRegBits readFloatRegBits(int reg_idx, int width)
268    {
269        return regs.readFloatRegBits(reg_idx, width);
270    }
271
272    FloatRegBits readFloatRegBits(int reg_idx)
273    {
274        return regs.readFloatRegBits(reg_idx);
275    }
276
277    void setIntReg(int reg_idx, uint64_t val)
278    {
279        regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
280    }
281
282    void setFloatReg(int reg_idx, FloatReg val, int width)
283    {
284        regs.setFloatReg(reg_idx, val, width);
285    }
286
287    void setFloatReg(int reg_idx, FloatReg val)
288    {
289        regs.setFloatReg(reg_idx, val);
290    }
291
292    void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
293    {
294        regs.setFloatRegBits(reg_idx, val, width);
295    }
296
297    void setFloatRegBits(int reg_idx, FloatRegBits val)
298    {
299        regs.setFloatRegBits(reg_idx, val);
300    }
301
302    uint64_t readPC()
303    {
304        return regs.readPC();
305    }
306
307    void setPC(uint64_t val)
308    {
309        regs.setPC(val);
310    }
311
312    uint64_t readMicroPC()
313    {
314        return microPC;
315    }
316
317    void setMicroPC(uint64_t val)
318    {
319        microPC = val;
320    }
321
322    uint64_t readNextPC()
323    {
324        return regs.readNextPC();
325    }
326
327    void setNextPC(uint64_t val)
328    {
329        regs.setNextPC(val);
330    }
331
332    uint64_t readNextMicroPC()
333    {
334        return nextMicroPC;
335    }
336
337    void setNextMicroPC(uint64_t val)
338    {
339        nextMicroPC = val;
340    }
341
342    uint64_t readNextNPC()
343    {
344        return regs.readNextNPC();
345    }
346
347    void setNextNPC(uint64_t val)
348    {
349        regs.setNextNPC(val);
350    }
351
352    MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
353    {
354        return regs.readMiscRegNoEffect(misc_reg);
355    }
356
357    MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
358    {
359        return regs.readMiscReg(misc_reg, tc);
360    }
361
362    void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
363    {
364        return regs.setMiscRegNoEffect(misc_reg, val);
365    }
366
367    void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
368    {
369        return regs.setMiscReg(misc_reg, val, tc);
370    }
371
372    unsigned readStCondFailures() { return storeCondFailures; }
373
374    void setStCondFailures(unsigned sc_failures)
375    { storeCondFailures = sc_failures; }
376
377#if !FULL_SYSTEM
378    TheISA::IntReg getSyscallArg(int i)
379    {
380        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
381                    TheISA::ArgumentReg0 + i));
382    }
383
384    // used to shift args for indirect syscall
385    void setSyscallArg(int i, TheISA::IntReg val)
386    {
387        regs.setIntReg(TheISA::flattenIntIndex(getTC(),
388                    TheISA::ArgumentReg0 + i), val);
389    }
390
391    void setSyscallReturn(SyscallReturn return_value)
392    {
393        TheISA::setSyscallReturn(return_value, getTC());
394    }
395
396    void syscall(int64_t callnum)
397    {
398        process->syscall(callnum, tc);
399    }
400#endif
401
402    void changeRegFileContext(TheISA::RegContextParam param,
403            TheISA::RegContextVal val)
404    {
405        regs.changeContext(param, val);
406    }
407};
408
409
410// for non-speculative execution context, spec_mode is always false
411inline bool
412SimpleThread::misspeculating()
413{
414    return false;
415}
416
417#endif // __CPU_CPU_EXEC_CONTEXT_HH__
418