simple_thread.hh revision 4488:400afb0dd42d
16019Shines@cs.fsu.edu/* 212495Sgiacomo.travaglini@arm.com * Copyright (c) 2001-2006 The Regents of The University of Michigan 37111Sgblack@eecs.umich.edu * All rights reserved. 47111Sgblack@eecs.umich.edu * 57111Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67111Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77111Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87111Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97111Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107111Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117111Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127111Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137111Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Steve Reinhardt 296019Shines@cs.fsu.edu * Nathan Binkert 306019Shines@cs.fsu.edu */ 316019Shines@cs.fsu.edu 326019Shines@cs.fsu.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 336019Shines@cs.fsu.edu#define __CPU_SIMPLE_THREAD_HH__ 346019Shines@cs.fsu.edu 356019Shines@cs.fsu.edu#include "arch/isa_traits.hh" 366019Shines@cs.fsu.edu#include "arch/regfile.hh" 376019Shines@cs.fsu.edu#include "arch/syscallreturn.hh" 386019Shines@cs.fsu.edu#include "config/full_system.hh" 396019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 406019Shines@cs.fsu.edu#include "cpu/thread_state.hh" 416019Shines@cs.fsu.edu#include "mem/request.hh" 426019Shines@cs.fsu.edu#include "sim/byteswap.hh" 436019Shines@cs.fsu.edu#include "sim/eventq.hh" 446019Shines@cs.fsu.edu#include "sim/host.hh" 456019Shines@cs.fsu.edu#include "sim/serialize.hh" 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.educlass BaseCPU; 487692SAli.Saidi@ARM.com 496242Sgblack@eecs.umich.edu#if FULL_SYSTEM 506019Shines@cs.fsu.edu 5112334Sgabeblack@google.com#include "sim/system.hh" 527408Sgblack@eecs.umich.edu#include "arch/tlb.hh" 536216Snate@binkert.org 547720Sgblack@eecs.umich.educlass FunctionProfile; 556019Shines@cs.fsu.educlass ProfileNode; 566019Shines@cs.fsu.educlass FunctionalPort; 5710037SARM gem5 Developersclass PhysicalPort; 5810037SARM gem5 Developers 596019Shines@cs.fsu.edunamespace TheISA { 606019Shines@cs.fsu.edu namespace Kernel { 617751SAli.Saidi@ARM.com class Statistics; 627751SAli.Saidi@ARM.com }; 637751SAli.Saidi@ARM.com}; 647751SAli.Saidi@ARM.com 657751SAli.Saidi@ARM.com#else // !FULL_SYSTEM 667751SAli.Saidi@ARM.com 677751SAli.Saidi@ARM.com#include "sim/process.hh" 687751SAli.Saidi@ARM.com#include "mem/page_table.hh" 697751SAli.Saidi@ARM.comclass TranslatingPort; 708303SAli.Saidi@ARM.com 717751SAli.Saidi@ARM.com#endif // FULL_SYSTEM 728303SAli.Saidi@ARM.com 738303SAli.Saidi@ARM.com/** 748303SAli.Saidi@ARM.com * The SimpleThread object provides a combination of the ThreadState 757751SAli.Saidi@ARM.com * object and the ThreadContext interface. It implements the 767720Sgblack@eecs.umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 778303SAli.Saidi@ARM.com * made using SimpleThread as the template parameter (see 788303SAli.Saidi@ARM.com * thread_context.hh). It adds to the ThreadState object by adding all 798303SAli.Saidi@ARM.com * the objects needed for simple functional execution, including a 808303SAli.Saidi@ARM.com * simple architectural register file, and pointers to the ITB and DTB 818303SAli.Saidi@ARM.com * in full system mode. For CPU models that do not need more advanced 828303SAli.Saidi@ARM.com * ways to hold state (i.e. a separate physical register file, or 838303SAli.Saidi@ARM.com * separate fetch and commit PC's), this SimpleThread class provides 848303SAli.Saidi@ARM.com * all the necessary state for full architecture-level functional 858303SAli.Saidi@ARM.com * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 868303SAli.Saidi@ARM.com * examples. 878303SAli.Saidi@ARM.com */ 888303SAli.Saidi@ARM.com 898303SAli.Saidi@ARM.comclass SimpleThread : public ThreadState 908303SAli.Saidi@ARM.com{ 917751SAli.Saidi@ARM.com protected: 927751SAli.Saidi@ARM.com typedef TheISA::RegFile RegFile; 937751SAli.Saidi@ARM.com typedef TheISA::MachInst MachInst; 947751SAli.Saidi@ARM.com typedef TheISA::MiscRegFile MiscRegFile; 957720Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 967751SAli.Saidi@ARM.com typedef TheISA::FloatReg FloatReg; 977720Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 987751SAli.Saidi@ARM.com public: 997751SAli.Saidi@ARM.com typedef ThreadContext::Status Status; 1007751SAli.Saidi@ARM.com 1017751SAli.Saidi@ARM.com protected: 1027751SAli.Saidi@ARM.com RegFile regs; // correct-path register context 1037751SAli.Saidi@ARM.com 1046242Sgblack@eecs.umich.edu public: 1057751SAli.Saidi@ARM.com // pointer to CPU associated with this SimpleThread 1067751SAli.Saidi@ARM.com BaseCPU *cpu; 10710407Smitch.hayenga@arm.com 1087751SAli.Saidi@ARM.com ProxyThreadContext<SimpleThread> *tc; 1096019Shines@cs.fsu.edu 1107751SAli.Saidi@ARM.com System *system; 1116246Sgblack@eecs.umich.edu 1127751SAli.Saidi@ARM.com#if FULL_SYSTEM 1137751SAli.Saidi@ARM.com TheISA::ITB *itb; 1147751SAli.Saidi@ARM.com TheISA::DTB *dtb; 1157751SAli.Saidi@ARM.com#endif 1167751SAli.Saidi@ARM.com 1176329Sgblack@eecs.umich.edu // constructor: initialize SimpleThread from given process structure 1187751SAli.Saidi@ARM.com#if FULL_SYSTEM 1196757SAli.Saidi@ARM.com SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1207751SAli.Saidi@ARM.com TheISA::ITB *_itb, TheISA::DTB *_dtb, 1217751SAli.Saidi@ARM.com bool use_kernel_stats = true); 1227751SAli.Saidi@ARM.com#else 12310037SARM gem5 Developers SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 1247751SAli.Saidi@ARM.com#endif 1257638Sgblack@eecs.umich.edu 1267751SAli.Saidi@ARM.com SimpleThread(); 1277751SAli.Saidi@ARM.com 1287751SAli.Saidi@ARM.com virtual ~SimpleThread(); 1297751SAli.Saidi@ARM.com 1307751SAli.Saidi@ARM.com virtual void takeOverFrom(ThreadContext *oldContext); 1317638Sgblack@eecs.umich.edu 1327751SAli.Saidi@ARM.com void regStats(const std::string &name); 1337751SAli.Saidi@ARM.com 1347751SAli.Saidi@ARM.com void copyTC(ThreadContext *context); 1357751SAli.Saidi@ARM.com 1367751SAli.Saidi@ARM.com void copyState(ThreadContext *oldContext); 1377638Sgblack@eecs.umich.edu 1387751SAli.Saidi@ARM.com void serialize(std::ostream &os); 1397751SAli.Saidi@ARM.com void unserialize(Checkpoint *cp, const std::string §ion); 1407751SAli.Saidi@ARM.com 1417751SAli.Saidi@ARM.com /*************************************************************** 1427751SAli.Saidi@ARM.com * SimpleThread functions to provide CPU with access to various 1436757SAli.Saidi@ARM.com * state, and to provide address translation methods. 14410037SARM gem5 Developers **************************************************************/ 14510037SARM gem5 Developers 14610037SARM gem5 Developers /** Returns the pointer to this SimpleThread's ThreadContext. Used 14710037SARM gem5 Developers * when a ThreadContext must be passed to objects outside of the 1487751SAli.Saidi@ARM.com * CPU. 14910037SARM gem5 Developers */ 15010037SARM gem5 Developers ThreadContext *getTC() { return tc; } 1517751SAli.Saidi@ARM.com 1527640Sgblack@eecs.umich.edu#if FULL_SYSTEM 15310037SARM gem5 Developers int getInstAsid() { return regs.instAsid(); } 15410037SARM gem5 Developers int getDataAsid() { return regs.dataAsid(); } 1557751SAli.Saidi@ARM.com 15610037SARM gem5 Developers Fault translateInstReq(RequestPtr &req) 15710037SARM gem5 Developers { 1587751SAli.Saidi@ARM.com return itb->translate(req, tc); 1597640Sgblack@eecs.umich.edu } 16012496Sgiacomo.travaglini@arm.com 16112496Sgiacomo.travaglini@arm.com Fault translateDataReadReq(RequestPtr &req) 16212496Sgiacomo.travaglini@arm.com { 16312496Sgiacomo.travaglini@arm.com return dtb->translate(req, tc, false); 16412496Sgiacomo.travaglini@arm.com } 16512496Sgiacomo.travaglini@arm.com 16612496Sgiacomo.travaglini@arm.com Fault translateDataWriteReq(RequestPtr &req) 16712496Sgiacomo.travaglini@arm.com { 16812496Sgiacomo.travaglini@arm.com return dtb->translate(req, tc, true); 16912496Sgiacomo.travaglini@arm.com } 17012496Sgiacomo.travaglini@arm.com 17112496Sgiacomo.travaglini@arm.com void dumpFuncProfile(); 17212496Sgiacomo.travaglini@arm.com 17312496Sgiacomo.travaglini@arm.com Fault hwrei(); 17412496Sgiacomo.travaglini@arm.com 17512496Sgiacomo.travaglini@arm.com bool simPalCheck(int palFunc); 17612496Sgiacomo.travaglini@arm.com#else 17712496Sgiacomo.travaglini@arm.com 17812494Schuan.zhu@arm.com Fault translateInstReq(RequestPtr &req) 17912494Schuan.zhu@arm.com { 18010037SARM gem5 Developers return process->pTable->translate(req); 18110037SARM gem5 Developers } 18210037SARM gem5 Developers 18310037SARM gem5 Developers Fault translateDataReadReq(RequestPtr &req) 18412788Sgiacomo.travaglini@arm.com { 18512788Sgiacomo.travaglini@arm.com return process->pTable->translate(req); 18612788Sgiacomo.travaglini@arm.com } 18712788Sgiacomo.travaglini@arm.com 18812788Sgiacomo.travaglini@arm.com Fault translateDataWriteReq(RequestPtr &req) 18912788Sgiacomo.travaglini@arm.com { 19012788Sgiacomo.travaglini@arm.com return process->pTable->translate(req); 19112788Sgiacomo.travaglini@arm.com } 19212788Sgiacomo.travaglini@arm.com#endif 19312788Sgiacomo.travaglini@arm.com 19412788Sgiacomo.travaglini@arm.com /******************************************* 19512788Sgiacomo.travaglini@arm.com * ThreadContext interface functions. 19612788Sgiacomo.travaglini@arm.com ******************************************/ 19712788Sgiacomo.travaglini@arm.com 19812788Sgiacomo.travaglini@arm.com BaseCPU *getCpuPtr() { return cpu; } 19912788Sgiacomo.travaglini@arm.com 20012788Sgiacomo.travaglini@arm.com int getThreadNum() { return tid; } 20112788Sgiacomo.travaglini@arm.com 20212788Sgiacomo.travaglini@arm.com#if FULL_SYSTEM 20312788Sgiacomo.travaglini@arm.com System *getSystemPtr() { return system; } 20411514Sandreas.sandberg@arm.com 20511514Sandreas.sandberg@arm.com TheISA::ITB *getITBPtr() { return itb; } 20611514Sandreas.sandberg@arm.com 20711514Sandreas.sandberg@arm.com TheISA::DTB *getDTBPtr() { return dtb; } 20811514Sandreas.sandberg@arm.com 20911514Sandreas.sandberg@arm.com FunctionalPort *getPhysPort() { return physPort; } 21011514Sandreas.sandberg@arm.com 21111514Sandreas.sandberg@arm.com /** Return a virtual port. If no thread context is specified then a static 21211514Sandreas.sandberg@arm.com * port is returned. Otherwise a port is created and returned. It must be 21311514Sandreas.sandberg@arm.com * deleted by deleteVirtPort(). */ 21410037SARM gem5 Developers VirtualPort *getVirtPort(ThreadContext *tc); 21510037SARM gem5 Developers 21610037SARM gem5 Developers void delVirtPort(VirtualPort *vp); 21710037SARM gem5 Developers#endif 21810037SARM gem5 Developers 21910037SARM gem5 Developers Status status() const { return _status; } 22010037SARM gem5 Developers 22110854SNathanael.Premillieu@arm.com void setStatus(Status newStatus) { _status = newStatus; } 22210854SNathanael.Premillieu@arm.com 22310037SARM gem5 Developers /// Set the status to Active. Optional delay indicates number of 22410037SARM gem5 Developers /// cycles to wait before beginning execution. 2257751SAli.Saidi@ARM.com void activate(int delay = 1); 22610037SARM gem5 Developers 2277751SAli.Saidi@ARM.com /// Set the status to Suspended. 22810037SARM gem5 Developers void suspend(); 22910037SARM gem5 Developers 23010037SARM gem5 Developers /// Set the status to Unallocated. 23110037SARM gem5 Developers void deallocate(); 23210037SARM gem5 Developers 23310037SARM gem5 Developers /// Set the status to Halted. 23410037SARM gem5 Developers void halt(); 23510037SARM gem5 Developers 23610037SARM gem5 Developers virtual bool misspeculating(); 23710037SARM gem5 Developers 23810037SARM gem5 Developers Fault instRead(RequestPtr &req) 23910037SARM gem5 Developers { 2407751SAli.Saidi@ARM.com panic("instRead not implemented"); 2417640Sgblack@eecs.umich.edu // return funcPhysMem->read(req, inst); 24212495Sgiacomo.travaglini@arm.com return NoFault; 24312495Sgiacomo.travaglini@arm.com } 24412495Sgiacomo.travaglini@arm.com 24512495Sgiacomo.travaglini@arm.com void copyArchRegs(ThreadContext *tc); 24612495Sgiacomo.travaglini@arm.com 24712495Sgiacomo.travaglini@arm.com void clearArchRegs() { regs.clear(); } 24812495Sgiacomo.travaglini@arm.com 24912495Sgiacomo.travaglini@arm.com // 25012495Sgiacomo.travaglini@arm.com // New accessors for new decoder. 25110037SARM gem5 Developers // 25210037SARM gem5 Developers uint64_t readIntReg(int reg_idx) 25310037SARM gem5 Developers { 25410037SARM gem5 Developers return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); 25510037SARM gem5 Developers } 25610037SARM gem5 Developers 25710037SARM gem5 Developers FloatReg readFloatReg(int reg_idx, int width) 25810037SARM gem5 Developers { 25910037SARM gem5 Developers return regs.readFloatReg(reg_idx, width); 26010037SARM gem5 Developers } 26110037SARM gem5 Developers 26210037SARM gem5 Developers FloatReg readFloatReg(int reg_idx) 26310037SARM gem5 Developers { 26410037SARM gem5 Developers return regs.readFloatReg(reg_idx); 26510037SARM gem5 Developers } 26610037SARM gem5 Developers 26710037SARM gem5 Developers FloatRegBits readFloatRegBits(int reg_idx, int width) 26810037SARM gem5 Developers { 26910037SARM gem5 Developers return regs.readFloatRegBits(reg_idx, width); 27010037SARM gem5 Developers } 27110037SARM gem5 Developers 27210037SARM gem5 Developers FloatRegBits readFloatRegBits(int reg_idx) 27310037SARM gem5 Developers { 27410037SARM gem5 Developers return regs.readFloatRegBits(reg_idx); 27510037SARM gem5 Developers } 27610037SARM gem5 Developers 27710037SARM gem5 Developers void setIntReg(int reg_idx, uint64_t val) 27810037SARM gem5 Developers { 27910037SARM gem5 Developers regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); 28010037SARM gem5 Developers } 28110037SARM gem5 Developers 28210037SARM gem5 Developers void setFloatReg(int reg_idx, FloatReg val, int width) 28310037SARM gem5 Developers { 28410037SARM gem5 Developers regs.setFloatReg(reg_idx, val, width); 28510037SARM gem5 Developers } 28610037SARM gem5 Developers 28710037SARM gem5 Developers void setFloatReg(int reg_idx, FloatReg val) 28810037SARM gem5 Developers { 28910037SARM gem5 Developers regs.setFloatReg(reg_idx, val); 29010037SARM gem5 Developers } 29110037SARM gem5 Developers 29210037SARM gem5 Developers void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 29310037SARM gem5 Developers { 29410037SARM gem5 Developers regs.setFloatRegBits(reg_idx, val, width); 29510037SARM gem5 Developers } 29610037SARM gem5 Developers 29710037SARM gem5 Developers void setFloatRegBits(int reg_idx, FloatRegBits val) 29810037SARM gem5 Developers { 29910037SARM gem5 Developers regs.setFloatRegBits(reg_idx, val); 30010037SARM gem5 Developers } 30110037SARM gem5 Developers 30210037SARM gem5 Developers uint64_t readPC() 30310037SARM gem5 Developers { 30410037SARM gem5 Developers return regs.readPC(); 30510037SARM gem5 Developers } 30610037SARM gem5 Developers 30710037SARM gem5 Developers void setPC(uint64_t val) 30810037SARM gem5 Developers { 30910037SARM gem5 Developers regs.setPC(val); 31010037SARM gem5 Developers } 31110037SARM gem5 Developers 31210037SARM gem5 Developers uint64_t readMicroPC() 31310037SARM gem5 Developers { 31410037SARM gem5 Developers return microPC; 31511582SDylan.Johnson@ARM.com } 31611582SDylan.Johnson@ARM.com 31710037SARM gem5 Developers void setMicroPC(uint64_t val) 31810037SARM gem5 Developers { 31910037SARM gem5 Developers microPC = val; 32010037SARM gem5 Developers } 32110037SARM gem5 Developers 3227707Sgblack@eecs.umich.edu uint64_t readNextPC() 3236757SAli.Saidi@ARM.com { 3247693SAli.Saidi@ARM.com return regs.readNextPC(); 3257693SAli.Saidi@ARM.com } 3267720Sgblack@eecs.umich.edu 32710417Sandreas.hansson@arm.com void setNextPC(uint64_t val) 3287720Sgblack@eecs.umich.edu { 3297720Sgblack@eecs.umich.edu regs.setNextPC(val); 3307720Sgblack@eecs.umich.edu } 3317720Sgblack@eecs.umich.edu 3327752SWilliam.Wang@arm.com uint64_t readNextMicroPC() 3337752SWilliam.Wang@arm.com { 3347752SWilliam.Wang@arm.com return nextMicroPC; 3358300Schander.sudanthi@arm.com } 3368300Schander.sudanthi@arm.com 3378300Schander.sudanthi@arm.com void setNextMicroPC(uint64_t val) 3388300Schander.sudanthi@arm.com { 3398300Schander.sudanthi@arm.com nextMicroPC = val; 3408300Schander.sudanthi@arm.com } 34110037SARM gem5 Developers 34210037SARM gem5 Developers uint64_t readNextNPC() 34310037SARM gem5 Developers { 34410037SARM gem5 Developers return regs.readNextNPC(); 34510037SARM gem5 Developers } 34610037SARM gem5 Developers 34710037SARM gem5 Developers void setNextNPC(uint64_t val) 34810037SARM gem5 Developers { 34910037SARM gem5 Developers regs.setNextNPC(val); 35010037SARM gem5 Developers } 35110037SARM gem5 Developers 35210037SARM gem5 Developers MiscReg readMiscRegNoEffect(int misc_reg) 35310037SARM gem5 Developers { 35410037SARM gem5 Developers return regs.readMiscRegNoEffect(misc_reg); 35510037SARM gem5 Developers } 35610037SARM gem5 Developers 35710037SARM gem5 Developers MiscReg readMiscReg(int misc_reg) 35810037SARM gem5 Developers { 35910037SARM gem5 Developers return regs.readMiscReg(misc_reg, tc); 36010037SARM gem5 Developers } 36110037SARM gem5 Developers 36210037SARM gem5 Developers void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 36310037SARM gem5 Developers { 36410037SARM gem5 Developers return regs.setMiscRegNoEffect(misc_reg, val); 36510037SARM gem5 Developers } 36610037SARM gem5 Developers 36710037SARM gem5 Developers void setMiscReg(int misc_reg, const MiscReg &val) 36810037SARM gem5 Developers { 36910037SARM gem5 Developers return regs.setMiscReg(misc_reg, val, tc); 37010037SARM gem5 Developers } 37112526Schuan.zhu@arm.com 37212526Schuan.zhu@arm.com unsigned readStCondFailures() { return storeCondFailures; } 37312526Schuan.zhu@arm.com 37412526Schuan.zhu@arm.com void setStCondFailures(unsigned sc_failures) 37512526Schuan.zhu@arm.com { storeCondFailures = sc_failures; } 3768902Sandreas.hansson@arm.com 3776019Shines@cs.fsu.edu#if !FULL_SYSTEM 3786019Shines@cs.fsu.edu TheISA::IntReg getSyscallArg(int i) 379 { 380 return regs.readIntReg(TheISA::flattenIntIndex(getTC(), 381 TheISA::ArgumentReg0 + i)); 382 } 383 384 // used to shift args for indirect syscall 385 void setSyscallArg(int i, TheISA::IntReg val) 386 { 387 regs.setIntReg(TheISA::flattenIntIndex(getTC(), 388 TheISA::ArgumentReg0 + i), val); 389 } 390 391 void setSyscallReturn(SyscallReturn return_value) 392 { 393 TheISA::setSyscallReturn(return_value, getTC()); 394 } 395 396 void syscall(int64_t callnum) 397 { 398 process->syscall(callnum, tc); 399 } 400#endif 401 402 void changeRegFileContext(TheISA::RegContextParam param, 403 TheISA::RegContextVal val) 404 { 405 regs.changeContext(param, val); 406 } 407}; 408 409 410// for non-speculative execution context, spec_mode is always false 411inline bool 412SimpleThread::misspeculating() 413{ 414 return false; 415} 416 417#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 418