simple_thread.hh revision 3733:2e34561f1eba
1/* 2 * Copyright (c) 2001-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __CPU_SIMPLE_THREAD_HH__ 33#define __CPU_SIMPLE_THREAD_HH__ 34 35#include "arch/isa_traits.hh" 36#include "config/full_system.hh" 37#include "cpu/thread_context.hh" 38#include "cpu/thread_state.hh" 39#include "mem/physical.hh" 40#include "mem/request.hh" 41#include "sim/byteswap.hh" 42#include "sim/eventq.hh" 43#include "sim/host.hh" 44#include "sim/serialize.hh" 45 46class BaseCPU; 47 48#if FULL_SYSTEM 49 50#include "sim/system.hh" 51#include "arch/tlb.hh" 52 53class FunctionProfile; 54class ProfileNode; 55class FunctionalPort; 56class PhysicalPort; 57 58namespace TheISA { 59 namespace Kernel { 60 class Statistics; 61 }; 62}; 63 64#else // !FULL_SYSTEM 65 66#include "sim/process.hh" 67#include "mem/page_table.hh" 68class TranslatingPort; 69 70#endif // FULL_SYSTEM 71 72/** 73 * The SimpleThread object provides a combination of the ThreadState 74 * object and the ThreadContext interface. It implements the 75 * ThreadContext interface so that a ProxyThreadContext class can be 76 * made using SimpleThread as the template parameter (see 77 * thread_context.hh). It adds to the ThreadState object by adding all 78 * the objects needed for simple functional execution, including a 79 * simple architectural register file, and pointers to the ITB and DTB 80 * in full system mode. For CPU models that do not need more advanced 81 * ways to hold state (i.e. a separate physical register file, or 82 * separate fetch and commit PC's), this SimpleThread class provides 83 * all the necessary state for full architecture-level functional 84 * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 85 * examples. 86 */ 87 88class SimpleThread : public ThreadState 89{ 90 protected: 91 typedef TheISA::RegFile RegFile; 92 typedef TheISA::MachInst MachInst; 93 typedef TheISA::MiscRegFile MiscRegFile; 94 typedef TheISA::MiscReg MiscReg; 95 typedef TheISA::FloatReg FloatReg; 96 typedef TheISA::FloatRegBits FloatRegBits; 97 public: 98 typedef ThreadContext::Status Status; 99 100 protected: 101 RegFile regs; // correct-path register context 102 103 public: 104 // pointer to CPU associated with this SimpleThread 105 BaseCPU *cpu; 106 107 ProxyThreadContext<SimpleThread> *tc; 108 109 System *system; 110 111#if FULL_SYSTEM 112 TheISA::ITB *itb; 113 TheISA::DTB *dtb; 114#endif 115 116 // constructor: initialize SimpleThread from given process structure 117#if FULL_SYSTEM 118 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 119 TheISA::ITB *_itb, TheISA::DTB *_dtb, 120 bool use_kernel_stats = true); 121#else 122 SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 123#endif 124 125 SimpleThread(); 126 127 virtual ~SimpleThread(); 128 129 virtual void takeOverFrom(ThreadContext *oldContext); 130 131 void regStats(const std::string &name); 132 133 void copyTC(ThreadContext *context); 134 135 void copyState(ThreadContext *oldContext); 136 137 void serialize(std::ostream &os); 138 void unserialize(Checkpoint *cp, const std::string §ion); 139 140 /*************************************************************** 141 * SimpleThread functions to provide CPU with access to various 142 * state, and to provide address translation methods. 143 **************************************************************/ 144 145 /** Returns the pointer to this SimpleThread's ThreadContext. Used 146 * when a ThreadContext must be passed to objects outside of the 147 * CPU. 148 */ 149 ThreadContext *getTC() { return tc; } 150 151#if FULL_SYSTEM 152 int getInstAsid() { return regs.instAsid(); } 153 int getDataAsid() { return regs.dataAsid(); } 154 155 Fault translateInstReq(RequestPtr &req) 156 { 157 return itb->translate(req, tc); 158 } 159 160 Fault translateDataReadReq(RequestPtr &req) 161 { 162 return dtb->translate(req, tc, false); 163 } 164 165 Fault translateDataWriteReq(RequestPtr &req) 166 { 167 return dtb->translate(req, tc, true); 168 } 169 170 void dumpFuncProfile(); 171 172 Fault hwrei(); 173 174 bool simPalCheck(int palFunc); 175#else 176 177 Fault translateInstReq(RequestPtr &req) 178 { 179 return process->pTable->translate(req); 180 } 181 182 Fault translateDataReadReq(RequestPtr &req) 183 { 184 return process->pTable->translate(req); 185 } 186 187 Fault translateDataWriteReq(RequestPtr &req) 188 { 189 return process->pTable->translate(req); 190 } 191#endif 192 193 /******************************************* 194 * ThreadContext interface functions. 195 ******************************************/ 196 197 BaseCPU *getCpuPtr() { return cpu; } 198 199 int getThreadNum() { return tid; } 200 201#if FULL_SYSTEM 202 System *getSystemPtr() { return system; } 203 204 TheISA::ITB *getITBPtr() { return itb; } 205 206 TheISA::DTB *getDTBPtr() { return dtb; } 207 208 FunctionalPort *getPhysPort() { return physPort; } 209 210 /** Return a virtual port. If no thread context is specified then a static 211 * port is returned. Otherwise a port is created and returned. It must be 212 * deleted by deleteVirtPort(). */ 213 VirtualPort *getVirtPort(ThreadContext *tc); 214 215 void delVirtPort(VirtualPort *vp); 216#endif 217 218 Status status() const { return _status; } 219 220 void setStatus(Status newStatus) { _status = newStatus; } 221 222 /// Set the status to Active. Optional delay indicates number of 223 /// cycles to wait before beginning execution. 224 void activate(int delay = 1); 225 226 /// Set the status to Suspended. 227 void suspend(); 228 229 /// Set the status to Unallocated. 230 void deallocate(); 231 232 /// Set the status to Halted. 233 void halt(); 234 235 virtual bool misspeculating(); 236 237 Fault instRead(RequestPtr &req) 238 { 239 panic("instRead not implemented"); 240 // return funcPhysMem->read(req, inst); 241 return NoFault; 242 } 243 244 void copyArchRegs(ThreadContext *tc); 245 246 void clearArchRegs() { regs.clear(); } 247 248 // 249 // New accessors for new decoder. 250 // 251 uint64_t readIntReg(int reg_idx) 252 { 253 return regs.readIntReg(reg_idx); 254 } 255 256 FloatReg readFloatReg(int reg_idx, int width) 257 { 258 return regs.readFloatReg(reg_idx, width); 259 } 260 261 FloatReg readFloatReg(int reg_idx) 262 { 263 return regs.readFloatReg(reg_idx); 264 } 265 266 FloatRegBits readFloatRegBits(int reg_idx, int width) 267 { 268 return regs.readFloatRegBits(reg_idx, width); 269 } 270 271 FloatRegBits readFloatRegBits(int reg_idx) 272 { 273 return regs.readFloatRegBits(reg_idx); 274 } 275 276 void setIntReg(int reg_idx, uint64_t val) 277 { 278 regs.setIntReg(reg_idx, val); 279 } 280 281 void setFloatReg(int reg_idx, FloatReg val, int width) 282 { 283 regs.setFloatReg(reg_idx, val, width); 284 } 285 286 void setFloatReg(int reg_idx, FloatReg val) 287 { 288 regs.setFloatReg(reg_idx, val); 289 } 290 291 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 292 { 293 regs.setFloatRegBits(reg_idx, val, width); 294 } 295 296 void setFloatRegBits(int reg_idx, FloatRegBits val) 297 { 298 regs.setFloatRegBits(reg_idx, val); 299 } 300 301 uint64_t readPC() 302 { 303 return regs.readPC(); 304 } 305 306 void setPC(uint64_t val) 307 { 308 regs.setPC(val); 309 } 310 311 uint64_t readMicroPC() 312 { 313 return microPC; 314 } 315 316 void setMicroPC(uint64_t val) 317 { 318 microPC = val; 319 } 320 321 uint64_t readNextPC() 322 { 323 return regs.readNextPC(); 324 } 325 326 void setNextPC(uint64_t val) 327 { 328 regs.setNextPC(val); 329 } 330 331 uint64_t readNextMicroPC() 332 { 333 return nextMicroPC; 334 } 335 336 void setNextMicroPC(uint64_t val) 337 { 338 nextMicroPC = val; 339 } 340 341 uint64_t readNextNPC() 342 { 343 return regs.readNextNPC(); 344 } 345 346 void setNextNPC(uint64_t val) 347 { 348 regs.setNextNPC(val); 349 } 350 351 MiscReg readMiscReg(int misc_reg) 352 { 353 return regs.readMiscReg(misc_reg); 354 } 355 356 MiscReg readMiscRegWithEffect(int misc_reg) 357 { 358 return regs.readMiscRegWithEffect(misc_reg, tc); 359 } 360 361 void setMiscReg(int misc_reg, const MiscReg &val) 362 { 363 return regs.setMiscReg(misc_reg, val); 364 } 365 366 void setMiscRegWithEffect(int misc_reg, const MiscReg &val) 367 { 368 return regs.setMiscRegWithEffect(misc_reg, val, tc); 369 } 370 371 unsigned readStCondFailures() { return storeCondFailures; } 372 373 void setStCondFailures(unsigned sc_failures) 374 { storeCondFailures = sc_failures; } 375 376#if !FULL_SYSTEM 377 TheISA::IntReg getSyscallArg(int i) 378 { 379 return regs.readIntReg(TheISA::ArgumentReg0 + i); 380 } 381 382 // used to shift args for indirect syscall 383 void setSyscallArg(int i, TheISA::IntReg val) 384 { 385 regs.setIntReg(TheISA::ArgumentReg0 + i, val); 386 } 387 388 void setSyscallReturn(SyscallReturn return_value) 389 { 390 TheISA::setSyscallReturn(return_value, ®s); 391 } 392 393 void syscall(int64_t callnum) 394 { 395 process->syscall(callnum, tc); 396 } 397#endif 398 399 void changeRegFileContext(TheISA::RegContextParam param, 400 TheISA::RegContextVal val) 401 { 402 regs.changeContext(param, val); 403 } 404}; 405 406 407// for non-speculative execution context, spec_mode is always false 408inline bool 409SimpleThread::misspeculating() 410{ 411 return false; 412} 413 414#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 415