simple_thread.hh revision 2400
12315SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 148733Sgeoffrey.blake@arm.com * this software without specific prior written permission. 152332SN/A * 162315SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172315SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182315SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192315SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202315SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212315SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222315SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232315SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242315SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252315SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262315SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272315SN/A */ 282315SN/A 292315SN/A#ifndef __CPU_EXEC_CONTEXT_HH__ 302315SN/A#define __CPU_EXEC_CONTEXT_HH__ 312315SN/A 322315SN/A#include "config/full_system.hh" 332315SN/A#include "mem/physical.hh" 342315SN/A#include "mem/request.hh" 352315SN/A#include "sim/host.hh" 362315SN/A#include "sim/serialize.hh" 372315SN/A#include "targetarch/byte_swap.hh" 382315SN/A#include "mem/translating_port.hh" 392315SN/A 402689Sktlim@umich.educlass BaseCPU; 412689Sktlim@umich.edu 422315SN/A#if FULL_SYSTEM 432315SN/A 442315SN/A#include "sim/system.hh" 452315SN/A#include "targetarch/alpha_memory.hh" 462315SN/A 472315SN/Aclass FunctionProfile; 488229Snate@binkert.orgclass ProfileNode; 492315SN/Aclass MemoryController; 502315SN/Anamespace Kernel { class Binning; class Statistics; } 512669Sktlim@umich.edu 522315SN/A#else // !FULL_SYSTEM 532315SN/A 542315SN/A#include "sim/process.hh" 5510319SAndreas.Sandberg@ARM.com 568229Snate@binkert.org#endif // FULL_SYSTEM 572683Sktlim@umich.edu 582315SN/A// 598733Sgeoffrey.blake@arm.com// The ExecContext object represents a functional context for 608733Sgeoffrey.blake@arm.com// instruction execution. It incorporates everything required for 612315SN/A// architecture-level functional simulation of a single thread. 622315SN/A// 632315SN/A 643468Sgblack@eecs.umich.educlass ExecContext 653468Sgblack@eecs.umich.edu{ 666022Sgblack@eecs.umich.edu public: 673468Sgblack@eecs.umich.edu enum Status 682315SN/A { 692315SN/A /// Initialized but not running yet. All CPUs start in 702315SN/A /// this state, but most transition to Active on cycle 1. 712680Sktlim@umich.edu /// In MP or SMT systems, non-primary contexts will stay 722669Sktlim@umich.edu /// in this state until a thread is assigned to them. 732315SN/A Unallocated, 742350SN/A 752350SN/A /// Running. Instructions should be executed only when 762350SN/A /// the context is in this state. 772350SN/A Active, 782350SN/A 792350SN/A /// Temporarily inactive. Entered while waiting for 802350SN/A /// synchronization, etc. 812350SN/A Suspended, 822350SN/A 832350SN/A /// Permanently shut down. Entered when target executes 842680Sktlim@umich.edu /// m5exit pseudo-instruction. When all contexts enter 852683Sktlim@umich.edu /// this state, the simulation will terminate. 862680Sktlim@umich.edu Halted 872350SN/A }; 882680Sktlim@umich.edu 892350SN/A private: 9010319SAndreas.Sandberg@ARM.com Status _status; 912315SN/A 922315SN/A public: 932315SN/A Status status() const { return _status; } 942669Sktlim@umich.edu 952669Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 962315SN/A /// cycles to wait before beginning execution. 978832SAli.Saidi@ARM.com void activate(int delay = 1); 988832SAli.Saidi@ARM.com 998832SAli.Saidi@ARM.com /// Set the status to Suspended. 1002315SN/A void suspend(); 1012315SN/A 1022315SN/A /// Set the status to Unallocated. 1035529Snate@binkert.org void deallocate(); 1042315SN/A 1052315SN/A /// Set the status to Halted. 1062315SN/A void halt(); 1072315SN/A 1082315SN/A public: 1099608Sandreas.hansson@arm.com RegFile regs; // correct-path register context 1102679Sktlim@umich.edu 1119608Sandreas.hansson@arm.com // pointer to CPU associated with this context 1122679Sktlim@umich.edu BaseCPU *cpu; 1139608Sandreas.hansson@arm.com 1148887Sgeoffrey.blake@arm.com // Current instruction 1159176Sandreas.hansson@arm.com MachInst inst; 1169176Sandreas.hansson@arm.com 1179176Sandreas.hansson@arm.com // Index of hardware thread context on the CPU that this represents. 1188887Sgeoffrey.blake@arm.com int thread_num; 1198887Sgeoffrey.blake@arm.com 1208887Sgeoffrey.blake@arm.com // ID of this context w.r.t. the System or Process object to which 1219608Sandreas.hansson@arm.com // it belongs. For full-system mode, this is the system CPU ID. 1228887Sgeoffrey.blake@arm.com int cpu_id; 1239176Sandreas.hansson@arm.com 1249176Sandreas.hansson@arm.com System *system; 1259176Sandreas.hansson@arm.com 1268887Sgeoffrey.blake@arm.com /// Port that syscalls can use to access memory (provides translation step). 1278887Sgeoffrey.blake@arm.com TranslatingPort *port; 1282679Sktlim@umich.edu// Memory *mem; 1299176Sandreas.hansson@arm.com 1309176Sandreas.hansson@arm.com#if FULL_SYSTEM 1319176Sandreas.hansson@arm.com AlphaITB *itb; 1329176Sandreas.hansson@arm.com AlphaDTB *dtb; 1339176Sandreas.hansson@arm.com 1349176Sandreas.hansson@arm.com // the following two fields are redundant, since we can always 1359608Sandreas.hansson@arm.com // look them up through the system pointer, but we'll leave them 1369608Sandreas.hansson@arm.com // here for now for convenience 1372315SN/A MemoryController *memctrl; 1382680Sktlim@umich.edu// PhysicalMemory *physmem; 1392315SN/A 1406022Sgblack@eecs.umich.edu Kernel::Binning *kernelBinning; 1416022Sgblack@eecs.umich.edu Kernel::Statistics *kernelStats; 1422315SN/A bool bin; 1432315SN/A bool fnbin; 1442315SN/A 1452315SN/A FunctionProfile *profile; 1462315SN/A ProfileNode *profileNode; 1472315SN/A Addr profilePC; 1488733Sgeoffrey.blake@arm.com void dumpFuncProfile(); 1498733Sgeoffrey.blake@arm.com 1508733Sgeoffrey.blake@arm.com#else 1518733Sgeoffrey.blake@arm.com Process *process; 1522315SN/A 1532315SN/A // Address space ID. Note that this is used for TIMING cache 1548733Sgeoffrey.blake@arm.com // simulation only; all functional memory accesses should use 1558733Sgeoffrey.blake@arm.com // one of the FunctionalMemory pointers above. 1568733Sgeoffrey.blake@arm.com short asid; 1572315SN/A 1582679Sktlim@umich.edu#endif 1592679Sktlim@umich.edu 1602315SN/A /** 1612315SN/A * Temporary storage to pass the source address from copy_load to 1628733Sgeoffrey.blake@arm.com * copy_store. 1632315SN/A * @todo Remove this temporary when we have a better way to do it. 1642315SN/A */ 1652315SN/A Addr copySrcAddr; 1662315SN/A /** 1672315SN/A * Temp storage for the physical source address of a copy. 1682315SN/A * @todo Remove this temporary when we have a better way to do it. 1692315SN/A */ 1709176Sandreas.hansson@arm.com Addr copySrcPhysAddr; 1719176Sandreas.hansson@arm.com 1729176Sandreas.hansson@arm.com 1739176Sandreas.hansson@arm.com /* 1749176Sandreas.hansson@arm.com * number of executed instructions, for matching with syscall trace 1758733Sgeoffrey.blake@arm.com * points in EIO files. 1768733Sgeoffrey.blake@arm.com */ 1778733Sgeoffrey.blake@arm.com Counter func_exe_inst; 1788887Sgeoffrey.blake@arm.com 1798887Sgeoffrey.blake@arm.com // 1808887Sgeoffrey.blake@arm.com // Count failed store conditionals so we can warn of apparent 1818887Sgeoffrey.blake@arm.com // application deadlock situations. 1828887Sgeoffrey.blake@arm.com unsigned storeCondFailures; 1838887Sgeoffrey.blake@arm.com 1842315SN/A // constructor: initialize context from given process structure 1852930Sktlim@umich.edu#if FULL_SYSTEM 1862315SN/A ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 1872315SN/A AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 1882315SN/A#else 1892315SN/A ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 1902315SN/A Memory *_mem, Process *_process, int _asid); 1912315SN/A#endif 19210905Sandreas.sandberg@arm.com virtual ~ExecContext(); 19310905Sandreas.sandberg@arm.com 1942315SN/A virtual void takeOverFrom(ExecContext *oldContext); 1952315SN/A 1962315SN/A void regStats(const std::string &name); 1972315SN/A 19810319SAndreas.Sandberg@ARM.com void serialize(std::ostream &os); 1992315SN/A void unserialize(Checkpoint *cp, const std::string §ion); 2002315SN/A 2012315SN/A#if FULL_SYSTEM 2022315SN/A bool validInstAddr(Addr addr) { return true; } 2032315SN/A bool validDataAddr(Addr addr) { return true; } 2042315SN/A int getInstAsid() { return regs.instAsid(); } 2052315SN/A int getDataAsid() { return regs.dataAsid(); } 2062315SN/A 2072315SN/A Fault translateInstReq(CpuRequestPtr &req) 2082315SN/A { 2092315SN/A return itb->translate(req); 2102315SN/A } 21110319SAndreas.Sandberg@ARM.com 2122315SN/A Fault translateDataReadReq(CpuRequestPtr &req) 2132683Sktlim@umich.edu { 2142315SN/A return dtb->translate(req, false); 2152315SN/A } 2163735Sstever@eecs.umich.edu 2172315SN/A Fault translateDataWriteReq(CpuRequestPtr &req) 2189918Ssteve.reinhardt@amd.com { 2192683Sktlim@umich.edu return dtb->translate(req, true); 2202315SN/A } 2212315SN/A 2223735Sstever@eecs.umich.edu#else 2232669Sktlim@umich.edu bool validInstAddr(Addr addr) 2249918Ssteve.reinhardt@amd.com { return process->validInstAddr(addr); } 2252683Sktlim@umich.edu 2262315SN/A bool validDataAddr(Addr addr) 2272315SN/A { return process->validDataAddr(addr); } 22810319SAndreas.Sandberg@ARM.com 2299920Syasuko.eckert@amd.com int getInstAsid() { return asid; } 2309920Syasuko.eckert@amd.com int getDataAsid() { return asid; } 2319920Syasuko.eckert@amd.com 2329920Syasuko.eckert@amd.com Fault translateInstReq(CpuRequestPtr &req) 2339920Syasuko.eckert@amd.com { 2348733Sgeoffrey.blake@arm.com return process->pTable->translate(req); 2358733Sgeoffrey.blake@arm.com } 2368733Sgeoffrey.blake@arm.com 2378733Sgeoffrey.blake@arm.com Fault translateDataReadReq(CpuRequestPtr &req) 2388733Sgeoffrey.blake@arm.com { 2398733Sgeoffrey.blake@arm.com return process->pTable->translate(req); 2408733Sgeoffrey.blake@arm.com } 2418733Sgeoffrey.blake@arm.com 24210319SAndreas.Sandberg@ARM.com Fault translateDataWriteReq(CpuRequestPtr &req) 2432315SN/A { 2442683Sktlim@umich.edu return process->pTable->translate(req); 2458733Sgeoffrey.blake@arm.com } 2462315SN/A 2472315SN/A#endif 2483735Sstever@eecs.umich.edu 2492669Sktlim@umich.edu/* 2509918Ssteve.reinhardt@amd.com template <class T> 2512683Sktlim@umich.edu Fault read(CpuRequestPtr &req, T &data) 2528733Sgeoffrey.blake@arm.com { 2532315SN/A#if FULL_SYSTEM && defined(TARGET_ALPHA) 2542315SN/A if (req->flags & LOCKED) { 2553735Sstever@eecs.umich.edu MiscRegFile *cregs = &req->xc->regs.miscRegs; 2563735Sstever@eecs.umich.edu cregs->lock_addr = req->paddr; 2572315SN/A cregs->lock_flag = true; 2589918Ssteve.reinhardt@amd.com } 2592683Sktlim@umich.edu#endif 2608733Sgeoffrey.blake@arm.com 2612315SN/A Fault error; 2622315SN/A error = mem->prot_read(req->paddr, data, req->size); 26310319SAndreas.Sandberg@ARM.com data = gtoh(data); 2649920Syasuko.eckert@amd.com return error; 2659920Syasuko.eckert@amd.com } 2669920Syasuko.eckert@amd.com 2679920Syasuko.eckert@amd.com template <class T> 2689920Syasuko.eckert@amd.com Fault write(CpuRequestPtr &req, T &data) 2699920Syasuko.eckert@amd.com { 2708733Sgeoffrey.blake@arm.com#if FULL_SYSTEM && defined(TARGET_ALPHA) 2718733Sgeoffrey.blake@arm.com 2728733Sgeoffrey.blake@arm.com MiscRegFile *cregs; 2738733Sgeoffrey.blake@arm.com 2748733Sgeoffrey.blake@arm.com // If this is a store conditional, act appropriately 2752669Sktlim@umich.edu if (req->flags & LOCKED) { 27610319SAndreas.Sandberg@ARM.com cregs = &req->xc->regs.miscRegs; 2778733Sgeoffrey.blake@arm.com 2788733Sgeoffrey.blake@arm.com if (req->flags & UNCACHEABLE) { 2798733Sgeoffrey.blake@arm.com // Don't update result register (see stq_c in isa_desc) 2808733Sgeoffrey.blake@arm.com req->result = 2; 2818733Sgeoffrey.blake@arm.com req->xc->storeCondFailures = 0;//Needed? [RGD] 2828733Sgeoffrey.blake@arm.com } else { 2838733Sgeoffrey.blake@arm.com req->result = cregs->lock_flag; 2848733Sgeoffrey.blake@arm.com if (!cregs->lock_flag || 2858733Sgeoffrey.blake@arm.com ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 2868733Sgeoffrey.blake@arm.com cregs->lock_flag = false; 2872315SN/A if (((++req->xc->storeCondFailures) % 100000) == 0) { 28810698Sandreas.hansson@arm.com std::cerr << "Warning: " 2894172Ssaidi@eecs.umich.edu << req->xc->storeCondFailures 2904172Ssaidi@eecs.umich.edu << " consecutive store conditional failures " 2914172Ssaidi@eecs.umich.edu << "on cpu " << req->xc->cpu_id 2924172Ssaidi@eecs.umich.edu << std::endl; 2932315SN/A } 2942315SN/A return No_Fault; 2952683Sktlim@umich.edu } 2962315SN/A else req->xc->storeCondFailures = 0; 2972315SN/A } 2984172Ssaidi@eecs.umich.edu } 2992315SN/A 30010034SGeoffrey.Blake@arm.com // Need to clear any locked flags on other proccessors for 3014172Ssaidi@eecs.umich.edu // this address. Only do this for succsful Store Conditionals 3024172Ssaidi@eecs.umich.edu // and all other stores (WH64?). Unsuccessful Store 3032315SN/A // Conditionals would have returned above, and wouldn't fall 3042315SN/A // through. 3053468Sgblack@eecs.umich.edu for (int i = 0; i < system->execContexts.size(); i++){ 3062315SN/A cregs = &system->execContexts[i]->regs.miscRegs; 30710034SGeoffrey.Blake@arm.com if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 3082315SN/A cregs->lock_flag = false; 3092683Sktlim@umich.edu } 3102315SN/A } 3112315SN/A 3128733Sgeoffrey.blake@arm.com#endif 3138733Sgeoffrey.blake@arm.com return mem->prot_write(req->paddr, (T)htog(data), req->size); 3149918Ssteve.reinhardt@amd.com } 3158733Sgeoffrey.blake@arm.com*/ 3168733Sgeoffrey.blake@arm.com virtual bool misspeculating(); 3178733Sgeoffrey.blake@arm.com 3188733Sgeoffrey.blake@arm.com 3198733Sgeoffrey.blake@arm.com MachInst getInst() { return inst; } 3208733Sgeoffrey.blake@arm.com 3219918Ssteve.reinhardt@amd.com void setInst(MachInst new_inst) 32210034SGeoffrey.Blake@arm.com { 3238733Sgeoffrey.blake@arm.com inst = new_inst; 3248888Sgeoffrey.blake@arm.com } 3258888Sgeoffrey.blake@arm.com 32610319SAndreas.Sandberg@ARM.com Fault instRead(CpuRequestPtr &req) 3278888Sgeoffrey.blake@arm.com { 3288888Sgeoffrey.blake@arm.com panic("instRead not implemented"); 3298888Sgeoffrey.blake@arm.com // return funcPhysMem->read(req, inst); 3308888Sgeoffrey.blake@arm.com return No_Fault; 3318888Sgeoffrey.blake@arm.com } 33210319SAndreas.Sandberg@ARM.com 3338888Sgeoffrey.blake@arm.com // 3348888Sgeoffrey.blake@arm.com // New accessors for new decoder. 3358888Sgeoffrey.blake@arm.com // 3368888Sgeoffrey.blake@arm.com uint64_t readIntReg(int reg_idx) 3378888Sgeoffrey.blake@arm.com { 3388733Sgeoffrey.blake@arm.com return regs.intRegFile[reg_idx]; 3398733Sgeoffrey.blake@arm.com } 3408733Sgeoffrey.blake@arm.com 3418733Sgeoffrey.blake@arm.com float readFloatRegSingle(int reg_idx) 3428733Sgeoffrey.blake@arm.com { 3438733Sgeoffrey.blake@arm.com return (float)regs.floatRegFile.d[reg_idx]; 3448733Sgeoffrey.blake@arm.com } 3452315SN/A 3465358Sgblack@eecs.umich.edu double readFloatRegDouble(int reg_idx) 3475358Sgblack@eecs.umich.edu { 3485358Sgblack@eecs.umich.edu return regs.floatRegFile.d[reg_idx]; 3495358Sgblack@eecs.umich.edu } 3505358Sgblack@eecs.umich.edu 3515358Sgblack@eecs.umich.edu uint64_t readFloatRegInt(int reg_idx) 35210529Smorr@cs.wisc.edu { 35310529Smorr@cs.wisc.edu return regs.floatRegFile.q[reg_idx]; 35410529Smorr@cs.wisc.edu } 35510529Smorr@cs.wisc.edu 35610529Smorr@cs.wisc.edu void setIntReg(int reg_idx, uint64_t val) 35710529Smorr@cs.wisc.edu { 35810529Smorr@cs.wisc.edu regs.intRegFile[reg_idx] = val; 3595358Sgblack@eecs.umich.edu } 3605358Sgblack@eecs.umich.edu 3615358Sgblack@eecs.umich.edu void setFloatRegSingle(int reg_idx, float val) 3625358Sgblack@eecs.umich.edu { 3635358Sgblack@eecs.umich.edu regs.floatRegFile.d[reg_idx] = (double)val; 3645358Sgblack@eecs.umich.edu } 3655358Sgblack@eecs.umich.edu 3665358Sgblack@eecs.umich.edu void setFloatRegDouble(int reg_idx, double val) 3675358Sgblack@eecs.umich.edu { 3685358Sgblack@eecs.umich.edu regs.floatRegFile.d[reg_idx] = val; 3698733Sgeoffrey.blake@arm.com } 3708733Sgeoffrey.blake@arm.com 3718733Sgeoffrey.blake@arm.com void setFloatRegInt(int reg_idx, uint64_t val) 3728733Sgeoffrey.blake@arm.com { 37310319SAndreas.Sandberg@ARM.com regs.floatRegFile.q[reg_idx] = val; 37410319SAndreas.Sandberg@ARM.com } 37510319SAndreas.Sandberg@ARM.com 37610319SAndreas.Sandberg@ARM.com uint64_t readPC() 37710319SAndreas.Sandberg@ARM.com { 3788733Sgeoffrey.blake@arm.com return regs.pc; 3798733Sgeoffrey.blake@arm.com } 3808733Sgeoffrey.blake@arm.com 3815702Ssaidi@eecs.umich.edu void setNextPC(uint64_t val) 3825702Ssaidi@eecs.umich.edu { 3838733Sgeoffrey.blake@arm.com regs.npc = val; 3842315SN/A } 3852332SN/A 38610319SAndreas.Sandberg@ARM.com uint64_t readUniq() 3872315SN/A { 3882315SN/A return regs.miscRegs.uniq; 3892315SN/A } 3902315SN/A 3912732Sktlim@umich.edu void setUniq(uint64_t val) 3922315SN/A { 3932732Sktlim@umich.edu regs.miscRegs.uniq = val; 3948733Sgeoffrey.blake@arm.com } 3958733Sgeoffrey.blake@arm.com 3962315SN/A uint64_t readFpcr() 3972732Sktlim@umich.edu { 3982732Sktlim@umich.edu return regs.miscRegs.fpcr; 3992680Sktlim@umich.edu } 4002683Sktlim@umich.edu 4012315SN/A void setFpcr(uint64_t val) 4022315SN/A { 4032669Sktlim@umich.edu regs.miscRegs.fpcr = val; 4042679Sktlim@umich.edu } 4052315SN/A 4062315SN/A#if FULL_SYSTEM 4072315SN/A uint64_t readIpr(int idx, Fault &fault); 4088733Sgeoffrey.blake@arm.com Fault setIpr(int idx, uint64_t val); 4092315SN/A int readIntrFlag() { return regs.intrflag; } 4102354SN/A void setIntrFlag(int val) { regs.intrflag = val; } 4112732Sktlim@umich.edu Fault hwrei(); 4122315SN/A bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 4132315SN/A void ev5_trap(Fault fault); 4142315SN/A bool simPalCheck(int palFunc); 4152315SN/A#endif 4162350SN/A 4172350SN/A /** Meant to be more generic trap function to be 4182350SN/A * called when an instruction faults. 4192350SN/A * @param fault The fault generated by executing the instruction. 4202350SN/A * @todo How to do this properly so it's dependent upon ISA only? 4212350SN/A */ 4228733Sgeoffrey.blake@arm.com 4232315SN/A void trap(Fault fault); 4242315SN/A 4258733Sgeoffrey.blake@arm.com#if !FULL_SYSTEM 4268733Sgeoffrey.blake@arm.com IntReg getSyscallArg(int i) 4278733Sgeoffrey.blake@arm.com { 4282315SN/A return regs.intRegFile[ArgumentReg0 + i]; 4292315SN/A } 4309023Sgblack@eecs.umich.edu 4312315SN/A // used to shift args for indirect syscall 4322315SN/A void setSyscallArg(int i, IntReg val) 4332840Sktlim@umich.edu { 4342315SN/A regs.intRegFile[ArgumentReg0 + i] = val; 4352315SN/A } 43610379Sandreas.hansson@arm.com 4378733Sgeoffrey.blake@arm.com void setSyscallReturn(SyscallReturn return_value) 4382732Sktlim@umich.edu { 4392315SN/A // check for error condition. Alpha syscall convention is to 4402315SN/A // indicate success/failure in reg a3 (r19) and put the 4412315SN/A // return value itself in the standard return value reg (v0). 4422315SN/A const int RegA3 = 19; // only place this is used 4432315SN/A if (return_value.successful()) { 44410935Snilay@cs.wisc.edu // no error 4458733Sgeoffrey.blake@arm.com regs.intRegFile[RegA3] = 0; 4462732Sktlim@umich.edu regs.intRegFile[ReturnValueReg] = return_value.value(); 4472732Sktlim@umich.edu } else { 4482732Sktlim@umich.edu // got an error, return details 4492732Sktlim@umich.edu regs.intRegFile[RegA3] = (IntReg) -1; 4502360SN/A regs.intRegFile[ReturnValueReg] = -return_value.value(); 4512732Sktlim@umich.edu } 4522360SN/A } 4532354SN/A 4542360SN/A void syscall() 4552732Sktlim@umich.edu { 4562732Sktlim@umich.edu process->syscall(this); 4572732Sktlim@umich.edu } 4582732Sktlim@umich.edu#endif 4592354SN/A}; 4602354SN/A 4612354SN/A 4622354SN/A// for non-speculative execution context, spec_mode is always false 4632315SN/Ainline bool 4642315SN/AExecContext::misspeculating() 4652315SN/A{ 4662315SN/A return false; 4672315SN/A} 4682315SN/A 469#endif // __CPU_EXEC_CONTEXT_HH__ 470