simple_thread.hh revision 2398
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/physical.hh" 34#include "mem/request.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "targetarch/byte_swap.hh" 38 39class Memory; 40class BaseCPU; 41 42#if FULL_SYSTEM 43 44#include "sim/system.hh" 45#include "targetarch/alpha_memory.hh" 46 47class FunctionProfile; 48class ProfileNode; 49class MemoryController; 50namespace Kernel { class Binning; class Statistics; } 51 52#else // !FULL_SYSTEM 53 54#include "sim/process.hh" 55 56#endif // FULL_SYSTEM 57 58// 59// The ExecContext object represents a functional context for 60// instruction execution. It incorporates everything required for 61// architecture-level functional simulation of a single thread. 62// 63 64class ExecContext 65{ 66 public: 67 enum Status 68 { 69 /// Initialized but not running yet. All CPUs start in 70 /// this state, but most transition to Active on cycle 1. 71 /// In MP or SMT systems, non-primary contexts will stay 72 /// in this state until a thread is assigned to them. 73 Unallocated, 74 75 /// Running. Instructions should be executed only when 76 /// the context is in this state. 77 Active, 78 79 /// Temporarily inactive. Entered while waiting for 80 /// synchronization, etc. 81 Suspended, 82 83 /// Permanently shut down. Entered when target executes 84 /// m5exit pseudo-instruction. When all contexts enter 85 /// this state, the simulation will terminate. 86 Halted 87 }; 88 89 private: 90 Status _status; 91 92 public: 93 Status status() const { return _status; } 94 95 /// Set the status to Active. Optional delay indicates number of 96 /// cycles to wait before beginning execution. 97 void activate(int delay = 1); 98 99 /// Set the status to Suspended. 100 void suspend(); 101 102 /// Set the status to Unallocated. 103 void deallocate(); 104 105 /// Set the status to Halted. 106 void halt(); 107 108 public: 109 RegFile regs; // correct-path register context 110 111 // pointer to CPU associated with this context 112 BaseCPU *cpu; 113 114 // Current instruction 115 MachInst inst; 116 117 // Index of hardware thread context on the CPU that this represents. 118 int thread_num; 119 120 // ID of this context w.r.t. the System or Process object to which 121 // it belongs. For full-system mode, this is the system CPU ID. 122 int cpu_id; 123 124 System *system; 125// Memory *mem; 126 127#if FULL_SYSTEM 128 AlphaITB *itb; 129 AlphaDTB *dtb; 130 131 // the following two fields are redundant, since we can always 132 // look them up through the system pointer, but we'll leave them 133 // here for now for convenience 134 MemoryController *memctrl; 135// PhysicalMemory *physmem; 136 137 Kernel::Binning *kernelBinning; 138 Kernel::Statistics *kernelStats; 139 bool bin; 140 bool fnbin; 141 142 FunctionProfile *profile; 143 ProfileNode *profileNode; 144 Addr profilePC; 145 void dumpFuncProfile(); 146 147#else 148 Process *process; 149 150 // Address space ID. Note that this is used for TIMING cache 151 // simulation only; all functional memory accesses should use 152 // one of the FunctionalMemory pointers above. 153 short asid; 154 155#endif 156 157 /** 158 * Temporary storage to pass the source address from copy_load to 159 * copy_store. 160 * @todo Remove this temporary when we have a better way to do it. 161 */ 162 Addr copySrcAddr; 163 /** 164 * Temp storage for the physical source address of a copy. 165 * @todo Remove this temporary when we have a better way to do it. 166 */ 167 Addr copySrcPhysAddr; 168 169 170 /* 171 * number of executed instructions, for matching with syscall trace 172 * points in EIO files. 173 */ 174 Counter func_exe_inst; 175 176 // 177 // Count failed store conditionals so we can warn of apparent 178 // application deadlock situations. 179 unsigned storeCondFailures; 180 181 // constructor: initialize context from given process structure 182#if FULL_SYSTEM 183 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 184 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 185#else 186 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 187 Memory *_mem, Process *_process, int _asid); 188#endif 189 virtual ~ExecContext(); 190 191 virtual void takeOverFrom(ExecContext *oldContext); 192 193 void regStats(const std::string &name); 194 195 void serialize(std::ostream &os); 196 void unserialize(Checkpoint *cp, const std::string §ion); 197 198#if FULL_SYSTEM 199 bool validInstAddr(Addr addr) { return true; } 200 bool validDataAddr(Addr addr) { return true; } 201 int getInstAsid() { return regs.instAsid(); } 202 int getDataAsid() { return regs.dataAsid(); } 203 204 Fault translateInstReq(CpuRequestPtr &req) 205 { 206 return itb->translate(req); 207 } 208 209 Fault translateDataReadReq(CpuRequestPtr &req) 210 { 211 return dtb->translate(req, false); 212 } 213 214 Fault translateDataWriteReq(CpuRequestPtr &req) 215 { 216 return dtb->translate(req, true); 217 } 218 219#else 220 bool validInstAddr(Addr addr) 221 { return process->validInstAddr(addr); } 222 223 bool validDataAddr(Addr addr) 224 { return process->validDataAddr(addr); } 225 226 int getInstAsid() { return asid; } 227 int getDataAsid() { return asid; } 228 229 Fault translateInstReq(CpuRequestPtr &req) 230 { 231 return process->pTable->translate(req); 232 } 233 234 Fault translateDataReadReq(CpuRequestPtr &req) 235 { 236 return process->pTable->translate(req); 237 } 238 239 Fault translateDataWriteReq(CpuRequestPtr &req) 240 { 241 return process->pTable->translate(req); 242 } 243 244#endif 245 246/* 247 template <class T> 248 Fault read(CpuRequestPtr &req, T &data) 249 { 250#if FULL_SYSTEM && defined(TARGET_ALPHA) 251 if (req->flags & LOCKED) { 252 MiscRegFile *cregs = &req->xc->regs.miscRegs; 253 cregs->lock_addr = req->paddr; 254 cregs->lock_flag = true; 255 } 256#endif 257 258 Fault error; 259 error = mem->prot_read(req->paddr, data, req->size); 260 data = gtoh(data); 261 return error; 262 } 263 264 template <class T> 265 Fault write(CpuRequestPtr &req, T &data) 266 { 267#if FULL_SYSTEM && defined(TARGET_ALPHA) 268 269 MiscRegFile *cregs; 270 271 // If this is a store conditional, act appropriately 272 if (req->flags & LOCKED) { 273 cregs = &req->xc->regs.miscRegs; 274 275 if (req->flags & UNCACHEABLE) { 276 // Don't update result register (see stq_c in isa_desc) 277 req->result = 2; 278 req->xc->storeCondFailures = 0;//Needed? [RGD] 279 } else { 280 req->result = cregs->lock_flag; 281 if (!cregs->lock_flag || 282 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 283 cregs->lock_flag = false; 284 if (((++req->xc->storeCondFailures) % 100000) == 0) { 285 std::cerr << "Warning: " 286 << req->xc->storeCondFailures 287 << " consecutive store conditional failures " 288 << "on cpu " << req->xc->cpu_id 289 << std::endl; 290 } 291 return No_Fault; 292 } 293 else req->xc->storeCondFailures = 0; 294 } 295 } 296 297 // Need to clear any locked flags on other proccessors for 298 // this address. Only do this for succsful Store Conditionals 299 // and all other stores (WH64?). Unsuccessful Store 300 // Conditionals would have returned above, and wouldn't fall 301 // through. 302 for (int i = 0; i < system->execContexts.size(); i++){ 303 cregs = &system->execContexts[i]->regs.miscRegs; 304 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 305 cregs->lock_flag = false; 306 } 307 } 308 309#endif 310 return mem->prot_write(req->paddr, (T)htog(data), req->size); 311 } 312*/ 313 virtual bool misspeculating(); 314 315 316 MachInst getInst() { return inst; } 317 318 void setInst(MachInst new_inst) 319 { 320 inst = new_inst; 321 } 322 323 Fault instRead(CpuRequestPtr &req) 324 { 325 panic("instRead not implemented"); 326 // return funcPhysMem->read(req, inst); 327 return No_Fault; 328 } 329 330 // 331 // New accessors for new decoder. 332 // 333 uint64_t readIntReg(int reg_idx) 334 { 335 return regs.intRegFile[reg_idx]; 336 } 337 338 float readFloatRegSingle(int reg_idx) 339 { 340 return (float)regs.floatRegFile.d[reg_idx]; 341 } 342 343 double readFloatRegDouble(int reg_idx) 344 { 345 return regs.floatRegFile.d[reg_idx]; 346 } 347 348 uint64_t readFloatRegInt(int reg_idx) 349 { 350 return regs.floatRegFile.q[reg_idx]; 351 } 352 353 void setIntReg(int reg_idx, uint64_t val) 354 { 355 regs.intRegFile[reg_idx] = val; 356 } 357 358 void setFloatRegSingle(int reg_idx, float val) 359 { 360 regs.floatRegFile.d[reg_idx] = (double)val; 361 } 362 363 void setFloatRegDouble(int reg_idx, double val) 364 { 365 regs.floatRegFile.d[reg_idx] = val; 366 } 367 368 void setFloatRegInt(int reg_idx, uint64_t val) 369 { 370 regs.floatRegFile.q[reg_idx] = val; 371 } 372 373 uint64_t readPC() 374 { 375 return regs.pc; 376 } 377 378 void setNextPC(uint64_t val) 379 { 380 regs.npc = val; 381 } 382 383 uint64_t readUniq() 384 { 385 return regs.miscRegs.uniq; 386 } 387 388 void setUniq(uint64_t val) 389 { 390 regs.miscRegs.uniq = val; 391 } 392 393 uint64_t readFpcr() 394 { 395 return regs.miscRegs.fpcr; 396 } 397 398 void setFpcr(uint64_t val) 399 { 400 regs.miscRegs.fpcr = val; 401 } 402 403#if FULL_SYSTEM 404 uint64_t readIpr(int idx, Fault &fault); 405 Fault setIpr(int idx, uint64_t val); 406 int readIntrFlag() { return regs.intrflag; } 407 void setIntrFlag(int val) { regs.intrflag = val; } 408 Fault hwrei(); 409 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 410 void ev5_trap(Fault fault); 411 bool simPalCheck(int palFunc); 412#endif 413 414 /** Meant to be more generic trap function to be 415 * called when an instruction faults. 416 * @param fault The fault generated by executing the instruction. 417 * @todo How to do this properly so it's dependent upon ISA only? 418 */ 419 420 void trap(Fault fault); 421 422#if !FULL_SYSTEM 423 IntReg getSyscallArg(int i) 424 { 425 return regs.intRegFile[ArgumentReg0 + i]; 426 } 427 428 // used to shift args for indirect syscall 429 void setSyscallArg(int i, IntReg val) 430 { 431 regs.intRegFile[ArgumentReg0 + i] = val; 432 } 433 434 void setSyscallReturn(SyscallReturn return_value) 435 { 436 // check for error condition. Alpha syscall convention is to 437 // indicate success/failure in reg a3 (r19) and put the 438 // return value itself in the standard return value reg (v0). 439 const int RegA3 = 19; // only place this is used 440 if (return_value.successful()) { 441 // no error 442 regs.intRegFile[RegA3] = 0; 443 regs.intRegFile[ReturnValueReg] = return_value.value(); 444 } else { 445 // got an error, return details 446 regs.intRegFile[RegA3] = (IntReg) -1; 447 regs.intRegFile[ReturnValueReg] = -return_value.value(); 448 } 449 } 450 451 void syscall() 452 { 453 process->syscall(this); 454 } 455#endif 456}; 457 458 459// for non-speculative execution context, spec_mode is always false 460inline bool 461ExecContext::misspeculating() 462{ 463 return false; 464} 465 466#endif // __CPU_EXEC_CONTEXT_HH__ 467