simple_thread.hh revision 13582:989577bf6abc
13101Sstever@eecs.umich.edu/* 28579Ssteve.reinhardt@amd.com * Copyright (c) 2011-2012, 2016 ARM Limited 33101Sstever@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 43101Sstever@eecs.umich.edu * All rights reserved 53101Sstever@eecs.umich.edu * 63101Sstever@eecs.umich.edu * The license below extends only to copyright in the software and shall 73101Sstever@eecs.umich.edu * not be construed as granting a license to any other intellectual 83101Sstever@eecs.umich.edu * property including but not limited to intellectual property relating 93101Sstever@eecs.umich.edu * to a hardware implementation of the functionality of the software 103101Sstever@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 113101Sstever@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 123101Sstever@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 133101Sstever@eecs.umich.edu * modified or unmodified, in source code or in binary form. 143101Sstever@eecs.umich.edu * 153101Sstever@eecs.umich.edu * Copyright (c) 2001-2006 The Regents of The University of Michigan 163101Sstever@eecs.umich.edu * All rights reserved. 173101Sstever@eecs.umich.edu * 183101Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 193101Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 203101Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 213101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 223101Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 233101Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 243101Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 253101Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 263101Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 273101Sstever@eecs.umich.edu * this software without specific prior written permission. 283101Sstever@eecs.umich.edu * 293101Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307778Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 313101Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 323101Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 333101Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 343101Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 353101Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 363101Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 373101Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 383101Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 393101Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 403101Sstever@eecs.umich.edu * 413101Sstever@eecs.umich.edu * Authors: Steve Reinhardt 423101Sstever@eecs.umich.edu * Nathan Binkert 433101Sstever@eecs.umich.edu */ 443101Sstever@eecs.umich.edu 453101Sstever@eecs.umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 463101Sstever@eecs.umich.edu#define __CPU_SIMPLE_THREAD_HH__ 473101Sstever@eecs.umich.edu 483101Sstever@eecs.umich.edu#include "arch/decoder.hh" 493885Sbinkertn@umich.edu#include "arch/generic/tlb.hh" 503885Sbinkertn@umich.edu#include "arch/isa.hh" 514762Snate@binkert.org#include "arch/isa_traits.hh" 523885Sbinkertn@umich.edu#include "arch/registers.hh" 533885Sbinkertn@umich.edu#include "arch/types.hh" 547528Ssteve.reinhardt@amd.com#include "base/types.hh" 553885Sbinkertn@umich.edu#include "config/the_isa.hh" 564380Sbinkertn@umich.edu#include "cpu/thread_context.hh" 574167Sbinkertn@umich.edu#include "cpu/thread_state.hh" 583102Sstever@eecs.umich.edu#include "debug/CCRegs.hh" 593101Sstever@eecs.umich.edu#include "debug/FloatRegs.hh" 604762Snate@binkert.org#include "debug/IntRegs.hh" 614762Snate@binkert.org#include "debug/VecRegs.hh" 624762Snate@binkert.org#include "mem/page_table.hh" 634762Snate@binkert.org#include "mem/request.hh" 644762Snate@binkert.org#include "sim/byteswap.hh" 654762Snate@binkert.org#include "sim/eventq.hh" 664762Snate@binkert.org#include "sim/process.hh" 674762Snate@binkert.org#include "sim/serialize.hh" 684762Snate@binkert.org#include "sim/system.hh" 695033Smilesck@eecs.umich.edu 705033Smilesck@eecs.umich.educlass BaseCPU; 715033Smilesck@eecs.umich.educlass CheckerCPU; 725033Smilesck@eecs.umich.edu 735033Smilesck@eecs.umich.educlass FunctionProfile; 745033Smilesck@eecs.umich.educlass ProfileNode; 755033Smilesck@eecs.umich.edu 765033Smilesck@eecs.umich.edunamespace TheISA { 775033Smilesck@eecs.umich.edu namespace Kernel { 785033Smilesck@eecs.umich.edu class Statistics; 793101Sstever@eecs.umich.edu } 803101Sstever@eecs.umich.edu} 813101Sstever@eecs.umich.edu 825033Smilesck@eecs.umich.edu/** 833101Sstever@eecs.umich.edu * The SimpleThread object provides a combination of the ThreadState 848596Ssteve.reinhardt@amd.com * object and the ThreadContext interface. It implements the 858596Ssteve.reinhardt@amd.com * ThreadContext interface so that a ProxyThreadContext class can be 868596Ssteve.reinhardt@amd.com * made using SimpleThread as the template parameter (see 878596Ssteve.reinhardt@amd.com * thread_context.hh). It adds to the ThreadState object by adding all 887673Snate@binkert.org * the objects needed for simple functional execution, including a 897673Snate@binkert.org * simple architectural register file, and pointers to the ITB and DTB 907673Snate@binkert.org * in full system mode. For CPU models that do not need more advanced 917673Snate@binkert.org * ways to hold state (i.e. a separate physical register file, or 928596Ssteve.reinhardt@amd.com * separate fetch and commit PC's), this SimpleThread class provides 938596Ssteve.reinhardt@amd.com * all the necessary state for full architecture-level functional 948596Ssteve.reinhardt@amd.com * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 957673Snate@binkert.org * examples. 967673Snate@binkert.org */ 977673Snate@binkert.org 983101Sstever@eecs.umich.educlass SimpleThread : public ThreadState 993101Sstever@eecs.umich.edu{ 1003101Sstever@eecs.umich.edu protected: 1013101Sstever@eecs.umich.edu typedef TheISA::MachInst MachInst; 1023101Sstever@eecs.umich.edu typedef TheISA::CCReg CCReg; 1033101Sstever@eecs.umich.edu using VecRegContainer = TheISA::VecRegContainer; 1043101Sstever@eecs.umich.edu using VecElem = TheISA::VecElem; 1053101Sstever@eecs.umich.edu public: 1063101Sstever@eecs.umich.edu typedef ThreadContext::Status Status; 1073101Sstever@eecs.umich.edu 1083101Sstever@eecs.umich.edu protected: 1093101Sstever@eecs.umich.edu RegVal floatRegs[TheISA::NumFloatRegs]; 1103101Sstever@eecs.umich.edu RegVal intRegs[TheISA::NumIntRegs]; 1113101Sstever@eecs.umich.edu VecRegContainer vecRegs[TheISA::NumVecRegs]; 1123101Sstever@eecs.umich.edu#ifdef ISA_HAS_CC_REGS 1133101Sstever@eecs.umich.edu TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1143101Sstever@eecs.umich.edu#endif 1153101Sstever@eecs.umich.edu TheISA::ISA *const isa; // one "instance" of the current ISA. 1163101Sstever@eecs.umich.edu 1173101Sstever@eecs.umich.edu TheISA::PCState _pcState; 1183101Sstever@eecs.umich.edu 1193101Sstever@eecs.umich.edu /** Did this instruction execute or is it predicated false */ 1203101Sstever@eecs.umich.edu bool predicate; 1213101Sstever@eecs.umich.edu 1223101Sstever@eecs.umich.edu public: 1233101Sstever@eecs.umich.edu std::string name() const 1243101Sstever@eecs.umich.edu { 1253101Sstever@eecs.umich.edu return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1263101Sstever@eecs.umich.edu } 1273101Sstever@eecs.umich.edu 1283101Sstever@eecs.umich.edu ProxyThreadContext<SimpleThread> *tc; 1293101Sstever@eecs.umich.edu 1303101Sstever@eecs.umich.edu System *system; 1313101Sstever@eecs.umich.edu 1323101Sstever@eecs.umich.edu BaseTLB *itb; 1333101Sstever@eecs.umich.edu BaseTLB *dtb; 1343101Sstever@eecs.umich.edu 1353101Sstever@eecs.umich.edu TheISA::Decoder decoder; 1363101Sstever@eecs.umich.edu 1373101Sstever@eecs.umich.edu // constructor: initialize SimpleThread from given process structure 1383101Sstever@eecs.umich.edu // FS 1393101Sstever@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1403101Sstever@eecs.umich.edu BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1413101Sstever@eecs.umich.edu bool use_kernel_stats = true); 1423101Sstever@eecs.umich.edu // SE 1433101Sstever@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1445033Smilesck@eecs.umich.edu Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1456656Snate@binkert.org TheISA::ISA *_isa); 1465033Smilesck@eecs.umich.edu 1475033Smilesck@eecs.umich.edu virtual ~SimpleThread(); 1485033Smilesck@eecs.umich.edu 1493101Sstever@eecs.umich.edu virtual void takeOverFrom(ThreadContext *oldContext); 1503101Sstever@eecs.umich.edu 1513101Sstever@eecs.umich.edu void regStats(const std::string &name); 1523101Sstever@eecs.umich.edu 1533101Sstever@eecs.umich.edu void copyState(ThreadContext *oldContext); 1543101Sstever@eecs.umich.edu 1553101Sstever@eecs.umich.edu void serialize(CheckpointOut &cp) const override; 1563101Sstever@eecs.umich.edu void unserialize(CheckpointIn &cp) override; 1573101Sstever@eecs.umich.edu void startup(); 1583101Sstever@eecs.umich.edu 1593101Sstever@eecs.umich.edu /*************************************************************** 1603101Sstever@eecs.umich.edu * SimpleThread functions to provide CPU with access to various 1613101Sstever@eecs.umich.edu * state. 1623102Sstever@eecs.umich.edu **************************************************************/ 1633101Sstever@eecs.umich.edu 1643101Sstever@eecs.umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1653101Sstever@eecs.umich.edu * when a ThreadContext must be passed to objects outside of the 1667673Snate@binkert.org * CPU. 1678607Sgblack@eecs.umich.edu */ 1687673Snate@binkert.org ThreadContext *getTC() { return tc; } 1693101Sstever@eecs.umich.edu 1707673Snate@binkert.org void demapPage(Addr vaddr, uint64_t asn) 1717673Snate@binkert.org { 1723101Sstever@eecs.umich.edu itb->demapPage(vaddr, asn); 1737673Snate@binkert.org dtb->demapPage(vaddr, asn); 1747673Snate@binkert.org } 1753101Sstever@eecs.umich.edu 1763101Sstever@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1773101Sstever@eecs.umich.edu { 1783101Sstever@eecs.umich.edu itb->demapPage(vaddr, asn); 1793101Sstever@eecs.umich.edu } 1803101Sstever@eecs.umich.edu 1815033Smilesck@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1825475Snate@binkert.org { 1835475Snate@binkert.org dtb->demapPage(vaddr, asn); 1845475Snate@binkert.org } 1855475Snate@binkert.org 1863101Sstever@eecs.umich.edu void dumpFuncProfile(); 1873101Sstever@eecs.umich.edu 1883101Sstever@eecs.umich.edu Fault hwrei(); 1894762Snate@binkert.org 1904762Snate@binkert.org bool simPalCheck(int palFunc); 1914762Snate@binkert.org 1923101Sstever@eecs.umich.edu /******************************************* 1938460SAli.Saidi@ARM.com * ThreadContext interface functions. 1948459SAli.Saidi@ARM.com ******************************************/ 1958459SAli.Saidi@ARM.com 1968459SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return baseCpu; } 1973101Sstever@eecs.umich.edu 1987528Ssteve.reinhardt@amd.com BaseTLB *getITBPtr() { return itb; } 1997528Ssteve.reinhardt@amd.com 2007528Ssteve.reinhardt@amd.com BaseTLB *getDTBPtr() { return dtb; } 2017528Ssteve.reinhardt@amd.com 2027528Ssteve.reinhardt@amd.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2037528Ssteve.reinhardt@amd.com 2043101Sstever@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2057528Ssteve.reinhardt@amd.com 2067528Ssteve.reinhardt@amd.com System *getSystemPtr() { return system; } 2077528Ssteve.reinhardt@amd.com 2087528Ssteve.reinhardt@amd.com Status status() const { return _status; } 2097528Ssteve.reinhardt@amd.com 2107528Ssteve.reinhardt@amd.com void setStatus(Status newStatus) { _status = newStatus; } 2117528Ssteve.reinhardt@amd.com 2127528Ssteve.reinhardt@amd.com /// Set the status to Active. 2137528Ssteve.reinhardt@amd.com void activate(); 2147528Ssteve.reinhardt@amd.com 2158321Ssteve.reinhardt@amd.com /// Set the status to Suspended. 2168321Ssteve.reinhardt@amd.com void suspend(); 2177528Ssteve.reinhardt@amd.com 2187528Ssteve.reinhardt@amd.com /// Set the status to Halted. 2197528Ssteve.reinhardt@amd.com void halt(); 2207528Ssteve.reinhardt@amd.com 2217528Ssteve.reinhardt@amd.com void copyArchRegs(ThreadContext *tc); 2227528Ssteve.reinhardt@amd.com 2237528Ssteve.reinhardt@amd.com void clearArchRegs() 2247528Ssteve.reinhardt@amd.com { 2257528Ssteve.reinhardt@amd.com _pcState = 0; 2267528Ssteve.reinhardt@amd.com memset(intRegs, 0, sizeof(intRegs)); 2277528Ssteve.reinhardt@amd.com memset(floatRegs, 0, sizeof(floatRegs)); 2287528Ssteve.reinhardt@amd.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 2297528Ssteve.reinhardt@amd.com vecRegs[i].zero(); 2303101Sstever@eecs.umich.edu } 2313101Sstever@eecs.umich.edu#ifdef ISA_HAS_CC_REGS 2323101Sstever@eecs.umich.edu memset(ccRegs, 0, sizeof(ccRegs)); 2333101Sstever@eecs.umich.edu#endif 2343101Sstever@eecs.umich.edu isa->clear(); 2353101Sstever@eecs.umich.edu } 2363101Sstever@eecs.umich.edu 2373101Sstever@eecs.umich.edu // 2383101Sstever@eecs.umich.edu // New accessors for new decoder. 2394762Snate@binkert.org // 2404762Snate@binkert.org RegVal 2414762Snate@binkert.org readIntReg(int reg_idx) 2424762Snate@binkert.org { 2437528Ssteve.reinhardt@amd.com int flatIndex = isa->flattenIntIndex(reg_idx); 2444762Snate@binkert.org assert(flatIndex < TheISA::NumIntRegs); 2454762Snate@binkert.org uint64_t regVal(readIntRegFlat(flatIndex)); 2464762Snate@binkert.org DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2478596Ssteve.reinhardt@amd.com reg_idx, flatIndex, regVal); 2488596Ssteve.reinhardt@amd.com return regVal; 2498596Ssteve.reinhardt@amd.com } 2507673Snate@binkert.org 2518596Ssteve.reinhardt@amd.com RegVal 2524762Snate@binkert.org readFloatRegBits(int reg_idx) 2537673Snate@binkert.org { 2548596Ssteve.reinhardt@amd.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2557675Snate@binkert.org assert(flatIndex < TheISA::NumFloatRegs); 2567675Snate@binkert.org RegVal regVal(readFloatRegBitsFlat(flatIndex)); 2577675Snate@binkert.org DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 2587675Snate@binkert.org reg_idx, flatIndex, regVal); 2597675Snate@binkert.org return regVal; 2607675Snate@binkert.org } 2617673Snate@binkert.org 2627675Snate@binkert.org const VecRegContainer& 2637675Snate@binkert.org readVecReg(const RegId& reg) const 2647675Snate@binkert.org { 2657675Snate@binkert.org int flatIndex = isa->flattenVecIndex(reg.index()); 2667675Snate@binkert.org assert(flatIndex < TheISA::NumVecRegs); 2677673Snate@binkert.org const VecRegContainer& regVal = readVecRegFlat(flatIndex); 2687675Snate@binkert.org DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 2697675Snate@binkert.org reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 2707675Snate@binkert.org return regVal; 2717675Snate@binkert.org } 2727675Snate@binkert.org 2737675Snate@binkert.org VecRegContainer& 2747675Snate@binkert.org getWritableVecReg(const RegId& reg) 2757675Snate@binkert.org { 2767675Snate@binkert.org int flatIndex = isa->flattenVecIndex(reg.index()); 2777675Snate@binkert.org assert(flatIndex < TheISA::NumVecRegs); 2787675Snate@binkert.org VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 2797675Snate@binkert.org DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 2807675Snate@binkert.org reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 2817675Snate@binkert.org return regVal; 2827675Snate@binkert.org } 2837675Snate@binkert.org 2847673Snate@binkert.org /** Vector Register Lane Interfaces. */ 2857673Snate@binkert.org /** @{ */ 2863101Sstever@eecs.umich.edu /** Reads source vector <T> operand. */ 2877675Snate@binkert.org template <typename T> 2887675Snate@binkert.org VecLaneT<T, true> 2897673Snate@binkert.org readVecLane(const RegId& reg) const 2907673Snate@binkert.org { 2917673Snate@binkert.org int flatIndex = isa->flattenVecIndex(reg.index()); 2923101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumVecRegs); 2937673Snate@binkert.org auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 2947673Snate@binkert.org DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 2953101Sstever@eecs.umich.edu reg.index(), flatIndex, reg.elemIndex(), regVal); 2963101Sstever@eecs.umich.edu return regVal; 2973101Sstever@eecs.umich.edu } 2983101Sstever@eecs.umich.edu 2993101Sstever@eecs.umich.edu /** Reads source vector 8bit operand. */ 3003101Sstever@eecs.umich.edu virtual ConstVecLane8 3013101Sstever@eecs.umich.edu readVec8BitLaneReg(const RegId& reg) const 3023101Sstever@eecs.umich.edu { return readVecLane<uint8_t>(reg); } 3033101Sstever@eecs.umich.edu 3043101Sstever@eecs.umich.edu /** Reads source vector 16bit operand. */ 3053101Sstever@eecs.umich.edu virtual ConstVecLane16 3063101Sstever@eecs.umich.edu readVec16BitLaneReg(const RegId& reg) const 3073101Sstever@eecs.umich.edu { return readVecLane<uint16_t>(reg); } 3083101Sstever@eecs.umich.edu 3093101Sstever@eecs.umich.edu /** Reads source vector 32bit operand. */ 3105033Smilesck@eecs.umich.edu virtual ConstVecLane32 3115033Smilesck@eecs.umich.edu readVec32BitLaneReg(const RegId& reg) const 3123101Sstever@eecs.umich.edu { return readVecLane<uint32_t>(reg); } 3133101Sstever@eecs.umich.edu 3143101Sstever@eecs.umich.edu /** Reads source vector 64bit operand. */ 3153101Sstever@eecs.umich.edu virtual ConstVecLane64 3163101Sstever@eecs.umich.edu readVec64BitLaneReg(const RegId& reg) const 3173101Sstever@eecs.umich.edu { return readVecLane<uint64_t>(reg); } 3183101Sstever@eecs.umich.edu 3193101Sstever@eecs.umich.edu /** Write a lane of the destination vector register. */ 3203101Sstever@eecs.umich.edu template <typename LD> 3213101Sstever@eecs.umich.edu void setVecLaneT(const RegId& reg, const LD& val) 3223101Sstever@eecs.umich.edu { 3233101Sstever@eecs.umich.edu int flatIndex = isa->flattenVecIndex(reg.index()); 3243101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumVecRegs); 3253101Sstever@eecs.umich.edu setVecLaneFlat(flatIndex, reg.elemIndex(), val); 3263101Sstever@eecs.umich.edu DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 3273101Sstever@eecs.umich.edu reg.index(), flatIndex, reg.elemIndex(), val); 3283101Sstever@eecs.umich.edu } 3293101Sstever@eecs.umich.edu virtual void setVecLane(const RegId& reg, 3303101Sstever@eecs.umich.edu const LaneData<LaneSize::Byte>& val) 3313101Sstever@eecs.umich.edu { return setVecLaneT(reg, val); } 3323101Sstever@eecs.umich.edu virtual void setVecLane(const RegId& reg, 3333101Sstever@eecs.umich.edu const LaneData<LaneSize::TwoByte>& val) 3343101Sstever@eecs.umich.edu { return setVecLaneT(reg, val); } 3353101Sstever@eecs.umich.edu virtual void setVecLane(const RegId& reg, 3363101Sstever@eecs.umich.edu const LaneData<LaneSize::FourByte>& val) 3377673Snate@binkert.org { return setVecLaneT(reg, val); } 3387673Snate@binkert.org virtual void setVecLane(const RegId& reg, 3397673Snate@binkert.org const LaneData<LaneSize::EightByte>& val) 3407673Snate@binkert.org { return setVecLaneT(reg, val); } 3417673Snate@binkert.org /** @} */ 3427673Snate@binkert.org 3437673Snate@binkert.org const VecElem& readVecElem(const RegId& reg) const 3447673Snate@binkert.org { 3454762Snate@binkert.org int flatIndex = isa->flattenVecElemIndex(reg.index()); 3464762Snate@binkert.org assert(flatIndex < TheISA::NumVecRegs); 3474762Snate@binkert.org const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 3483101Sstever@eecs.umich.edu DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 3493101Sstever@eecs.umich.edu " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 3503101Sstever@eecs.umich.edu return regVal; 3513101Sstever@eecs.umich.edu } 3523101Sstever@eecs.umich.edu 3533101Sstever@eecs.umich.edu 3543101Sstever@eecs.umich.edu CCReg readCCReg(int reg_idx) 3553101Sstever@eecs.umich.edu { 3563101Sstever@eecs.umich.edu#ifdef ISA_HAS_CC_REGS 3573101Sstever@eecs.umich.edu int flatIndex = isa->flattenCCIndex(reg_idx); 3583101Sstever@eecs.umich.edu assert(0 <= flatIndex); 3593714Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumCCRegs); 3603714Sstever@eecs.umich.edu uint64_t regVal(readCCRegFlat(flatIndex)); 3613714Sstever@eecs.umich.edu DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 3623714Sstever@eecs.umich.edu reg_idx, flatIndex, regVal); 3633714Sstever@eecs.umich.edu return regVal; 3643714Sstever@eecs.umich.edu#else 3653101Sstever@eecs.umich.edu panic("Tried to read a CC register."); 3663101Sstever@eecs.umich.edu return 0; 3673101Sstever@eecs.umich.edu#endif 3683101Sstever@eecs.umich.edu } 3693101Sstever@eecs.umich.edu 3703101Sstever@eecs.umich.edu void 3713101Sstever@eecs.umich.edu setIntReg(int reg_idx, RegVal val) 3723101Sstever@eecs.umich.edu { 3733101Sstever@eecs.umich.edu int flatIndex = isa->flattenIntIndex(reg_idx); 3743101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 3753101Sstever@eecs.umich.edu DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 3763101Sstever@eecs.umich.edu reg_idx, flatIndex, val); 3773101Sstever@eecs.umich.edu setIntRegFlat(flatIndex, val); 3783101Sstever@eecs.umich.edu } 3793101Sstever@eecs.umich.edu 3803101Sstever@eecs.umich.edu void 3813101Sstever@eecs.umich.edu setFloatRegBits(int reg_idx, RegVal val) 3823101Sstever@eecs.umich.edu { 3833101Sstever@eecs.umich.edu int flatIndex = isa->flattenFloatIndex(reg_idx); 3843101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3853101Sstever@eecs.umich.edu // XXX: Fix array out of bounds compiler error for gem5.fast 3863101Sstever@eecs.umich.edu // when checkercpu enabled 3873101Sstever@eecs.umich.edu if (flatIndex < TheISA::NumFloatRegs) 3883101Sstever@eecs.umich.edu setFloatRegBitsFlat(flatIndex, val); 3893101Sstever@eecs.umich.edu DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 3905033Smilesck@eecs.umich.edu reg_idx, flatIndex, val); 3913101Sstever@eecs.umich.edu } 3923101Sstever@eecs.umich.edu 3933101Sstever@eecs.umich.edu void 3943101Sstever@eecs.umich.edu setVecReg(const RegId& reg, const VecRegContainer& val) 3953101Sstever@eecs.umich.edu { 3963101Sstever@eecs.umich.edu int flatIndex = isa->flattenVecIndex(reg.index()); 3973101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumVecRegs); 3983101Sstever@eecs.umich.edu setVecRegFlat(flatIndex, val); 3993101Sstever@eecs.umich.edu DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 4003101Sstever@eecs.umich.edu reg.index(), flatIndex, val.print()); 4013101Sstever@eecs.umich.edu } 4023101Sstever@eecs.umich.edu 4035822Ssaidi@eecs.umich.edu void 4045822Ssaidi@eecs.umich.edu setVecElem(const RegId& reg, const VecElem& val) 4053101Sstever@eecs.umich.edu { 4063101Sstever@eecs.umich.edu int flatIndex = isa->flattenVecElemIndex(reg.index()); 4073101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumVecRegs); 4083101Sstever@eecs.umich.edu setVecElemFlat(flatIndex, reg.elemIndex(), val); 4093101Sstever@eecs.umich.edu DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 4103101Sstever@eecs.umich.edu " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 4113101Sstever@eecs.umich.edu } 4123101Sstever@eecs.umich.edu 4133101Sstever@eecs.umich.edu void 4143101Sstever@eecs.umich.edu setCCReg(int reg_idx, CCReg val) 4153101Sstever@eecs.umich.edu { 4163101Sstever@eecs.umich.edu#ifdef ISA_HAS_CC_REGS 4173101Sstever@eecs.umich.edu int flatIndex = isa->flattenCCIndex(reg_idx); 4183101Sstever@eecs.umich.edu assert(flatIndex < TheISA::NumCCRegs); 4193101Sstever@eecs.umich.edu DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 4203101Sstever@eecs.umich.edu reg_idx, flatIndex, val); 4213101Sstever@eecs.umich.edu setCCRegFlat(flatIndex, val); 4223101Sstever@eecs.umich.edu#else 4233101Sstever@eecs.umich.edu panic("Tried to set a CC register."); 4243101Sstever@eecs.umich.edu#endif 4253101Sstever@eecs.umich.edu } 4263102Sstever@eecs.umich.edu 4273714Sstever@eecs.umich.edu TheISA::PCState 4283101Sstever@eecs.umich.edu pcState() 4293714Sstever@eecs.umich.edu { 4303714Sstever@eecs.umich.edu return _pcState; 4313714Sstever@eecs.umich.edu } 4323101Sstever@eecs.umich.edu 4333101Sstever@eecs.umich.edu void 4347673Snate@binkert.org pcState(const TheISA::PCState &val) 4357673Snate@binkert.org { 4367673Snate@binkert.org _pcState = val; 4377673Snate@binkert.org } 4387673Snate@binkert.org 4397673Snate@binkert.org void 4407673Snate@binkert.org pcStateNoRecord(const TheISA::PCState &val) 4417673Snate@binkert.org { 4427673Snate@binkert.org _pcState = val; 4437673Snate@binkert.org } 4447673Snate@binkert.org 4454762Snate@binkert.org Addr 4464762Snate@binkert.org instAddr() 4474762Snate@binkert.org { 4483101Sstever@eecs.umich.edu return _pcState.instAddr(); 4493101Sstever@eecs.umich.edu } 4503101Sstever@eecs.umich.edu 4513101Sstever@eecs.umich.edu Addr 4523101Sstever@eecs.umich.edu nextInstAddr() 4533101Sstever@eecs.umich.edu { 4543101Sstever@eecs.umich.edu return _pcState.nextInstAddr(); 4553101Sstever@eecs.umich.edu } 4563101Sstever@eecs.umich.edu 4573101Sstever@eecs.umich.edu void 4583101Sstever@eecs.umich.edu setNPC(Addr val) 4593101Sstever@eecs.umich.edu { 4603101Sstever@eecs.umich.edu _pcState.setNPC(val); 4613101Sstever@eecs.umich.edu } 4623101Sstever@eecs.umich.edu 4633101Sstever@eecs.umich.edu MicroPC 4643101Sstever@eecs.umich.edu microPC() 4653101Sstever@eecs.umich.edu { 4663101Sstever@eecs.umich.edu return _pcState.microPC(); 4673101Sstever@eecs.umich.edu } 4684446Sbinkertn@umich.edu 4693101Sstever@eecs.umich.edu bool readPredicate() 4705468Snate@binkert.org { 4715468Snate@binkert.org return predicate; 4725468Snate@binkert.org } 4735468Snate@binkert.org 4745468Snate@binkert.org void setPredicate(bool val) 4755468Snate@binkert.org { 4765468Snate@binkert.org predicate = val; 4774762Snate@binkert.org } 4784762Snate@binkert.org 4794762Snate@binkert.org RegVal 4803101Sstever@eecs.umich.edu readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const 4813101Sstever@eecs.umich.edu { 4823101Sstever@eecs.umich.edu return isa->readMiscRegNoEffect(misc_reg); 4833101Sstever@eecs.umich.edu } 4843101Sstever@eecs.umich.edu 4853101Sstever@eecs.umich.edu RegVal 4863101Sstever@eecs.umich.edu readMiscReg(int misc_reg, ThreadID tid=0) 4873101Sstever@eecs.umich.edu { 4883102Sstever@eecs.umich.edu return isa->readMiscReg(misc_reg, tc); 4893101Sstever@eecs.umich.edu } 4903101Sstever@eecs.umich.edu 4913101Sstever@eecs.umich.edu void 4924168Sbinkertn@umich.edu setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0) 4933101Sstever@eecs.umich.edu { 4943101Sstever@eecs.umich.edu return isa->setMiscRegNoEffect(misc_reg, val); 4953101Sstever@eecs.umich.edu } 4963101Sstever@eecs.umich.edu 4973101Sstever@eecs.umich.edu void 4983101Sstever@eecs.umich.edu setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0) 4993102Sstever@eecs.umich.edu { 5003101Sstever@eecs.umich.edu return isa->setMiscReg(misc_reg, val, tc); 5013101Sstever@eecs.umich.edu } 5023101Sstever@eecs.umich.edu 5033101Sstever@eecs.umich.edu RegId 5043101Sstever@eecs.umich.edu flattenRegId(const RegId& regId) const 5053101Sstever@eecs.umich.edu { 5063101Sstever@eecs.umich.edu return isa->flattenRegId(regId); 5073101Sstever@eecs.umich.edu } 5083101Sstever@eecs.umich.edu 5093101Sstever@eecs.umich.edu unsigned readStCondFailures() { return storeCondFailures; } 5103101Sstever@eecs.umich.edu 5113102Sstever@eecs.umich.edu void setStCondFailures(unsigned sc_failures) 5123101Sstever@eecs.umich.edu { storeCondFailures = sc_failures; } 5133101Sstever@eecs.umich.edu 5143101Sstever@eecs.umich.edu void 5153584Ssaidi@eecs.umich.edu syscall(int64_t callnum, Fault *fault) 5163584Ssaidi@eecs.umich.edu { 5173584Ssaidi@eecs.umich.edu process->syscall(callnum, tc, fault); 5183584Ssaidi@eecs.umich.edu } 5193584Ssaidi@eecs.umich.edu 5203101Sstever@eecs.umich.edu RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 5213101Sstever@eecs.umich.edu void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } 5225033Smilesck@eecs.umich.edu 5233101Sstever@eecs.umich.edu RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 5243101Sstever@eecs.umich.edu void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } 5253101Sstever@eecs.umich.edu 5263101Sstever@eecs.umich.edu const VecRegContainer & 5273101Sstever@eecs.umich.edu readVecRegFlat(const RegIndex& reg) const 5283101Sstever@eecs.umich.edu { 5293101Sstever@eecs.umich.edu return vecRegs[reg]; 5303101Sstever@eecs.umich.edu } 5313101Sstever@eecs.umich.edu 5323101Sstever@eecs.umich.edu VecRegContainer & 5333101Sstever@eecs.umich.edu getWritableVecRegFlat(const RegIndex& reg) 5343101Sstever@eecs.umich.edu { 5353101Sstever@eecs.umich.edu return vecRegs[reg]; 5363101Sstever@eecs.umich.edu } 5373101Sstever@eecs.umich.edu 5383101Sstever@eecs.umich.edu void 5393101Sstever@eecs.umich.edu setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 5403101Sstever@eecs.umich.edu { 5413101Sstever@eecs.umich.edu vecRegs[reg] = val; 5423101Sstever@eecs.umich.edu } 5433101Sstever@eecs.umich.edu 5443101Sstever@eecs.umich.edu template <typename T> 5453101Sstever@eecs.umich.edu VecLaneT<T, true> 5463101Sstever@eecs.umich.edu readVecLaneFlat(const RegIndex& reg, int lId) const 5473101Sstever@eecs.umich.edu { 5483101Sstever@eecs.umich.edu return vecRegs[reg].laneView<T>(lId); 5493101Sstever@eecs.umich.edu } 5503101Sstever@eecs.umich.edu 5513101Sstever@eecs.umich.edu template <typename LD> 5525219Ssaidi@eecs.umich.edu void 5535219Ssaidi@eecs.umich.edu setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 5545219Ssaidi@eecs.umich.edu { 5553101Sstever@eecs.umich.edu vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 5563101Sstever@eecs.umich.edu } 5573101Sstever@eecs.umich.edu 5583101Sstever@eecs.umich.edu const VecElem & 5593101Sstever@eecs.umich.edu readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const 5603101Sstever@eecs.umich.edu { 5613101Sstever@eecs.umich.edu return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 5623101Sstever@eecs.umich.edu } 5633101Sstever@eecs.umich.edu 5643101Sstever@eecs.umich.edu void 5653101Sstever@eecs.umich.edu setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 5663101Sstever@eecs.umich.edu const VecElem val) 5673101Sstever@eecs.umich.edu { 5683101Sstever@eecs.umich.edu vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 5693101Sstever@eecs.umich.edu } 5703101Sstever@eecs.umich.edu 5717673Snate@binkert.org#ifdef ISA_HAS_CC_REGS 5727673Snate@binkert.org CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 5737675Snate@binkert.org void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 5747673Snate@binkert.org#else 5757675Snate@binkert.org CCReg readCCRegFlat(int idx) 5767675Snate@binkert.org { panic("readCCRegFlat w/no CC regs!\n"); } 5777675Snate@binkert.org 5787675Snate@binkert.org void setCCRegFlat(int idx, CCReg val) 5797675Snate@binkert.org { panic("setCCRegFlat w/no CC regs!\n"); } 5807673Snate@binkert.org#endif 5813101Sstever@eecs.umich.edu}; 5823101Sstever@eecs.umich.edu 5837673Snate@binkert.org 5844762Snate@binkert.org#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 5857675Snate@binkert.org