simple_thread.hh revision 12106:7784fac1b159 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2001-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 *          Nathan Binkert
43 */
44
45#ifndef __CPU_SIMPLE_THREAD_HH__
46#define __CPU_SIMPLE_THREAD_HH__
47
48#include "arch/decoder.hh"
49#include "arch/isa.hh"
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "arch/tlb.hh"
53#include "arch/types.hh"
54#include "base/types.hh"
55#include "config/the_isa.hh"
56#include "cpu/thread_context.hh"
57#include "cpu/thread_state.hh"
58#include "debug/CCRegs.hh"
59#include "debug/FloatRegs.hh"
60#include "debug/IntRegs.hh"
61#include "mem/page_table.hh"
62#include "mem/request.hh"
63#include "sim/byteswap.hh"
64#include "sim/eventq.hh"
65#include "sim/process.hh"
66#include "sim/serialize.hh"
67#include "sim/system.hh"
68
69class BaseCPU;
70class CheckerCPU;
71
72class FunctionProfile;
73class ProfileNode;
74
75namespace TheISA {
76    namespace Kernel {
77        class Statistics;
78    }
79}
80
81/**
82 * The SimpleThread object provides a combination of the ThreadState
83 * object and the ThreadContext interface. It implements the
84 * ThreadContext interface so that a ProxyThreadContext class can be
85 * made using SimpleThread as the template parameter (see
86 * thread_context.hh). It adds to the ThreadState object by adding all
87 * the objects needed for simple functional execution, including a
88 * simple architectural register file, and pointers to the ITB and DTB
89 * in full system mode. For CPU models that do not need more advanced
90 * ways to hold state (i.e. a separate physical register file, or
91 * separate fetch and commit PC's), this SimpleThread class provides
92 * all the necessary state for full architecture-level functional
93 * simulation.  See the AtomicSimpleCPU or TimingSimpleCPU for
94 * examples.
95 */
96
97class SimpleThread : public ThreadState
98{
99  protected:
100    typedef TheISA::MachInst MachInst;
101    typedef TheISA::MiscReg MiscReg;
102    typedef TheISA::FloatReg FloatReg;
103    typedef TheISA::FloatRegBits FloatRegBits;
104    typedef TheISA::CCReg CCReg;
105  public:
106    typedef ThreadContext::Status Status;
107
108  protected:
109    union {
110        FloatReg f[TheISA::NumFloatRegs];
111        FloatRegBits i[TheISA::NumFloatRegs];
112    } floatRegs;
113    TheISA::IntReg intRegs[TheISA::NumIntRegs];
114#ifdef ISA_HAS_CC_REGS
115    TheISA::CCReg ccRegs[TheISA::NumCCRegs];
116#endif
117    TheISA::ISA *const isa;    // one "instance" of the current ISA.
118
119    TheISA::PCState _pcState;
120
121    /** Did this instruction execute or is it predicated false */
122    bool predicate;
123
124  public:
125    std::string name() const
126    {
127        return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId());
128    }
129
130    ProxyThreadContext<SimpleThread> *tc;
131
132    System *system;
133
134    TheISA::TLB *itb;
135    TheISA::TLB *dtb;
136
137    TheISA::Decoder decoder;
138
139    // constructor: initialize SimpleThread from given process structure
140    // FS
141    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
142                 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
143                 bool use_kernel_stats = true);
144    // SE
145    SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
146                 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
147                 TheISA::ISA *_isa);
148
149    virtual ~SimpleThread();
150
151    virtual void takeOverFrom(ThreadContext *oldContext);
152
153    void regStats(const std::string &name);
154
155    void copyState(ThreadContext *oldContext);
156
157    void serialize(CheckpointOut &cp) const override;
158    void unserialize(CheckpointIn &cp) override;
159    void startup();
160
161    /***************************************************************
162     *  SimpleThread functions to provide CPU with access to various
163     *  state.
164     **************************************************************/
165
166    /** Returns the pointer to this SimpleThread's ThreadContext. Used
167     *  when a ThreadContext must be passed to objects outside of the
168     *  CPU.
169     */
170    ThreadContext *getTC() { return tc; }
171
172    void demapPage(Addr vaddr, uint64_t asn)
173    {
174        itb->demapPage(vaddr, asn);
175        dtb->demapPage(vaddr, asn);
176    }
177
178    void demapInstPage(Addr vaddr, uint64_t asn)
179    {
180        itb->demapPage(vaddr, asn);
181    }
182
183    void demapDataPage(Addr vaddr, uint64_t asn)
184    {
185        dtb->demapPage(vaddr, asn);
186    }
187
188    void dumpFuncProfile();
189
190    Fault hwrei();
191
192    bool simPalCheck(int palFunc);
193
194    /*******************************************
195     * ThreadContext interface functions.
196     ******************************************/
197
198    BaseCPU *getCpuPtr() { return baseCpu; }
199
200    TheISA::TLB *getITBPtr() { return itb; }
201
202    TheISA::TLB *getDTBPtr() { return dtb; }
203
204    CheckerCPU *getCheckerCpuPtr() { return NULL; }
205
206    TheISA::Decoder *getDecoderPtr() { return &decoder; }
207
208    System *getSystemPtr() { return system; }
209
210    Status status() const { return _status; }
211
212    void setStatus(Status newStatus) { _status = newStatus; }
213
214    /// Set the status to Active.
215    void activate();
216
217    /// Set the status to Suspended.
218    void suspend();
219
220    /// Set the status to Halted.
221    void halt();
222
223    void copyArchRegs(ThreadContext *tc);
224
225    void clearArchRegs()
226    {
227        _pcState = 0;
228        memset(intRegs, 0, sizeof(intRegs));
229        memset(floatRegs.i, 0, sizeof(floatRegs.i));
230#ifdef ISA_HAS_CC_REGS
231        memset(ccRegs, 0, sizeof(ccRegs));
232#endif
233        isa->clear();
234    }
235
236    //
237    // New accessors for new decoder.
238    //
239    uint64_t readIntReg(int reg_idx)
240    {
241        int flatIndex = isa->flattenIntIndex(reg_idx);
242        assert(flatIndex < TheISA::NumIntRegs);
243        uint64_t regVal(readIntRegFlat(flatIndex));
244        DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
245                reg_idx, flatIndex, regVal);
246        return regVal;
247    }
248
249    FloatReg readFloatReg(int reg_idx)
250    {
251        int flatIndex = isa->flattenFloatIndex(reg_idx);
252        assert(flatIndex < TheISA::NumFloatRegs);
253        FloatReg regVal(readFloatRegFlat(flatIndex));
254        DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
255                reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
256        return regVal;
257    }
258
259    FloatRegBits readFloatRegBits(int reg_idx)
260    {
261        int flatIndex = isa->flattenFloatIndex(reg_idx);
262        assert(flatIndex < TheISA::NumFloatRegs);
263        FloatRegBits regVal(readFloatRegBitsFlat(flatIndex));
264        DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
265                reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]);
266        return regVal;
267    }
268
269    CCReg readCCReg(int reg_idx)
270    {
271#ifdef ISA_HAS_CC_REGS
272        int flatIndex = isa->flattenCCIndex(reg_idx);
273        assert(0 <= flatIndex);
274        assert(flatIndex < TheISA::NumCCRegs);
275        uint64_t regVal(readCCRegFlat(flatIndex));
276        DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n",
277                reg_idx, flatIndex, regVal);
278        return regVal;
279#else
280        panic("Tried to read a CC register.");
281        return 0;
282#endif
283    }
284
285    void setIntReg(int reg_idx, uint64_t val)
286    {
287        int flatIndex = isa->flattenIntIndex(reg_idx);
288        assert(flatIndex < TheISA::NumIntRegs);
289        DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
290                reg_idx, flatIndex, val);
291        setIntRegFlat(flatIndex, val);
292    }
293
294    void setFloatReg(int reg_idx, FloatReg val)
295    {
296        int flatIndex = isa->flattenFloatIndex(reg_idx);
297        assert(flatIndex < TheISA::NumFloatRegs);
298        setFloatRegFlat(flatIndex, val);
299        DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
300                reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
301    }
302
303    void setFloatRegBits(int reg_idx, FloatRegBits val)
304    {
305        int flatIndex = isa->flattenFloatIndex(reg_idx);
306        assert(flatIndex < TheISA::NumFloatRegs);
307        // XXX: Fix array out of bounds compiler error for gem5.fast
308        // when checkercpu enabled
309        if (flatIndex < TheISA::NumFloatRegs)
310            setFloatRegBitsFlat(flatIndex, val);
311        DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n",
312                reg_idx, flatIndex, val, floatRegs.f[flatIndex]);
313    }
314
315    void setCCReg(int reg_idx, CCReg val)
316    {
317#ifdef ISA_HAS_CC_REGS
318        int flatIndex = isa->flattenCCIndex(reg_idx);
319        assert(flatIndex < TheISA::NumCCRegs);
320        DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n",
321                reg_idx, flatIndex, val);
322        setCCRegFlat(flatIndex, val);
323#else
324        panic("Tried to set a CC register.");
325#endif
326    }
327
328    TheISA::PCState
329    pcState()
330    {
331        return _pcState;
332    }
333
334    void
335    pcState(const TheISA::PCState &val)
336    {
337        _pcState = val;
338    }
339
340    void
341    pcStateNoRecord(const TheISA::PCState &val)
342    {
343        _pcState = val;
344    }
345
346    Addr
347    instAddr()
348    {
349        return _pcState.instAddr();
350    }
351
352    Addr
353    nextInstAddr()
354    {
355        return _pcState.nextInstAddr();
356    }
357
358    void
359    setNPC(Addr val)
360    {
361        _pcState.setNPC(val);
362    }
363
364    MicroPC
365    microPC()
366    {
367        return _pcState.microPC();
368    }
369
370    bool readPredicate()
371    {
372        return predicate;
373    }
374
375    void setPredicate(bool val)
376    {
377        predicate = val;
378    }
379
380    MiscReg
381    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
382    {
383        return isa->readMiscRegNoEffect(misc_reg);
384    }
385
386    MiscReg
387    readMiscReg(int misc_reg, ThreadID tid = 0)
388    {
389        return isa->readMiscReg(misc_reg, tc);
390    }
391
392    void
393    setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
394    {
395        return isa->setMiscRegNoEffect(misc_reg, val);
396    }
397
398    void
399    setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
400    {
401        return isa->setMiscReg(misc_reg, val, tc);
402    }
403
404    RegId
405    flattenRegId(const RegId& regId) const
406    {
407        return isa->flattenRegId(regId);
408    }
409
410    unsigned readStCondFailures() { return storeCondFailures; }
411
412    void setStCondFailures(unsigned sc_failures)
413    { storeCondFailures = sc_failures; }
414
415    void syscall(int64_t callnum, Fault *fault)
416    {
417        process->syscall(callnum, tc, fault);
418    }
419
420    uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
421    void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
422
423    FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
424    void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
425
426    FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
427    void setFloatRegBitsFlat(int idx, FloatRegBits val) {
428        floatRegs.i[idx] = val;
429    }
430
431#ifdef ISA_HAS_CC_REGS
432    CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
433    void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
434#else
435    CCReg readCCRegFlat(int idx)
436    { panic("readCCRegFlat w/no CC regs!\n"); }
437
438    void setCCRegFlat(int idx, CCReg val)
439    { panic("setCCRegFlat w/no CC regs!\n"); }
440#endif
441};
442
443
444#endif // __CPU_CPU_EXEC_CONTEXT_HH__
445