simple_thread.hh revision 10664:61a0b02aa800
111723Sar4jc@virginia.edu/* 211963Sar4jc@virginia.edu * Copyright (c) 2011-2012 ARM Limited 311963Sar4jc@virginia.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 411963Sar4jc@virginia.edu * All rights reserved 511963Sar4jc@virginia.edu * 611963Sar4jc@virginia.edu * The license below extends only to copyright in the software and shall 711963Sar4jc@virginia.edu * not be construed as granting a license to any other intellectual 811963Sar4jc@virginia.edu * property including but not limited to intellectual property relating 911963Sar4jc@virginia.edu * to a hardware implementation of the functionality of the software 1011963Sar4jc@virginia.edu * licensed hereunder. You may use the software subject to the license 1111963Sar4jc@virginia.edu * terms below provided that you ensure that this notice is replicated 1211963Sar4jc@virginia.edu * unmodified and in its entirety in all distributions of the software, 1311963Sar4jc@virginia.edu * modified or unmodified, in source code or in binary form. 1411963Sar4jc@virginia.edu * 1511963Sar4jc@virginia.edu * Copyright (c) 2001-2006 The Regents of The University of Michigan 1611963Sar4jc@virginia.edu * All rights reserved. 1711723Sar4jc@virginia.edu * 1811723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 1911723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 2011723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 2111723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 2211723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 2311723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 2411723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 2511723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 2611723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 2711723Sar4jc@virginia.edu * this software without specific prior written permission. 2811723Sar4jc@virginia.edu * 2911723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3011723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3111723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3211723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3511723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3611723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3711723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3811723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3911723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4011723Sar4jc@virginia.edu * 4111723Sar4jc@virginia.edu * Authors: Steve Reinhardt 4211723Sar4jc@virginia.edu * Nathan Binkert 4311723Sar4jc@virginia.edu */ 4411963Sar4jc@virginia.edu 4511963Sar4jc@virginia.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 4611963Sar4jc@virginia.edu#define __CPU_SIMPLE_THREAD_HH__ 4711963Sar4jc@virginia.edu 4811723Sar4jc@virginia.edu#include "arch/decoder.hh" 4911723Sar4jc@virginia.edu#include "arch/isa.hh" 5011963Sar4jc@virginia.edu#include "arch/isa_traits.hh" 5111963Sar4jc@virginia.edu#include "arch/registers.hh" 5211963Sar4jc@virginia.edu#include "arch/tlb.hh" 5311963Sar4jc@virginia.edu#include "arch/types.hh" 5411963Sar4jc@virginia.edu#include "base/types.hh" 5511963Sar4jc@virginia.edu#include "config/the_isa.hh" 5611963Sar4jc@virginia.edu#include "cpu/thread_context.hh" 5711963Sar4jc@virginia.edu#include "cpu/thread_state.hh" 5811963Sar4jc@virginia.edu#include "debug/CCRegs.hh" 5911963Sar4jc@virginia.edu#include "debug/FloatRegs.hh" 6011963Sar4jc@virginia.edu#include "debug/IntRegs.hh" 6111963Sar4jc@virginia.edu#include "mem/page_table.hh" 6211963Sar4jc@virginia.edu#include "mem/request.hh" 6311963Sar4jc@virginia.edu#include "sim/byteswap.hh" 6411963Sar4jc@virginia.edu#include "sim/eventq.hh" 6511963Sar4jc@virginia.edu#include "sim/process.hh" 6611963Sar4jc@virginia.edu#include "sim/serialize.hh" 6711963Sar4jc@virginia.edu#include "sim/system.hh" 6811963Sar4jc@virginia.edu 6911963Sar4jc@virginia.educlass BaseCPU; 7011963Sar4jc@virginia.educlass CheckerCPU; 7111963Sar4jc@virginia.edu 7211963Sar4jc@virginia.educlass FunctionProfile; 7311963Sar4jc@virginia.educlass ProfileNode; 7411963Sar4jc@virginia.edu 7511963Sar4jc@virginia.edunamespace TheISA { 7611963Sar4jc@virginia.edu namespace Kernel { 7711963Sar4jc@virginia.edu class Statistics; 7811963Sar4jc@virginia.edu } 7911963Sar4jc@virginia.edu} 8011963Sar4jc@virginia.edu 8111963Sar4jc@virginia.edu/** 8211963Sar4jc@virginia.edu * The SimpleThread object provides a combination of the ThreadState 8311963Sar4jc@virginia.edu * object and the ThreadContext interface. It implements the 8411963Sar4jc@virginia.edu * ThreadContext interface so that a ProxyThreadContext class can be 8511963Sar4jc@virginia.edu * made using SimpleThread as the template parameter (see 8611963Sar4jc@virginia.edu * thread_context.hh). It adds to the ThreadState object by adding all 8711963Sar4jc@virginia.edu * the objects needed for simple functional execution, including a 8811963Sar4jc@virginia.edu * simple architectural register file, and pointers to the ITB and DTB 8911963Sar4jc@virginia.edu * in full system mode. For CPU models that do not need more advanced 9011963Sar4jc@virginia.edu * ways to hold state (i.e. a separate physical register file, or 9111963Sar4jc@virginia.edu * separate fetch and commit PC's), this SimpleThread class provides 9211963Sar4jc@virginia.edu * all the necessary state for full architecture-level functional 9311963Sar4jc@virginia.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 9411963Sar4jc@virginia.edu * examples. 9511963Sar4jc@virginia.edu */ 9611963Sar4jc@virginia.edu 9711963Sar4jc@virginia.educlass SimpleThread : public ThreadState 9811963Sar4jc@virginia.edu{ 9911963Sar4jc@virginia.edu protected: 10011963Sar4jc@virginia.edu typedef TheISA::MachInst MachInst; 10111963Sar4jc@virginia.edu typedef TheISA::MiscReg MiscReg; 10211963Sar4jc@virginia.edu typedef TheISA::FloatReg FloatReg; 10311963Sar4jc@virginia.edu typedef TheISA::FloatRegBits FloatRegBits; 10411963Sar4jc@virginia.edu typedef TheISA::CCReg CCReg; 10511963Sar4jc@virginia.edu public: 10611963Sar4jc@virginia.edu typedef ThreadContext::Status Status; 10711963Sar4jc@virginia.edu 10811963Sar4jc@virginia.edu protected: 10911963Sar4jc@virginia.edu union { 11011963Sar4jc@virginia.edu FloatReg f[TheISA::NumFloatRegs]; 11111963Sar4jc@virginia.edu FloatRegBits i[TheISA::NumFloatRegs]; 11211963Sar4jc@virginia.edu } floatRegs; 11311963Sar4jc@virginia.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 11411963Sar4jc@virginia.edu#ifdef ISA_HAS_CC_REGS 11511963Sar4jc@virginia.edu TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 11611963Sar4jc@virginia.edu#endif 11711963Sar4jc@virginia.edu TheISA::ISA *const isa; // one "instance" of the current ISA. 11811963Sar4jc@virginia.edu 11911963Sar4jc@virginia.edu TheISA::PCState _pcState; 12011963Sar4jc@virginia.edu 12111963Sar4jc@virginia.edu /** Did this instruction execute or is it predicated false */ 12211963Sar4jc@virginia.edu bool predicate; 12311963Sar4jc@virginia.edu 12411963Sar4jc@virginia.edu public: 12511963Sar4jc@virginia.edu std::string name() const 12611963Sar4jc@virginia.edu { 12711963Sar4jc@virginia.edu return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 12811963Sar4jc@virginia.edu } 12911963Sar4jc@virginia.edu 13011963Sar4jc@virginia.edu ProxyThreadContext<SimpleThread> *tc; 13111963Sar4jc@virginia.edu 13211963Sar4jc@virginia.edu System *system; 13311963Sar4jc@virginia.edu 13411963Sar4jc@virginia.edu TheISA::TLB *itb; 13511963Sar4jc@virginia.edu TheISA::TLB *dtb; 13611963Sar4jc@virginia.edu 13711963Sar4jc@virginia.edu TheISA::Decoder decoder; 13811963Sar4jc@virginia.edu 13911963Sar4jc@virginia.edu // constructor: initialize SimpleThread from given process structure 14011963Sar4jc@virginia.edu // FS 14111963Sar4jc@virginia.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14211963Sar4jc@virginia.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 14311963Sar4jc@virginia.edu bool use_kernel_stats = true); 14411963Sar4jc@virginia.edu // SE 14511963Sar4jc@virginia.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14611963Sar4jc@virginia.edu Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 14711723Sar4jc@virginia.edu TheISA::ISA *_isa); 14811723Sar4jc@virginia.edu 14911723Sar4jc@virginia.edu virtual ~SimpleThread(); 15011723Sar4jc@virginia.edu 15111963Sar4jc@virginia.edu virtual void takeOverFrom(ThreadContext *oldContext); 15212031Sgabeblack@google.com 15311723Sar4jc@virginia.edu void regStats(const std::string &name); 15411723Sar4jc@virginia.edu 15511723Sar4jc@virginia.edu void copyState(ThreadContext *oldContext); 15611963Sar4jc@virginia.edu 15711963Sar4jc@virginia.edu void serialize(std::ostream &os); 15811723Sar4jc@virginia.edu void unserialize(Checkpoint *cp, const std::string §ion); 15911963Sar4jc@virginia.edu void startup(); 16011963Sar4jc@virginia.edu 16111963Sar4jc@virginia.edu /*************************************************************** 16211963Sar4jc@virginia.edu * SimpleThread functions to provide CPU with access to various 16311963Sar4jc@virginia.edu * state. 16411723Sar4jc@virginia.edu **************************************************************/ 16511723Sar4jc@virginia.edu 16611723Sar4jc@virginia.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 16711963Sar4jc@virginia.edu * when a ThreadContext must be passed to objects outside of the 16811723Sar4jc@virginia.edu * CPU. 16911963Sar4jc@virginia.edu */ 17011963Sar4jc@virginia.edu ThreadContext *getTC() { return tc; } 17111963Sar4jc@virginia.edu 17211963Sar4jc@virginia.edu void demapPage(Addr vaddr, uint64_t asn) 17311963Sar4jc@virginia.edu { 17411963Sar4jc@virginia.edu itb->demapPage(vaddr, asn); 17511963Sar4jc@virginia.edu dtb->demapPage(vaddr, asn); 17611963Sar4jc@virginia.edu } 17711963Sar4jc@virginia.edu 17811963Sar4jc@virginia.edu void demapInstPage(Addr vaddr, uint64_t asn) 17911963Sar4jc@virginia.edu { 18011963Sar4jc@virginia.edu itb->demapPage(vaddr, asn); 18111963Sar4jc@virginia.edu } 18211723Sar4jc@virginia.edu 18311723Sar4jc@virginia.edu void demapDataPage(Addr vaddr, uint64_t asn) 18411723Sar4jc@virginia.edu { 18511963Sar4jc@virginia.edu dtb->demapPage(vaddr, asn); 18611723Sar4jc@virginia.edu } 18711963Sar4jc@virginia.edu 18811963Sar4jc@virginia.edu void dumpFuncProfile(); 18911963Sar4jc@virginia.edu 19011963Sar4jc@virginia.edu Fault hwrei(); 19111963Sar4jc@virginia.edu 19211963Sar4jc@virginia.edu bool simPalCheck(int palFunc); 19311963Sar4jc@virginia.edu 19411963Sar4jc@virginia.edu /******************************************* 19511963Sar4jc@virginia.edu * ThreadContext interface functions. 19611963Sar4jc@virginia.edu ******************************************/ 19711963Sar4jc@virginia.edu 19811963Sar4jc@virginia.edu BaseCPU *getCpuPtr() { return baseCpu; } 19911963Sar4jc@virginia.edu 20011723Sar4jc@virginia.edu TheISA::TLB *getITBPtr() { return itb; } 20111963Sar4jc@virginia.edu 20211963Sar4jc@virginia.edu TheISA::TLB *getDTBPtr() { return dtb; } 20311963Sar4jc@virginia.edu 20412031Sgabeblack@google.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 20511963Sar4jc@virginia.edu 206 TheISA::Decoder *getDecoderPtr() { return &decoder; } 207 208 System *getSystemPtr() { return system; } 209 210 Status status() const { return _status; } 211 212 void setStatus(Status newStatus) { _status = newStatus; } 213 214 /// Set the status to Active. 215 void activate(); 216 217 /// Set the status to Suspended. 218 void suspend(); 219 220 /// Set the status to Halted. 221 void halt(); 222 223 void copyArchRegs(ThreadContext *tc); 224 225 void clearArchRegs() 226 { 227 _pcState = 0; 228 memset(intRegs, 0, sizeof(intRegs)); 229 memset(floatRegs.i, 0, sizeof(floatRegs.i)); 230#ifdef ISA_HAS_CC_REGS 231 memset(ccRegs, 0, sizeof(ccRegs)); 232#endif 233 isa->clear(); 234 } 235 236 // 237 // New accessors for new decoder. 238 // 239 uint64_t readIntReg(int reg_idx) 240 { 241 int flatIndex = isa->flattenIntIndex(reg_idx); 242 assert(flatIndex < TheISA::NumIntRegs); 243 uint64_t regVal(readIntRegFlat(flatIndex)); 244 DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 245 reg_idx, flatIndex, regVal); 246 return regVal; 247 } 248 249 FloatReg readFloatReg(int reg_idx) 250 { 251 int flatIndex = isa->flattenFloatIndex(reg_idx); 252 assert(flatIndex < TheISA::NumFloatRegs); 253 FloatReg regVal(readFloatRegFlat(flatIndex)); 254 DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 255 reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 256 return regVal; 257 } 258 259 FloatRegBits readFloatRegBits(int reg_idx) 260 { 261 int flatIndex = isa->flattenFloatIndex(reg_idx); 262 assert(flatIndex < TheISA::NumFloatRegs); 263 FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 264 DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 265 reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 266 return regVal; 267 } 268 269 CCReg readCCReg(int reg_idx) 270 { 271#ifdef ISA_HAS_CC_REGS 272 int flatIndex = isa->flattenCCIndex(reg_idx); 273 assert(0 <= flatIndex); 274 assert(flatIndex < TheISA::NumCCRegs); 275 uint64_t regVal(readCCRegFlat(flatIndex)); 276 DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 277 reg_idx, flatIndex, regVal); 278 return regVal; 279#else 280 panic("Tried to read a CC register."); 281 return 0; 282#endif 283 } 284 285 void setIntReg(int reg_idx, uint64_t val) 286 { 287 int flatIndex = isa->flattenIntIndex(reg_idx); 288 assert(flatIndex < TheISA::NumIntRegs); 289 DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 290 reg_idx, flatIndex, val); 291 setIntRegFlat(flatIndex, val); 292 } 293 294 void setFloatReg(int reg_idx, FloatReg val) 295 { 296 int flatIndex = isa->flattenFloatIndex(reg_idx); 297 assert(flatIndex < TheISA::NumFloatRegs); 298 setFloatRegFlat(flatIndex, val); 299 DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 300 reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 301 } 302 303 void setFloatRegBits(int reg_idx, FloatRegBits val) 304 { 305 int flatIndex = isa->flattenFloatIndex(reg_idx); 306 assert(flatIndex < TheISA::NumFloatRegs); 307 // XXX: Fix array out of bounds compiler error for gem5.fast 308 // when checkercpu enabled 309 if (flatIndex < TheISA::NumFloatRegs) 310 setFloatRegBitsFlat(flatIndex, val); 311 DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 312 reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 313 } 314 315 void setCCReg(int reg_idx, CCReg val) 316 { 317#ifdef ISA_HAS_CC_REGS 318 int flatIndex = isa->flattenCCIndex(reg_idx); 319 assert(flatIndex < TheISA::NumCCRegs); 320 DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 321 reg_idx, flatIndex, val); 322 setCCRegFlat(flatIndex, val); 323#else 324 panic("Tried to set a CC register."); 325#endif 326 } 327 328 TheISA::PCState 329 pcState() 330 { 331 return _pcState; 332 } 333 334 void 335 pcState(const TheISA::PCState &val) 336 { 337 _pcState = val; 338 } 339 340 void 341 pcStateNoRecord(const TheISA::PCState &val) 342 { 343 _pcState = val; 344 } 345 346 Addr 347 instAddr() 348 { 349 return _pcState.instAddr(); 350 } 351 352 Addr 353 nextInstAddr() 354 { 355 return _pcState.nextInstAddr(); 356 } 357 358 MicroPC 359 microPC() 360 { 361 return _pcState.microPC(); 362 } 363 364 bool readPredicate() 365 { 366 return predicate; 367 } 368 369 void setPredicate(bool val) 370 { 371 predicate = val; 372 } 373 374 MiscReg 375 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 376 { 377 return isa->readMiscRegNoEffect(misc_reg); 378 } 379 380 MiscReg 381 readMiscReg(int misc_reg, ThreadID tid = 0) 382 { 383 return isa->readMiscReg(misc_reg, tc); 384 } 385 386 void 387 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 388 { 389 return isa->setMiscRegNoEffect(misc_reg, val); 390 } 391 392 void 393 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 394 { 395 return isa->setMiscReg(misc_reg, val, tc); 396 } 397 398 int 399 flattenIntIndex(int reg) 400 { 401 return isa->flattenIntIndex(reg); 402 } 403 404 int 405 flattenFloatIndex(int reg) 406 { 407 return isa->flattenFloatIndex(reg); 408 } 409 410 int 411 flattenCCIndex(int reg) 412 { 413 return isa->flattenCCIndex(reg); 414 } 415 416 int 417 flattenMiscIndex(int reg) 418 { 419 return isa->flattenMiscIndex(reg); 420 } 421 422 unsigned readStCondFailures() { return storeCondFailures; } 423 424 void setStCondFailures(unsigned sc_failures) 425 { storeCondFailures = sc_failures; } 426 427 void syscall(int64_t callnum) 428 { 429 process->syscall(callnum, tc); 430 } 431 432 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 433 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 434 435 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 436 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 437 438 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 439 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 440 floatRegs.i[idx] = val; 441 } 442 443#ifdef ISA_HAS_CC_REGS 444 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 445 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 446#else 447 CCReg readCCRegFlat(int idx) 448 { panic("readCCRegFlat w/no CC regs!\n"); } 449 450 void setCCRegFlat(int idx, CCReg val) 451 { panic("setCCRegFlat w/no CC regs!\n"); } 452#endif 453}; 454 455 456#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 457