simple_thread.hh revision 873
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __EXEC_CONTEXT_HH__ 30#define __EXEC_CONTEXT_HH__ 31 32#include "sim/host.hh" 33#include "mem/mem_req.hh" 34#include "sim/serialize.hh" 35#include "targetarch/byte_swap.hh" 36 37// forward declaration: see functional_memory.hh 38class FunctionalMemory; 39class PhysicalMemory; 40class BaseCPU; 41 42#ifdef FULL_SYSTEM 43 44#include "targetarch/alpha_memory.hh" 45class MemoryController; 46 47#include "kern/tru64/kernel_stats.hh" 48#include "sim/system.hh" 49#include "sim/sw_context.hh" 50 51#else // !FULL_SYSTEM 52 53#include "sim/process.hh" 54 55#endif // FULL_SYSTEM 56 57// 58// The ExecContext object represents a functional context for 59// instruction execution. It incorporates everything required for 60// architecture-level functional simulation of a single thread. 61// 62 63class ExecContext 64{ 65 public: 66 enum Status 67 { 68 /// Initialized but not running yet. All CPUs start in 69 /// this state, but most transition to Active on cycle 1. 70 /// In MP or SMT systems, non-primary contexts will stay 71 /// in this state until a thread is assigned to them. 72 Unallocated, 73 74 /// Running. Instructions should be executed only when 75 /// the context is in this state. 76 Active, 77 78 /// Temporarily inactive. Entered while waiting for 79 /// synchronization, etc. 80 Suspended, 81 82 /// Permanently shut down. Entered when target executes 83 /// m5exit pseudo-instruction. When all contexts enter 84 /// this state, the simulation will terminate. 85 Halted 86 }; 87 88 private: 89 Status _status; 90 91 public: 92 Status status() const { return _status; } 93 94 /// Set the status to Active. Optional delay indicates number of 95 /// cycles to wait before beginning execution. 96 void activate(int delay = 1); 97 98 /// Set the status to Suspended. 99 void suspend(); 100 101 /// Set the status to Unallocated. 102 void deallocate(); 103 104 /// Set the status to Halted. 105 void halt(); 106 107#ifdef FULL_SYSTEM 108 public: 109 KernelStats kernelStats; 110#endif 111 112 public: 113 RegFile regs; // correct-path register context 114 115 // pointer to CPU associated with this context 116 BaseCPU *cpu; 117 118 // Index of hardware thread context on the CPU that this represents. 119 int thread_num; 120 121 // ID of this context w.r.t. the System or Process object to which 122 // it belongs. For full-system mode, this is the system CPU ID. 123 int cpu_id; 124 125#ifdef FULL_SYSTEM 126 127 FunctionalMemory *mem; 128 AlphaITB *itb; 129 AlphaDTB *dtb; 130 System *system; 131 132 // the following two fields are redundant, since we can always 133 // look them up through the system pointer, but we'll leave them 134 // here for now for convenience 135 MemoryController *memCtrl; 136 PhysicalMemory *physmem; 137 138 SWContext *swCtx; 139#else 140 Process *process; 141 142 FunctionalMemory *mem; // functional storage for process address space 143 144 // Address space ID. Note that this is used for TIMING cache 145 // simulation only; all functional memory accesses should use 146 // one of the FunctionalMemory pointers above. 147 short asid; 148 149#endif 150 151 /** 152 * Temporary storage to pass the source address from copy_load to 153 * copy_store. 154 * @todo Remove this temporary when we have a better way to do it. 155 */ 156 Addr copySrcAddr; 157 /** 158 * Temp storage for the physical source address of a copy. 159 * @todo Remove this temporary when we have a better way to do it. 160 */ 161 Addr copySrcPhysAddr; 162 163 164 /* 165 * number of executed instructions, for matching with syscall trace 166 * points in EIO files. 167 */ 168 Counter func_exe_inst; 169 170 // 171 // Count failed store conditionals so we can warn of apparent 172 // application deadlock situations. 173 unsigned storeCondFailures; 174 175 // constructor: initialize context from given process structure 176#ifdef FULL_SYSTEM 177 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 178 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 179#else 180 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 181 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 182 int _asid); 183#endif 184 virtual ~ExecContext() {} 185 186 virtual void takeOverFrom(ExecContext *oldContext); 187 188 void regStats(const std::string &name); 189 190 void serialize(std::ostream &os); 191 void unserialize(Checkpoint *cp, const std::string §ion); 192 193#ifdef FULL_SYSTEM 194 bool validInstAddr(Addr addr) { return true; } 195 bool validDataAddr(Addr addr) { return true; } 196 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } 197 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } 198 199 Fault translateInstReq(MemReqPtr &req) 200 { 201 return itb->translate(req); 202 } 203 204 Fault translateDataReadReq(MemReqPtr &req) 205 { 206 return dtb->translate(req, false); 207 } 208 209 Fault translateDataWriteReq(MemReqPtr &req) 210 { 211 return dtb->translate(req, true); 212 } 213 214#else 215 bool validInstAddr(Addr addr) 216 { return process->validInstAddr(addr); } 217 218 bool validDataAddr(Addr addr) 219 { return process->validDataAddr(addr); } 220 221 int getInstAsid() { return asid; } 222 int getDataAsid() { return asid; } 223 224 Fault dummyTranslation(MemReqPtr &req) 225 { 226#if 0 227 assert((req->vaddr >> 48 & 0xffff) == 0); 228#endif 229 230 // put the asid in the upper 16 bits of the paddr 231 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 232 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 233 return No_Fault; 234 } 235 Fault translateInstReq(MemReqPtr &req) 236 { 237 return dummyTranslation(req); 238 } 239 Fault translateDataReadReq(MemReqPtr &req) 240 { 241 return dummyTranslation(req); 242 } 243 Fault translateDataWriteReq(MemReqPtr &req) 244 { 245 return dummyTranslation(req); 246 } 247 248#endif 249 250 template <class T> 251 Fault read(MemReqPtr &req, T &data) 252 { 253#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 254 if (req->flags & LOCKED) { 255 MiscRegFile *cregs = &req->xc->regs.miscRegs; 256 cregs->lock_addr = req->paddr; 257 cregs->lock_flag = true; 258 } 259#endif 260 261 Fault error; 262 error = mem->read(req, data); 263 data = htoa(data); 264 return error; 265 } 266 267 template <class T> 268 Fault write(MemReqPtr &req, T &data) 269 { 270#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 271 272 MiscRegFile *cregs; 273 274 // If this is a store conditional, act appropriately 275 if (req->flags & LOCKED) { 276 cregs = &req->xc->regs.miscRegs; 277 278 if (req->flags & UNCACHEABLE) { 279 // Don't update result register (see stq_c in isa_desc) 280 req->result = 2; 281 req->xc->storeCondFailures = 0;//Needed? [RGD] 282 } else { 283 req->result = cregs->lock_flag; 284 if (!cregs->lock_flag || 285 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 286 cregs->lock_flag = false; 287 if (((++req->xc->storeCondFailures) % 100000) == 0) { 288 std::cerr << "Warning: " 289 << req->xc->storeCondFailures 290 << " consecutive store conditional failures " 291 << "on cpu " << req->xc->cpu_id 292 << std::endl; 293 } 294 return No_Fault; 295 } 296 else req->xc->storeCondFailures = 0; 297 } 298 } 299 300 // Need to clear any locked flags on other proccessors for 301 // this address. Only do this for succsful Store Conditionals 302 // and all other stores (WH64?). Unsuccessful Store 303 // Conditionals would have returned above, and wouldn't fall 304 // through. 305 for (int i = 0; i < system->execContexts.size(); i++){ 306 cregs = &system->execContexts[i]->regs.miscRegs; 307 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 308 cregs->lock_flag = false; 309 } 310 } 311 312#endif 313 return mem->write(req, (T)htoa(data)); 314 } 315 316 virtual bool misspeculating(); 317 318 319 // 320 // New accessors for new decoder. 321 // 322 uint64_t readIntReg(int reg_idx) 323 { 324 return regs.intRegFile[reg_idx]; 325 } 326 327 float readFloatRegSingle(int reg_idx) 328 { 329 return (float)regs.floatRegFile.d[reg_idx]; 330 } 331 332 double readFloatRegDouble(int reg_idx) 333 { 334 return regs.floatRegFile.d[reg_idx]; 335 } 336 337 uint64_t readFloatRegInt(int reg_idx) 338 { 339 return regs.floatRegFile.q[reg_idx]; 340 } 341 342 void setIntReg(int reg_idx, uint64_t val) 343 { 344 regs.intRegFile[reg_idx] = val; 345 } 346 347 void setFloatRegSingle(int reg_idx, float val) 348 { 349 regs.floatRegFile.d[reg_idx] = (double)val; 350 } 351 352 void setFloatRegDouble(int reg_idx, double val) 353 { 354 regs.floatRegFile.d[reg_idx] = val; 355 } 356 357 void setFloatRegInt(int reg_idx, uint64_t val) 358 { 359 regs.floatRegFile.q[reg_idx] = val; 360 } 361 362 uint64_t readPC() 363 { 364 return regs.pc; 365 } 366 367 void setNextPC(uint64_t val) 368 { 369 regs.npc = val; 370 } 371 372 uint64_t readUniq() 373 { 374 return regs.miscRegs.uniq; 375 } 376 377 void setUniq(uint64_t val) 378 { 379 regs.miscRegs.uniq = val; 380 } 381 382 uint64_t readFpcr() 383 { 384 return regs.miscRegs.fpcr; 385 } 386 387 void setFpcr(uint64_t val) 388 { 389 regs.miscRegs.fpcr = val; 390 } 391 392#ifdef FULL_SYSTEM 393 uint64_t readIpr(int idx, Fault &fault); 394 Fault setIpr(int idx, uint64_t val); 395 int readIntrFlag() { return regs.intrflag; } 396 void setIntrFlag(int val) { regs.intrflag = val; } 397 Fault hwrei(); 398 bool inPalMode() { return PC_PAL(regs.pc); } 399 void ev5_trap(Fault fault); 400 bool simPalCheck(int palFunc); 401#endif 402 403#ifndef FULL_SYSTEM 404 IntReg getSyscallArg(int i) 405 { 406 return regs.intRegFile[ArgumentReg0 + i]; 407 } 408 409 // used to shift args for indirect syscall 410 void setSyscallArg(int i, IntReg val) 411 { 412 regs.intRegFile[ArgumentReg0 + i] = val; 413 } 414 415 void setSyscallReturn(int64_t return_value) 416 { 417 // check for error condition. Alpha syscall convention is to 418 // indicate success/failure in reg a3 (r19) and put the 419 // return value itself in the standard return value reg (v0). 420 const int RegA3 = 19; // only place this is used 421 if (return_value >= 0) { 422 // no error 423 regs.intRegFile[RegA3] = 0; 424 regs.intRegFile[ReturnValueReg] = return_value; 425 } else { 426 // got an error, return details 427 regs.intRegFile[RegA3] = (IntReg) -1; 428 regs.intRegFile[ReturnValueReg] = -return_value; 429 } 430 } 431 432 void syscall() 433 { 434 process->syscall(this); 435 } 436#endif 437}; 438 439 440// for non-speculative execution context, spec_mode is always false 441inline bool 442ExecContext::misspeculating() 443{ 444 return false; 445} 446 447#endif // __EXEC_CONTEXT_HH__ 448