simple_thread.hh revision 8357
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 432680SN/A#include "cpu/thread_context.hh" 442683Sktlim@umich.edu#include "cpu/thread_state.hh" 458232Snate@binkert.org#include "debug/FloatRegs.hh" 468232Snate@binkert.org#include "debug/IntRegs.hh" 472395SN/A#include "mem/request.hh" 482190SN/A#include "sim/byteswap.hh" 492188SN/A#include "sim/eventq.hh" 50217SN/A#include "sim/serialize.hh" 512SN/A 522SN/Aclass BaseCPU; 532SN/A 541858SN/A#if FULL_SYSTEM 552SN/A 561070SN/A#include "sim/system.hh" 571070SN/A 581917SN/Aclass FunctionProfile; 591917SN/Aclass ProfileNode; 602521SN/Aclass FunctionalPort; 612521SN/Aclass PhysicalPort; 622521SN/A 633548Sgblack@eecs.umich.edunamespace TheISA { 643548Sgblack@eecs.umich.edu namespace Kernel { 653548Sgblack@eecs.umich.edu class Statistics; 663548Sgblack@eecs.umich.edu }; 672330SN/A}; 682330SN/A 692SN/A#else // !FULL_SYSTEM 702SN/A 718229Snate@binkert.org#include "mem/page_table.hh" 72360SN/A#include "sim/process.hh" 732420SN/Aclass TranslatingPort; 742SN/A 752SN/A#endif // FULL_SYSTEM 762SN/A 772683Sktlim@umich.edu/** 782683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 792683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 802683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 812683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 822683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 832683Sktlim@umich.edu * the objects needed for simple functional execution, including a 842683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 852683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 862683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 872683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 882683Sktlim@umich.edu * all the necessary state for full architecture-level functional 892683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 902683Sktlim@umich.edu * examples. 912683Sktlim@umich.edu */ 922SN/A 932683Sktlim@umich.educlass SimpleThread : public ThreadState 942SN/A{ 952107SN/A protected: 962107SN/A typedef TheISA::MachInst MachInst; 972159SN/A typedef TheISA::MiscReg MiscReg; 982455SN/A typedef TheISA::FloatReg FloatReg; 992455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1002SN/A public: 1012680SN/A typedef ThreadContext::Status Status; 1022SN/A 1032190SN/A protected: 1046315Sgblack@eecs.umich.edu union { 1056315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1066315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1076315Sgblack@eecs.umich.edu } floatRegs; 1086316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1096313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1102SN/A 1117720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1126324Sgblack@eecs.umich.edu 1137597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1147597Sminkyu.jeong@arm.com bool predicate; 1157597Sminkyu.jeong@arm.com 1162190SN/A public: 1178357Sksewell@umich.edu std::string name() const 1188357Sksewell@umich.edu { 1198357Sksewell@umich.edu return csprintf("%s.[tid:%i]", cpu->name(), tc->threadId()); 1208357Sksewell@umich.edu } 1218357Sksewell@umich.edu 1222683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1232SN/A BaseCPU *cpu; 1242SN/A 1252683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1262188SN/A 1272378SN/A System *system; 1282400SN/A 1296022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1306022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1312SN/A 1322683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1331858SN/A#if FULL_SYSTEM 1342683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1356022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1362683Sktlim@umich.edu bool use_kernel_stats = true); 1372SN/A#else 1384997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1396331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1402SN/A#endif 1412862Sktlim@umich.edu 1422864Sktlim@umich.edu SimpleThread(); 1432862Sktlim@umich.edu 1442683Sktlim@umich.edu virtual ~SimpleThread(); 1452SN/A 1462680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 147180SN/A 1482SN/A void regStats(const std::string &name); 1492SN/A 1502864Sktlim@umich.edu void copyTC(ThreadContext *context); 1512864Sktlim@umich.edu 1522862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1532862Sktlim@umich.edu 154217SN/A void serialize(std::ostream &os); 155237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 156217SN/A 1572683Sktlim@umich.edu /*************************************************************** 1582683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1595891Sgblack@eecs.umich.edu * state. 1602683Sktlim@umich.edu **************************************************************/ 1612190SN/A 1622683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1632683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1642683Sktlim@umich.edu * CPU. 1652683Sktlim@umich.edu */ 1662680SN/A ThreadContext *getTC() { return tc; } 1672190SN/A 1685358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1695358Sgblack@eecs.umich.edu { 1705358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1715358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1725358Sgblack@eecs.umich.edu } 1735358Sgblack@eecs.umich.edu 1745358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1755358Sgblack@eecs.umich.edu { 1765358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1775358Sgblack@eecs.umich.edu } 1785358Sgblack@eecs.umich.edu 1795358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1805358Sgblack@eecs.umich.edu { 1815358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu } 1835358Sgblack@eecs.umich.edu 1844997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1852683Sktlim@umich.edu void dumpFuncProfile(); 1862521SN/A 1875702Ssaidi@eecs.umich.edu Fault hwrei(); 1885702Ssaidi@eecs.umich.edu 1895702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1905702Ssaidi@eecs.umich.edu 1912683Sktlim@umich.edu#endif 1922SN/A 1932683Sktlim@umich.edu /******************************************* 1942683Sktlim@umich.edu * ThreadContext interface functions. 1952683Sktlim@umich.edu ******************************************/ 1962683Sktlim@umich.edu 1972683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1982683Sktlim@umich.edu 1996022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2002683Sktlim@umich.edu 2016022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2022683Sktlim@umich.edu 2034997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2044997Sgblack@eecs.umich.edu 2055803Snate@binkert.org#if FULL_SYSTEM 2062683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2072683Sktlim@umich.edu 2085499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2095499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2105499Ssaidi@eecs.umich.edu * mean stale data. 2115499Ssaidi@eecs.umich.edu */ 2125499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2132SN/A#endif 2142SN/A 2152683Sktlim@umich.edu Status status() const { return _status; } 2162683Sktlim@umich.edu 2172683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2182683Sktlim@umich.edu 2192683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2202683Sktlim@umich.edu /// cycles to wait before beginning execution. 2212683Sktlim@umich.edu void activate(int delay = 1); 2222683Sktlim@umich.edu 2232683Sktlim@umich.edu /// Set the status to Suspended. 2242683Sktlim@umich.edu void suspend(); 2252683Sktlim@umich.edu 2262683Sktlim@umich.edu /// Set the status to Halted. 2272683Sktlim@umich.edu void halt(); 2282683Sktlim@umich.edu 2292SN/A virtual bool misspeculating(); 2302SN/A 2312683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2322190SN/A 2336315Sgblack@eecs.umich.edu void clearArchRegs() 2346315Sgblack@eecs.umich.edu { 2357720Sgblack@eecs.umich.edu _pcState = 0; 2366316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2376315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2387400SAli.Saidi@ARM.com isa.clear(); 2396315Sgblack@eecs.umich.edu } 2402190SN/A 2412SN/A // 2422SN/A // New accessors for new decoder. 2432SN/A // 2442SN/A uint64_t readIntReg(int reg_idx) 2452SN/A { 2466313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2476323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2486418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2497601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2507601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2516418Sgblack@eecs.umich.edu return regVal; 2522SN/A } 2532SN/A 2542455SN/A FloatReg readFloatReg(int reg_idx) 2552SN/A { 2566313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2576323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2587341Sgblack@eecs.umich.edu FloatReg regVal = floatRegs.f[flatIndex]; 2597601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 2607601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2617341Sgblack@eecs.umich.edu return regVal; 2622SN/A } 2632SN/A 2642455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2652455SN/A { 2666313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2676323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2687341Sgblack@eecs.umich.edu FloatRegBits regVal = floatRegs.i[flatIndex]; 2697601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2707601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2717341Sgblack@eecs.umich.edu return regVal; 2722SN/A } 2732SN/A 2742SN/A void setIntReg(int reg_idx, uint64_t val) 2752SN/A { 2766313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2776323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2787601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2797601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 2806316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2812SN/A } 2822SN/A 2832455SN/A void setFloatReg(int reg_idx, FloatReg val) 2842SN/A { 2856313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2866323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2876315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2887601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 2897601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 2902SN/A } 2912SN/A 2922455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2932455SN/A { 2946313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2956323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2966315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 2977601Sminkyu.jeong@arm.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 2987601Sminkyu.jeong@arm.com reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 2992SN/A } 3002SN/A 3017720Sgblack@eecs.umich.edu TheISA::PCState 3027720Sgblack@eecs.umich.edu pcState() 3032SN/A { 3047720Sgblack@eecs.umich.edu return _pcState; 3052SN/A } 3062SN/A 3077720Sgblack@eecs.umich.edu void 3087720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3092190SN/A { 3107720Sgblack@eecs.umich.edu _pcState = val; 3112190SN/A } 3122190SN/A 3137720Sgblack@eecs.umich.edu Addr 3147720Sgblack@eecs.umich.edu instAddr() 3153276Sgblack@eecs.umich.edu { 3167720Sgblack@eecs.umich.edu return _pcState.instAddr(); 3173276Sgblack@eecs.umich.edu } 3183276Sgblack@eecs.umich.edu 3197720Sgblack@eecs.umich.edu Addr 3207720Sgblack@eecs.umich.edu nextInstAddr() 3213276Sgblack@eecs.umich.edu { 3227720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 3233276Sgblack@eecs.umich.edu } 3243276Sgblack@eecs.umich.edu 3257720Sgblack@eecs.umich.edu MicroPC 3267720Sgblack@eecs.umich.edu microPC() 3272190SN/A { 3287720Sgblack@eecs.umich.edu return _pcState.microPC(); 3292251SN/A } 3302251SN/A 3317597Sminkyu.jeong@arm.com bool readPredicate() 3327597Sminkyu.jeong@arm.com { 3337597Sminkyu.jeong@arm.com return predicate; 3347597Sminkyu.jeong@arm.com } 3357597Sminkyu.jeong@arm.com 3367597Sminkyu.jeong@arm.com void setPredicate(bool val) 3377597Sminkyu.jeong@arm.com { 3387597Sminkyu.jeong@arm.com predicate = val; 3397597Sminkyu.jeong@arm.com } 3407597Sminkyu.jeong@arm.com 3416221Snate@binkert.org MiscReg 3426221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3434172Ssaidi@eecs.umich.edu { 3446313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3454172Ssaidi@eecs.umich.edu } 3464172Ssaidi@eecs.umich.edu 3476221Snate@binkert.org MiscReg 3486221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3492SN/A { 3506313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3512SN/A } 3522SN/A 3536221Snate@binkert.org void 3546221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3552SN/A { 3566313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3572SN/A } 3582SN/A 3596221Snate@binkert.org void 3606221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3612SN/A { 3626313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3636313Sgblack@eecs.umich.edu } 3646313Sgblack@eecs.umich.edu 3656313Sgblack@eecs.umich.edu int 3666313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3676313Sgblack@eecs.umich.edu { 3686313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3696313Sgblack@eecs.umich.edu } 3706313Sgblack@eecs.umich.edu 3716313Sgblack@eecs.umich.edu int 3726313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3736313Sgblack@eecs.umich.edu { 3746313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3752SN/A } 3762SN/A 3772190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3782190SN/A 3792190SN/A void setStCondFailures(unsigned sc_failures) 3802190SN/A { storeCondFailures = sc_failures; } 3812190SN/A 3821858SN/A#if !FULL_SYSTEM 3832561SN/A void syscall(int64_t callnum) 3842SN/A { 3852680SN/A process->syscall(callnum, tc); 3862SN/A } 3872SN/A#endif 3882SN/A}; 3892SN/A 3902SN/A 3912SN/A// for non-speculative execution context, spec_mode is always false 3922SN/Ainline bool 3932683Sktlim@umich.eduSimpleThread::misspeculating() 3942SN/A{ 3952SN/A return false; 3962SN/A} 3972SN/A 3982190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 399