simple_thread.hh revision 716
14202Sbinkertn@umich.edu/* 24202Sbinkertn@umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 34202Sbinkertn@umich.edu * All rights reserved. 44202Sbinkertn@umich.edu * 54202Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64202Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74202Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94202Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104202Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114202Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124202Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134202Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144202Sbinkertn@umich.edu * this software without specific prior written permission. 154202Sbinkertn@umich.edu * 164202Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174202Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184202Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194202Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204202Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224202Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244202Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254202Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264202Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274202Sbinkertn@umich.edu */ 284202Sbinkertn@umich.edu 294202Sbinkertn@umich.edu#ifndef __EXEC_CONTEXT_HH__ 304202Sbinkertn@umich.edu#define __EXEC_CONTEXT_HH__ 314202Sbinkertn@umich.edu 324202Sbinkertn@umich.edu#include "sim/host.hh" 3310996Sandreas.sandberg@arm.com#include "mem/mem_req.hh" 3410996Sandreas.sandberg@arm.com#include "mem/functional_mem/functional_memory.hh" 359398Sandreas.hansson@arm.com#include "sim/serialize.hh" 369850Sandreas.hansson@arm.com 379259SAli.Saidi@ARM.com// forward declaration: see functional_memory.hh 384486Sbinkertn@umich.educlass FunctionalMemory; 3910146Sandreas.hansson@arm.comclass PhysicalMemory; 4010478SAndrew.Bardsley@arm.comclass BaseCPU; 4110478SAndrew.Bardsley@arm.com 426165Ssanchezd@stanford.edu#ifdef FULL_SYSTEM 439850Sandreas.hansson@arm.com 4410405Sandreas.hansson@arm.com#include "targetarch/alpha_memory.hh" 4511184Serfan.azarkhish@unibo.itclass MemoryController; 4611185Serfan.azarkhish@unibo.it 4712802Sandreas.sandberg@arm.com#include "kern/tru64/kernel_stats.hh" 486168Snate@binkert.org#include "sim/system.hh" 499850Sandreas.hansson@arm.com#include "sim/sw_context.hh" 509259SAli.Saidi@ARM.com 514202Sbinkertn@umich.edu#else // !FULL_SYSTEM 5210405Sandreas.hansson@arm.com 5310431SOmar.Naji@arm.com#include "sim/process.hh" 5410146Sandreas.hansson@arm.com 5510478SAndrew.Bardsley@arm.com#endif // FULL_SYSTEM 5610478SAndrew.Bardsley@arm.com 574202Sbinkertn@umich.edu// 588761Sgblack@eecs.umich.edu// The ExecContext object represents a functional context for 5910405Sandreas.hansson@arm.com// instruction execution. It incorporates everything required for 604202Sbinkertn@umich.edu// architecture-level functional simulation of a single thread. 614202Sbinkertn@umich.edu// 628914Sandreas.hansson@arm.com 6310405Sandreas.hansson@arm.comclass ExecContext 6410405Sandreas.hansson@arm.com{ 6510405Sandreas.hansson@arm.com public: 6610405Sandreas.hansson@arm.com enum Status 6710614Skanishk.sugand@arm.com { 684202Sbinkertn@umich.edu /// Initialized but not running yet. All CPUs start in 6910405Sandreas.hansson@arm.com /// this state, but most transition to Active on cycle 1. 7011184Serfan.azarkhish@unibo.it /// In MP or SMT systems, non-primary contexts will stay 7111185Serfan.azarkhish@unibo.it /// in this state until a thread is assigned to them. 7212802Sandreas.sandberg@arm.com Unallocated, 736168Snate@binkert.org 749850Sandreas.hansson@arm.com /// Running. Instructions should be executed only when 759850Sandreas.hansson@arm.com /// the context is in this state. 769850Sandreas.hansson@arm.com Active, 778763Sgblack@eecs.umich.edu 787768SAli.Saidi@ARM.com /// Temporarily inactive. Entered while waiting for 7910131Sandreas.hansson@arm.com /// synchronization, etc. 8010131Sandreas.hansson@arm.com Suspended, 8110131Sandreas.hansson@arm.com 8210131Sandreas.hansson@arm.com /// Permanently shut down. Entered when target executes 8310066Sandreas.hansson@arm.com /// m5exit pseudo-instruction. When all contexts enter 8410612SMarco.Elver@ARM.com /// this state, the simulation will terminate. 8510612SMarco.Elver@ARM.com Halted 8610612SMarco.Elver@ARM.com }; 8710612SMarco.Elver@ARM.com 8810405Sandreas.hansson@arm.com private: 8910405Sandreas.hansson@arm.com Status _status; 9010405Sandreas.hansson@arm.com 9110405Sandreas.hansson@arm.com public: 9210399Sstephan.diestelhorst@arm.com Status status() const { return _status; } 9310405Sandreas.hansson@arm.com 9410405Sandreas.hansson@arm.com /// Set the status to Active. Optional delay indicates number of 959036Sandreas.hansson@arm.com /// cycles to wait before beginning execution. 969164Sandreas.hansson@arm.com void activate(int delay = 1); 978981Sandreas.hansson@arm.com 989243Sandreas.hansson@arm.com /// Set the status to Suspended. 9910247Sandreas.hansson@arm.com void suspend(); 10010208Sandreas.hansson@arm.com 10110478SAndrew.Bardsley@arm.com /// Set the status to Unallocated. 1028335Snate@binkert.org void deallocate(); 1038335Snate@binkert.org 1048335Snate@binkert.org /// Set the status to Halted. 1058914Sandreas.hansson@arm.com void halt(); 10610614Skanishk.sugand@arm.com 10710066Sandreas.hansson@arm.com#ifdef FULL_SYSTEM 10811184Serfan.azarkhish@unibo.it public: 10911185Serfan.azarkhish@unibo.it KernelStats kernelStats; 11010612SMarco.Elver@ARM.com#endif 11110612SMarco.Elver@ARM.com 11210612SMarco.Elver@ARM.com public: 113 RegFile regs; // correct-path register context 114 115 // pointer to CPU associated with this context 116 BaseCPU *cpu; 117 118 // Current instruction 119 MachInst inst; 120 121 // Index of hardware thread context on the CPU that this represents. 122 int thread_num; 123 124 // ID of this context w.r.t. the System or Process object to which 125 // it belongs. For full-system mode, this is the system CPU ID. 126 int cpu_id; 127 128#ifdef FULL_SYSTEM 129 130 FunctionalMemory *mem; 131 AlphaITB *itb; 132 AlphaDTB *dtb; 133 System *system; 134 135 // the following two fields are redundant, since we can always 136 // look them up through the system pointer, but we'll leave them 137 // here for now for convenience 138 MemoryController *memCtrl; 139 PhysicalMemory *physmem; 140 141 SWContext *swCtx; 142#else 143 Process *process; 144 145 FunctionalMemory *mem; // functional storage for process address space 146 147 // Address space ID. Note that this is used for TIMING cache 148 // simulation only; all functional memory accesses should use 149 // one of the FunctionalMemory pointers above. 150 short asid; 151 152#endif 153 154 /** 155 * Temporary storage to pass the source address from copy_load to 156 * copy_store. 157 * @todo Remove this temporary when we have a better way to do it. 158 */ 159 Addr copySrcAddr; 160 /** 161 * Temp storage for the physical source address of a copy. 162 * @todo Remove this temporary when we have a better way to do it. 163 */ 164 Addr copySrcPhysAddr; 165 166 167 /* 168 * number of executed instructions, for matching with syscall trace 169 * points in EIO files. 170 */ 171 Counter func_exe_inst; 172 173 // 174 // Count failed store conditionals so we can warn of apparent 175 // application deadlock situations. 176 unsigned storeCondFailures; 177 178 // constructor: initialize context from given process structure 179#ifdef FULL_SYSTEM 180 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 181 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 182#else 183 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 184 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 185 int _asid); 186#endif 187 virtual ~ExecContext() {} 188 189 virtual void takeOverFrom(ExecContext *oldContext); 190 191 void regStats(const std::string &name); 192 193 void serialize(std::ostream &os); 194 void unserialize(Checkpoint *cp, const std::string §ion); 195 196#ifdef FULL_SYSTEM 197 bool validInstAddr(Addr addr) { return true; } 198 bool validDataAddr(Addr addr) { return true; } 199 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } 200 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } 201 202 Fault translateInstReq(MemReqPtr &req) 203 { 204 return itb->translate(req); 205 } 206 207 Fault translateDataReadReq(MemReqPtr &req) 208 { 209 return dtb->translate(req, false); 210 } 211 212 Fault translateDataWriteReq(MemReqPtr &req) 213 { 214 return dtb->translate(req, true); 215 } 216 217#else 218 bool validInstAddr(Addr addr) 219 { return process->validInstAddr(addr); } 220 221 bool validDataAddr(Addr addr) 222 { return process->validDataAddr(addr); } 223 224 int getInstAsid() { return asid; } 225 int getDataAsid() { return asid; } 226 227 Fault dummyTranslation(MemReqPtr &req) 228 { 229#if 0 230 assert((req->vaddr >> 48 & 0xffff) == 0); 231#endif 232 233 // put the asid in the upper 16 bits of the paddr 234 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 235 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 236 return No_Fault; 237 } 238 Fault translateInstReq(MemReqPtr &req) 239 { 240 return dummyTranslation(req); 241 } 242 Fault translateDataReadReq(MemReqPtr &req) 243 { 244 return dummyTranslation(req); 245 } 246 Fault translateDataWriteReq(MemReqPtr &req) 247 { 248 return dummyTranslation(req); 249 } 250 251#endif 252 253 template <class T> 254 Fault read(MemReqPtr &req, T &data) 255 { 256#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 257 if (req->flags & LOCKED) { 258 MiscRegFile *cregs = &req->xc->regs.miscRegs; 259 cregs->lock_addr = req->paddr; 260 cregs->lock_flag = true; 261 } 262#endif 263 return mem->read(req, data); 264 } 265 266 template <class T> 267 Fault write(MemReqPtr &req, T &data) 268 { 269#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 270 271 MiscRegFile *cregs; 272 273 // If this is a store conditional, act appropriately 274 if (req->flags & LOCKED) { 275 cregs = &req->xc->regs.miscRegs; 276 277 if (req->flags & UNCACHEABLE) { 278 // Don't update result register (see stq_c in isa_desc) 279 req->result = 2; 280 req->xc->storeCondFailures = 0;//Needed? [RGD] 281 } else { 282 req->result = cregs->lock_flag; 283 if (!cregs->lock_flag || 284 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 285 cregs->lock_flag = false; 286 if (((++req->xc->storeCondFailures) % 100000) == 0) { 287 std::cerr << "Warning: " 288 << req->xc->storeCondFailures 289 << " consecutive store conditional failures " 290 << "on cpu " << req->xc->cpu_id 291 << std::endl; 292 } 293 return No_Fault; 294 } 295 else req->xc->storeCondFailures = 0; 296 } 297 } 298 299 // Need to clear any locked flags on other proccessors for 300 // this address. Only do this for succsful Store Conditionals 301 // and all other stores (WH64?). Unsuccessful Store 302 // Conditionals would have returned above, and wouldn't fall 303 // through. 304 for (int i = 0; i < system->execContexts.size(); i++){ 305 cregs = &system->execContexts[i]->regs.miscRegs; 306 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 307 cregs->lock_flag = false; 308 } 309 } 310 311#endif 312 return mem->write(req, data); 313 } 314 315 virtual bool misspeculating(); 316 317 318 MachInst getInst() { return inst; } 319 320 void setInst(MachInst new_inst) 321 { 322 inst = new_inst; 323 } 324 325 Fault instRead(MemReqPtr &req) 326 { 327 return mem->read(req, inst); 328 } 329 330 // 331 // New accessors for new decoder. 332 // 333 uint64_t readIntReg(int reg_idx) 334 { 335 return regs.intRegFile[reg_idx]; 336 } 337 338 float readFloatRegSingle(int reg_idx) 339 { 340 return (float)regs.floatRegFile.d[reg_idx]; 341 } 342 343 double readFloatRegDouble(int reg_idx) 344 { 345 return regs.floatRegFile.d[reg_idx]; 346 } 347 348 uint64_t readFloatRegInt(int reg_idx) 349 { 350 return regs.floatRegFile.q[reg_idx]; 351 } 352 353 void setIntReg(int reg_idx, uint64_t val) 354 { 355 regs.intRegFile[reg_idx] = val; 356 } 357 358 void setFloatRegSingle(int reg_idx, float val) 359 { 360 regs.floatRegFile.d[reg_idx] = (double)val; 361 } 362 363 void setFloatRegDouble(int reg_idx, double val) 364 { 365 regs.floatRegFile.d[reg_idx] = val; 366 } 367 368 void setFloatRegInt(int reg_idx, uint64_t val) 369 { 370 regs.floatRegFile.q[reg_idx] = val; 371 } 372 373 uint64_t readPC() 374 { 375 return regs.pc; 376 } 377 378 void setNextPC(uint64_t val) 379 { 380 regs.npc = val; 381 } 382 383 uint64_t readUniq() 384 { 385 return regs.miscRegs.uniq; 386 } 387 388 void setUniq(uint64_t val) 389 { 390 regs.miscRegs.uniq = val; 391 } 392 393 uint64_t readFpcr() 394 { 395 return regs.miscRegs.fpcr; 396 } 397 398 void setFpcr(uint64_t val) 399 { 400 regs.miscRegs.fpcr = val; 401 } 402 403#ifdef FULL_SYSTEM 404 uint64_t readIpr(int idx, Fault &fault); 405 Fault setIpr(int idx, uint64_t val); 406 int readIntrFlag() { return regs.intrflag; } 407 void setIntrFlag(int val) { regs.intrflag = val; } 408 Fault hwrei(); 409 bool inPalMode() { return PC_PAL(regs.pc); } 410 void ev5_trap(Fault fault); 411 bool simPalCheck(int palFunc); 412#endif 413 414 /** Meant to be more generic trap function to be 415 * called when an instruction faults. 416 * @param fault The fault generated by executing the instruction. 417 * @todo How to do this properly so it's dependent upon ISA only? 418 */ 419 420 void trap(Fault fault); 421 422#ifndef FULL_SYSTEM 423 IntReg getSyscallArg(int i) 424 { 425 return regs.intRegFile[ArgumentReg0 + i]; 426 } 427 428 // used to shift args for indirect syscall 429 void setSyscallArg(int i, IntReg val) 430 { 431 regs.intRegFile[ArgumentReg0 + i] = val; 432 } 433 434 void setSyscallReturn(int64_t return_value) 435 { 436 // check for error condition. Alpha syscall convention is to 437 // indicate success/failure in reg a3 (r19) and put the 438 // return value itself in the standard return value reg (v0). 439 const int RegA3 = 19; // only place this is used 440 if (return_value >= 0) { 441 // no error 442 regs.intRegFile[RegA3] = 0; 443 regs.intRegFile[ReturnValueReg] = return_value; 444 } else { 445 // got an error, return details 446 regs.intRegFile[RegA3] = (IntReg) -1; 447 regs.intRegFile[ReturnValueReg] = -return_value; 448 } 449 } 450 451 void syscall() 452 { 453 process->syscall(this); 454 } 455#endif 456}; 457 458 459// for non-speculative execution context, spec_mode is always false 460inline bool 461ExecContext::misspeculating() 462{ 463 return false; 464} 465 466#endif // __EXEC_CONTEXT_HH__ 467