simple_thread.hh revision 6658
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396316Sgblack@eecs.umich.edu#include "arch/types.hh" 406216Snate@binkert.org#include "base/types.hh" 411858SN/A#include "config/full_system.hh" 426658Snate@binkert.org#include "config/the_isa.hh" 432680SN/A#include "cpu/thread_context.hh" 442683Sktlim@umich.edu#include "cpu/thread_state.hh" 452395SN/A#include "mem/request.hh" 462190SN/A#include "sim/byteswap.hh" 472188SN/A#include "sim/eventq.hh" 48217SN/A#include "sim/serialize.hh" 492SN/A 502SN/Aclass BaseCPU; 512SN/A 521858SN/A#if FULL_SYSTEM 532SN/A 541070SN/A#include "sim/system.hh" 551070SN/A 561917SN/Aclass FunctionProfile; 571917SN/Aclass ProfileNode; 582521SN/Aclass FunctionalPort; 592521SN/Aclass PhysicalPort; 602521SN/A 613548Sgblack@eecs.umich.edunamespace TheISA { 623548Sgblack@eecs.umich.edu namespace Kernel { 633548Sgblack@eecs.umich.edu class Statistics; 643548Sgblack@eecs.umich.edu }; 652330SN/A}; 662330SN/A 672SN/A#else // !FULL_SYSTEM 682SN/A 69360SN/A#include "sim/process.hh" 702462SN/A#include "mem/page_table.hh" 712420SN/Aclass TranslatingPort; 722SN/A 732SN/A#endif // FULL_SYSTEM 742SN/A 752683Sktlim@umich.edu/** 762683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 772683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 782683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 792683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 802683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 812683Sktlim@umich.edu * the objects needed for simple functional execution, including a 822683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 832683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 842683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 852683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 862683Sktlim@umich.edu * all the necessary state for full architecture-level functional 872683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 882683Sktlim@umich.edu * examples. 892683Sktlim@umich.edu */ 902SN/A 912683Sktlim@umich.educlass SimpleThread : public ThreadState 922SN/A{ 932107SN/A protected: 942107SN/A typedef TheISA::MachInst MachInst; 952159SN/A typedef TheISA::MiscReg MiscReg; 962455SN/A typedef TheISA::FloatReg FloatReg; 972455SN/A typedef TheISA::FloatRegBits FloatRegBits; 982SN/A public: 992680SN/A typedef ThreadContext::Status Status; 1002SN/A 1012190SN/A protected: 1026315Sgblack@eecs.umich.edu union { 1036315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1046315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1056315Sgblack@eecs.umich.edu } floatRegs; 1066316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1076313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1082SN/A 1096324Sgblack@eecs.umich.edu /** The current microcode pc for the currently executing macro 1106324Sgblack@eecs.umich.edu * operation. 1116324Sgblack@eecs.umich.edu */ 1126324Sgblack@eecs.umich.edu MicroPC microPC; 1136324Sgblack@eecs.umich.edu 1146324Sgblack@eecs.umich.edu /** The next microcode pc for the currently executing macro 1156324Sgblack@eecs.umich.edu * operation. 1166324Sgblack@eecs.umich.edu */ 1176324Sgblack@eecs.umich.edu MicroPC nextMicroPC; 1186324Sgblack@eecs.umich.edu 1196324Sgblack@eecs.umich.edu /** The current pc. 1206324Sgblack@eecs.umich.edu */ 1216324Sgblack@eecs.umich.edu Addr PC; 1226324Sgblack@eecs.umich.edu 1236324Sgblack@eecs.umich.edu /** The next pc. 1246324Sgblack@eecs.umich.edu */ 1256324Sgblack@eecs.umich.edu Addr nextPC; 1266324Sgblack@eecs.umich.edu 1276324Sgblack@eecs.umich.edu /** The next next pc. 1286324Sgblack@eecs.umich.edu */ 1296324Sgblack@eecs.umich.edu Addr nextNPC; 1306324Sgblack@eecs.umich.edu 1312190SN/A public: 1322683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1332SN/A BaseCPU *cpu; 1342SN/A 1352683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1362188SN/A 1372378SN/A System *system; 1382400SN/A 1396022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1406022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1412SN/A 1422683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1431858SN/A#if FULL_SYSTEM 1442683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1456022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1462683Sktlim@umich.edu bool use_kernel_stats = true); 1472SN/A#else 1484997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1496331Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb); 1502SN/A#endif 1512862Sktlim@umich.edu 1522864Sktlim@umich.edu SimpleThread(); 1532862Sktlim@umich.edu 1542683Sktlim@umich.edu virtual ~SimpleThread(); 1552SN/A 1562680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 157180SN/A 1582SN/A void regStats(const std::string &name); 1592SN/A 1602864Sktlim@umich.edu void copyTC(ThreadContext *context); 1612864Sktlim@umich.edu 1622862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1632862Sktlim@umich.edu 164217SN/A void serialize(std::ostream &os); 165237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 166217SN/A 1672683Sktlim@umich.edu /*************************************************************** 1682683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1695891Sgblack@eecs.umich.edu * state. 1702683Sktlim@umich.edu **************************************************************/ 1712190SN/A 1722683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1732683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1742683Sktlim@umich.edu * CPU. 1752683Sktlim@umich.edu */ 1762680SN/A ThreadContext *getTC() { return tc; } 1772190SN/A 1785358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1795358Sgblack@eecs.umich.edu { 1805358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1815358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu } 1835358Sgblack@eecs.umich.edu 1845358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1855358Sgblack@eecs.umich.edu { 1865358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1875358Sgblack@eecs.umich.edu } 1885358Sgblack@eecs.umich.edu 1895358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1905358Sgblack@eecs.umich.edu { 1915358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1925358Sgblack@eecs.umich.edu } 1935358Sgblack@eecs.umich.edu 1944997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1952683Sktlim@umich.edu void dumpFuncProfile(); 1962521SN/A 1975702Ssaidi@eecs.umich.edu Fault hwrei(); 1985702Ssaidi@eecs.umich.edu 1995702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 2005702Ssaidi@eecs.umich.edu 2012683Sktlim@umich.edu#endif 2022SN/A 2032683Sktlim@umich.edu /******************************************* 2042683Sktlim@umich.edu * ThreadContext interface functions. 2052683Sktlim@umich.edu ******************************************/ 2062683Sktlim@umich.edu 2072683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 2082683Sktlim@umich.edu 2096022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 2102683Sktlim@umich.edu 2116022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 2122683Sktlim@umich.edu 2134997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2144997Sgblack@eecs.umich.edu 2155803Snate@binkert.org#if FULL_SYSTEM 2162683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 2172683Sktlim@umich.edu 2185499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 2195499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2205499Ssaidi@eecs.umich.edu * mean stale data. 2215499Ssaidi@eecs.umich.edu */ 2225499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2232SN/A#endif 2242SN/A 2252683Sktlim@umich.edu Status status() const { return _status; } 2262683Sktlim@umich.edu 2272683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2282683Sktlim@umich.edu 2292683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2302683Sktlim@umich.edu /// cycles to wait before beginning execution. 2312683Sktlim@umich.edu void activate(int delay = 1); 2322683Sktlim@umich.edu 2332683Sktlim@umich.edu /// Set the status to Suspended. 2342683Sktlim@umich.edu void suspend(); 2352683Sktlim@umich.edu 2362683Sktlim@umich.edu /// Set the status to Halted. 2372683Sktlim@umich.edu void halt(); 2382683Sktlim@umich.edu 2392SN/A virtual bool misspeculating(); 2402SN/A 2412532SN/A Fault instRead(RequestPtr &req) 242716SN/A { 2432378SN/A panic("instRead not implemented"); 2442378SN/A // return funcPhysMem->read(req, inst); 2452423SN/A return NoFault; 246716SN/A } 247716SN/A 2482683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2492190SN/A 2506315Sgblack@eecs.umich.edu void clearArchRegs() 2516315Sgblack@eecs.umich.edu { 2526324Sgblack@eecs.umich.edu microPC = 0; 2536324Sgblack@eecs.umich.edu nextMicroPC = 1; 2546324Sgblack@eecs.umich.edu PC = nextPC = nextNPC = 0; 2556316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 2566315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2576315Sgblack@eecs.umich.edu } 2582190SN/A 2592SN/A // 2602SN/A // New accessors for new decoder. 2612SN/A // 2622SN/A uint64_t readIntReg(int reg_idx) 2632SN/A { 2646313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2656323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2666418Sgblack@eecs.umich.edu uint64_t regVal = intRegs[flatIndex]; 2676418Sgblack@eecs.umich.edu DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal); 2686418Sgblack@eecs.umich.edu return regVal; 2692SN/A } 2702SN/A 2712455SN/A FloatReg readFloatReg(int reg_idx) 2722SN/A { 2736313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2746323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2756315Sgblack@eecs.umich.edu return floatRegs.f[flatIndex]; 2762SN/A } 2772SN/A 2782455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2792455SN/A { 2806313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2816323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2826315Sgblack@eecs.umich.edu return floatRegs.i[flatIndex]; 2832SN/A } 2842SN/A 2852SN/A void setIntReg(int reg_idx, uint64_t val) 2862SN/A { 2876313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2886323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2896418Sgblack@eecs.umich.edu DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val); 2906316Sgblack@eecs.umich.edu intRegs[flatIndex] = val; 2912SN/A } 2922SN/A 2932455SN/A void setFloatReg(int reg_idx, FloatReg val) 2942SN/A { 2956313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2966323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2976315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2982SN/A } 2992SN/A 3002455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3012455SN/A { 3026313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 3036323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3046315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 3052SN/A } 3062SN/A 3072SN/A uint64_t readPC() 3082SN/A { 3096324Sgblack@eecs.umich.edu return PC; 3102SN/A } 3112SN/A 3122190SN/A void setPC(uint64_t val) 3132190SN/A { 3146324Sgblack@eecs.umich.edu PC = val; 3152190SN/A } 3162190SN/A 3173276Sgblack@eecs.umich.edu uint64_t readMicroPC() 3183276Sgblack@eecs.umich.edu { 3193276Sgblack@eecs.umich.edu return microPC; 3203276Sgblack@eecs.umich.edu } 3213276Sgblack@eecs.umich.edu 3223276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 3233276Sgblack@eecs.umich.edu { 3243276Sgblack@eecs.umich.edu microPC = val; 3253276Sgblack@eecs.umich.edu } 3263276Sgblack@eecs.umich.edu 3272190SN/A uint64_t readNextPC() 3282190SN/A { 3296324Sgblack@eecs.umich.edu return nextPC; 3302190SN/A } 3312190SN/A 3322SN/A void setNextPC(uint64_t val) 3332SN/A { 3346324Sgblack@eecs.umich.edu nextPC = val; 3352SN/A } 3362SN/A 3373276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3383276Sgblack@eecs.umich.edu { 3393276Sgblack@eecs.umich.edu return nextMicroPC; 3403276Sgblack@eecs.umich.edu } 3413276Sgblack@eecs.umich.edu 3423276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3433276Sgblack@eecs.umich.edu { 3443276Sgblack@eecs.umich.edu nextMicroPC = val; 3453276Sgblack@eecs.umich.edu } 3463276Sgblack@eecs.umich.edu 3472252SN/A uint64_t readNextNPC() 3482252SN/A { 3496324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3506324Sgblack@eecs.umich.edu return nextNPC; 3516324Sgblack@eecs.umich.edu#else 3526324Sgblack@eecs.umich.edu return nextPC + sizeof(TheISA::MachInst); 3536324Sgblack@eecs.umich.edu#endif 3542252SN/A } 3552252SN/A 3562251SN/A void setNextNPC(uint64_t val) 3572251SN/A { 3586324Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 3596324Sgblack@eecs.umich.edu nextNPC = val; 3606324Sgblack@eecs.umich.edu#endif 3612251SN/A } 3622251SN/A 3636221Snate@binkert.org MiscReg 3646221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3654172Ssaidi@eecs.umich.edu { 3666313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3674172Ssaidi@eecs.umich.edu } 3684172Ssaidi@eecs.umich.edu 3696221Snate@binkert.org MiscReg 3706221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3712SN/A { 3726313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3732SN/A } 3742SN/A 3756221Snate@binkert.org void 3766221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3772SN/A { 3786313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3792SN/A } 3802SN/A 3816221Snate@binkert.org void 3826221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3832SN/A { 3846313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3856313Sgblack@eecs.umich.edu } 3866313Sgblack@eecs.umich.edu 3876313Sgblack@eecs.umich.edu int 3886313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3896313Sgblack@eecs.umich.edu { 3906313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3916313Sgblack@eecs.umich.edu } 3926313Sgblack@eecs.umich.edu 3936313Sgblack@eecs.umich.edu int 3946313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3956313Sgblack@eecs.umich.edu { 3966313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3972SN/A } 3982SN/A 3992190SN/A unsigned readStCondFailures() { return storeCondFailures; } 4002190SN/A 4012190SN/A void setStCondFailures(unsigned sc_failures) 4022190SN/A { storeCondFailures = sc_failures; } 4032190SN/A 4041858SN/A#if !FULL_SYSTEM 4052561SN/A void syscall(int64_t callnum) 4062SN/A { 4072680SN/A process->syscall(callnum, tc); 4082SN/A } 4092SN/A#endif 4102SN/A}; 4112SN/A 4122SN/A 4132SN/A// for non-speculative execution context, spec_mode is always false 4142SN/Ainline bool 4152683Sktlim@umich.eduSimpleThread::misspeculating() 4162SN/A{ 4172SN/A return false; 4182SN/A} 4192SN/A 4202190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 421