simple_thread.hh revision 6315
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302SN/A */ 312SN/A 322683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 332683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 342SN/A 356313Sgblack@eecs.umich.edu#include "arch/isa.hh" 362190SN/A#include "arch/isa_traits.hh" 373776Sgblack@eecs.umich.edu#include "arch/regfile.hh" 384997Sgblack@eecs.umich.edu#include "arch/tlb.hh" 396216Snate@binkert.org#include "base/types.hh" 401858SN/A#include "config/full_system.hh" 412680SN/A#include "cpu/thread_context.hh" 422683Sktlim@umich.edu#include "cpu/thread_state.hh" 432395SN/A#include "mem/request.hh" 442190SN/A#include "sim/byteswap.hh" 452188SN/A#include "sim/eventq.hh" 46217SN/A#include "sim/serialize.hh" 472SN/A 482SN/Aclass BaseCPU; 492SN/A 501858SN/A#if FULL_SYSTEM 512SN/A 521070SN/A#include "sim/system.hh" 531070SN/A 541917SN/Aclass FunctionProfile; 551917SN/Aclass ProfileNode; 562521SN/Aclass FunctionalPort; 572521SN/Aclass PhysicalPort; 582521SN/A 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642330SN/A 652SN/A#else // !FULL_SYSTEM 662SN/A 67360SN/A#include "sim/process.hh" 682462SN/A#include "mem/page_table.hh" 692420SN/Aclass TranslatingPort; 702SN/A 712SN/A#endif // FULL_SYSTEM 722SN/A 732683Sktlim@umich.edu/** 742683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 752683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 762683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 772683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 782683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 792683Sktlim@umich.edu * the objects needed for simple functional execution, including a 802683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 812683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 822683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 832683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 842683Sktlim@umich.edu * all the necessary state for full architecture-level functional 852683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 862683Sktlim@umich.edu * examples. 872683Sktlim@umich.edu */ 882SN/A 892683Sktlim@umich.educlass SimpleThread : public ThreadState 902SN/A{ 912107SN/A protected: 922107SN/A typedef TheISA::RegFile RegFile; 932107SN/A typedef TheISA::MachInst MachInst; 942159SN/A typedef TheISA::MiscReg MiscReg; 952455SN/A typedef TheISA::FloatReg FloatReg; 962455SN/A typedef TheISA::FloatRegBits FloatRegBits; 972SN/A public: 982680SN/A typedef ThreadContext::Status Status; 992SN/A 1002190SN/A protected: 1015543Ssaidi@eecs.umich.edu RegFile regs; // correct-path register context 1026315Sgblack@eecs.umich.edu union { 1036315Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1046315Sgblack@eecs.umich.edu FloatRegBits i[TheISA::NumFloatRegs]; 1056315Sgblack@eecs.umich.edu } floatRegs; 1066313Sgblack@eecs.umich.edu TheISA::ISA isa; // one "instance" of the current ISA. 1072SN/A 1082190SN/A public: 1092683Sktlim@umich.edu // pointer to CPU associated with this SimpleThread 1102SN/A BaseCPU *cpu; 1112SN/A 1122683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1132188SN/A 1142378SN/A System *system; 1152400SN/A 1166022Sgblack@eecs.umich.edu TheISA::TLB *itb; 1176022Sgblack@eecs.umich.edu TheISA::TLB *dtb; 1182SN/A 1192683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1201858SN/A#if FULL_SYSTEM 1212683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1226022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, 1232683Sktlim@umich.edu bool use_kernel_stats = true); 1242SN/A#else 1254997Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, 1266022Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid); 1272SN/A#endif 1282862Sktlim@umich.edu 1292864Sktlim@umich.edu SimpleThread(); 1302862Sktlim@umich.edu 1312683Sktlim@umich.edu virtual ~SimpleThread(); 1322SN/A 1332680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 134180SN/A 1352SN/A void regStats(const std::string &name); 1362SN/A 1372864Sktlim@umich.edu void copyTC(ThreadContext *context); 1382864Sktlim@umich.edu 1392862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1402862Sktlim@umich.edu 141217SN/A void serialize(std::ostream &os); 142237SN/A void unserialize(Checkpoint *cp, const std::string §ion); 143217SN/A 1442683Sktlim@umich.edu /*************************************************************** 1452683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1465891Sgblack@eecs.umich.edu * state. 1472683Sktlim@umich.edu **************************************************************/ 1482190SN/A 1492683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1502683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1512683Sktlim@umich.edu * CPU. 1522683Sktlim@umich.edu */ 1532680SN/A ThreadContext *getTC() { return tc; } 1542190SN/A 1555358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1565358Sgblack@eecs.umich.edu { 1575358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1585358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1595358Sgblack@eecs.umich.edu } 1605358Sgblack@eecs.umich.edu 1615358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1625358Sgblack@eecs.umich.edu { 1635358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1645358Sgblack@eecs.umich.edu } 1655358Sgblack@eecs.umich.edu 1665358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1675358Sgblack@eecs.umich.edu { 1685358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1695358Sgblack@eecs.umich.edu } 1705358Sgblack@eecs.umich.edu 1714997Sgblack@eecs.umich.edu#if FULL_SYSTEM 1726313Sgblack@eecs.umich.edu int getInstAsid() { return isa.instAsid(); } 1736313Sgblack@eecs.umich.edu int getDataAsid() { return isa.dataAsid(); } 1744997Sgblack@eecs.umich.edu 1752683Sktlim@umich.edu void dumpFuncProfile(); 1762521SN/A 1775702Ssaidi@eecs.umich.edu Fault hwrei(); 1785702Ssaidi@eecs.umich.edu 1795702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1805702Ssaidi@eecs.umich.edu 1812683Sktlim@umich.edu#endif 1822SN/A 1832683Sktlim@umich.edu /******************************************* 1842683Sktlim@umich.edu * ThreadContext interface functions. 1852683Sktlim@umich.edu ******************************************/ 1862683Sktlim@umich.edu 1872683Sktlim@umich.edu BaseCPU *getCpuPtr() { return cpu; } 1882683Sktlim@umich.edu 1896022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return itb; } 1902683Sktlim@umich.edu 1916022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return dtb; } 1922683Sktlim@umich.edu 1934997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 1944997Sgblack@eecs.umich.edu 1955803Snate@binkert.org#if FULL_SYSTEM 1962683Sktlim@umich.edu FunctionalPort *getPhysPort() { return physPort; } 1972683Sktlim@umich.edu 1985499Ssaidi@eecs.umich.edu /** Return a virtual port. This port cannot be cached locally in an object. 1995499Ssaidi@eecs.umich.edu * After a CPU switch it may point to the wrong memory object which could 2005499Ssaidi@eecs.umich.edu * mean stale data. 2015499Ssaidi@eecs.umich.edu */ 2025499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return virtPort; } 2032SN/A#endif 2042SN/A 2052683Sktlim@umich.edu Status status() const { return _status; } 2062683Sktlim@umich.edu 2072683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2082683Sktlim@umich.edu 2092683Sktlim@umich.edu /// Set the status to Active. Optional delay indicates number of 2102683Sktlim@umich.edu /// cycles to wait before beginning execution. 2112683Sktlim@umich.edu void activate(int delay = 1); 2122683Sktlim@umich.edu 2132683Sktlim@umich.edu /// Set the status to Suspended. 2142683Sktlim@umich.edu void suspend(); 2152683Sktlim@umich.edu 2162683Sktlim@umich.edu /// Set the status to Halted. 2172683Sktlim@umich.edu void halt(); 2182683Sktlim@umich.edu 2192SN/A virtual bool misspeculating(); 2202SN/A 2212532SN/A Fault instRead(RequestPtr &req) 222716SN/A { 2232378SN/A panic("instRead not implemented"); 2242378SN/A // return funcPhysMem->read(req, inst); 2252423SN/A return NoFault; 226716SN/A } 227716SN/A 2282683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2292190SN/A 2306315Sgblack@eecs.umich.edu void clearArchRegs() 2316315Sgblack@eecs.umich.edu { 2326315Sgblack@eecs.umich.edu regs.clear(); 2336315Sgblack@eecs.umich.edu memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2346315Sgblack@eecs.umich.edu } 2352190SN/A 2362SN/A // 2372SN/A // New accessors for new decoder. 2382SN/A // 2392SN/A uint64_t readIntReg(int reg_idx) 2402SN/A { 2416313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2425082Sgblack@eecs.umich.edu return regs.readIntReg(flatIndex); 2432SN/A } 2442SN/A 2452455SN/A FloatReg readFloatReg(int reg_idx) 2462SN/A { 2476313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2486315Sgblack@eecs.umich.edu return floatRegs.f[flatIndex]; 2492SN/A } 2502SN/A 2512455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2522455SN/A { 2536313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2546315Sgblack@eecs.umich.edu return floatRegs.i[flatIndex]; 2552SN/A } 2562SN/A 2572SN/A void setIntReg(int reg_idx, uint64_t val) 2582SN/A { 2596313Sgblack@eecs.umich.edu int flatIndex = isa.flattenIntIndex(reg_idx); 2605082Sgblack@eecs.umich.edu regs.setIntReg(flatIndex, val); 2612SN/A } 2622SN/A 2632455SN/A void setFloatReg(int reg_idx, FloatReg val) 2642SN/A { 2656313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2666315Sgblack@eecs.umich.edu floatRegs.f[flatIndex] = val; 2672SN/A } 2682SN/A 2692455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 2702455SN/A { 2716313Sgblack@eecs.umich.edu int flatIndex = isa.flattenFloatIndex(reg_idx); 2726315Sgblack@eecs.umich.edu floatRegs.i[flatIndex] = val; 2732SN/A } 2742SN/A 2752SN/A uint64_t readPC() 2762SN/A { 2772525SN/A return regs.readPC(); 2782SN/A } 2792SN/A 2802190SN/A void setPC(uint64_t val) 2812190SN/A { 2822525SN/A regs.setPC(val); 2832190SN/A } 2842190SN/A 2853276Sgblack@eecs.umich.edu uint64_t readMicroPC() 2863276Sgblack@eecs.umich.edu { 2873276Sgblack@eecs.umich.edu return microPC; 2883276Sgblack@eecs.umich.edu } 2893276Sgblack@eecs.umich.edu 2903276Sgblack@eecs.umich.edu void setMicroPC(uint64_t val) 2913276Sgblack@eecs.umich.edu { 2923276Sgblack@eecs.umich.edu microPC = val; 2933276Sgblack@eecs.umich.edu } 2943276Sgblack@eecs.umich.edu 2952190SN/A uint64_t readNextPC() 2962190SN/A { 2972525SN/A return regs.readNextPC(); 2982190SN/A } 2992190SN/A 3002SN/A void setNextPC(uint64_t val) 3012SN/A { 3022525SN/A regs.setNextPC(val); 3032SN/A } 3042SN/A 3053276Sgblack@eecs.umich.edu uint64_t readNextMicroPC() 3063276Sgblack@eecs.umich.edu { 3073276Sgblack@eecs.umich.edu return nextMicroPC; 3083276Sgblack@eecs.umich.edu } 3093276Sgblack@eecs.umich.edu 3103276Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) 3113276Sgblack@eecs.umich.edu { 3123276Sgblack@eecs.umich.edu nextMicroPC = val; 3133276Sgblack@eecs.umich.edu } 3143276Sgblack@eecs.umich.edu 3152252SN/A uint64_t readNextNPC() 3162252SN/A { 3172525SN/A return regs.readNextNPC(); 3182252SN/A } 3192252SN/A 3202251SN/A void setNextNPC(uint64_t val) 3212251SN/A { 3222525SN/A regs.setNextNPC(val); 3232251SN/A } 3242251SN/A 3256221Snate@binkert.org MiscReg 3266221Snate@binkert.org readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) 3274172Ssaidi@eecs.umich.edu { 3286313Sgblack@eecs.umich.edu return isa.readMiscRegNoEffect(misc_reg); 3294172Ssaidi@eecs.umich.edu } 3304172Ssaidi@eecs.umich.edu 3316221Snate@binkert.org MiscReg 3326221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 3332SN/A { 3346313Sgblack@eecs.umich.edu return isa.readMiscReg(misc_reg, tc); 3352SN/A } 3362SN/A 3376221Snate@binkert.org void 3386221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3392SN/A { 3406313Sgblack@eecs.umich.edu return isa.setMiscRegNoEffect(misc_reg, val); 3412SN/A } 3422SN/A 3436221Snate@binkert.org void 3446221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 3452SN/A { 3466313Sgblack@eecs.umich.edu return isa.setMiscReg(misc_reg, val, tc); 3476313Sgblack@eecs.umich.edu } 3486313Sgblack@eecs.umich.edu 3496313Sgblack@eecs.umich.edu int 3506313Sgblack@eecs.umich.edu flattenIntIndex(int reg) 3516313Sgblack@eecs.umich.edu { 3526313Sgblack@eecs.umich.edu return isa.flattenIntIndex(reg); 3536313Sgblack@eecs.umich.edu } 3546313Sgblack@eecs.umich.edu 3556313Sgblack@eecs.umich.edu int 3566313Sgblack@eecs.umich.edu flattenFloatIndex(int reg) 3576313Sgblack@eecs.umich.edu { 3586313Sgblack@eecs.umich.edu return isa.flattenFloatIndex(reg); 3592SN/A } 3602SN/A 3612190SN/A unsigned readStCondFailures() { return storeCondFailures; } 3622190SN/A 3632190SN/A void setStCondFailures(unsigned sc_failures) 3642190SN/A { storeCondFailures = sc_failures; } 3652190SN/A 3661858SN/A#if !FULL_SYSTEM 3672561SN/A void syscall(int64_t callnum) 3682SN/A { 3692680SN/A process->syscall(callnum, tc); 3702SN/A } 3712SN/A#endif 3722SN/A}; 3732SN/A 3742SN/A 3752SN/A// for non-speculative execution context, spec_mode is always false 3762SN/Ainline bool 3772683Sktlim@umich.eduSimpleThread::misspeculating() 3782SN/A{ 3792SN/A return false; 3802SN/A} 3812SN/A 3822190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 383