simple_thread.hh revision 2036
12155SN/A/* 22155SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32155SN/A * All rights reserved. 42155SN/A * 52155SN/A * Redistribution and use in source and binary forms, with or without 62155SN/A * modification, are permitted provided that the following conditions are 72155SN/A * met: redistributions of source code must retain the above copyright 82155SN/A * notice, this list of conditions and the following disclaimer; 92155SN/A * redistributions in binary form must reproduce the above copyright 102155SN/A * notice, this list of conditions and the following disclaimer in the 112155SN/A * documentation and/or other materials provided with the distribution; 122155SN/A * neither the name of the copyright holders nor the names of its 132155SN/A * contributors may be used to endorse or promote products derived from 142155SN/A * this software without specific prior written permission. 152155SN/A * 162155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272155SN/A */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __CPU_EXEC_CONTEXT_HH__ 302155SN/A#define __CPU_EXEC_CONTEXT_HH__ 314202Sbinkertn@umich.edu 322155SN/A#include "config/full_system.hh" 339850Sandreas.hansson@arm.com#include "mem/functional/functional.hh" 349850Sandreas.hansson@arm.com#include "mem/mem_req.hh" 359850Sandreas.hansson@arm.com#include "sim/host.hh" 367768SAli.Saidi@ARM.com#include "sim/serialize.hh" 377768SAli.Saidi@ARM.com#include "sim/byteswap.hh" 382178SN/A 392178SN/A// forward declaration: see functional_memory.hh 402178SN/Aclass FunctionalMemory; 412178SN/Aclass PhysicalMemory; 422178SN/Aclass BaseCPU; 432178SN/A 442178SN/A#if FULL_SYSTEM 452178SN/A 462178SN/A#include "sim/system.hh" 472178SN/A#include "targetarch/alpha_memory.hh" 482178SN/A 492155SN/Aclass FunctionProfile; 505865Sksewell@umich.educlass ProfileNode; 516181Sksewell@umich.educlass MemoryController; 526181Sksewell@umich.edunamespace Kernel { class Binning; class Statistics; } 535865Sksewell@umich.edu 543918Ssaidi@eecs.umich.edu#else // !FULL_SYSTEM 555865Sksewell@umich.edu 562623SN/A#include "sim/process.hh" 573918Ssaidi@eecs.umich.edu 582155SN/A#endif // FULL_SYSTEM 592155SN/A 602292SN/A// 616181Sksewell@umich.edu// The ExecContext object represents a functional context for 626181Sksewell@umich.edu// instruction execution. It incorporates everything required for 633918Ssaidi@eecs.umich.edu// architecture-level functional simulation of a single thread. 642292SN/A// 652292SN/A 662292SN/Aclass ExecContext 673918Ssaidi@eecs.umich.edu{ 682292SN/A public: 692292SN/A enum Status 702766Sktlim@umich.edu { 712766Sktlim@umich.edu /// Initialized but not running yet. All CPUs start in 722766Sktlim@umich.edu /// this state, but most transition to Active on cycle 1. 732921Sktlim@umich.edu /// In MP or SMT systems, non-primary contexts will stay 748887Sgeoffrey.blake@arm.com /// in this state until a thread is assigned to them. 758887Sgeoffrey.blake@arm.com Unallocated, 762766Sktlim@umich.edu 774762Snate@binkert.org /// Running. Instructions should be executed only when 782155SN/A /// the context is in this state. 792155SN/A Active, 802155SN/A 812155SN/A /// Temporarily inactive. Entered while waiting for 822155SN/A /// synchronization, etc. 832155SN/A Suspended, 842766Sktlim@umich.edu 852155SN/A /// Permanently shut down. Entered when target executes 865865Sksewell@umich.edu /// m5exit pseudo-instruction. When all contexts enter 872155SN/A /// this state, the simulation will terminate. 882155SN/A Halted 892155SN/A }; 902155SN/A 912178SN/A private: 922178SN/A Status _status; 937756SAli.Saidi@ARM.com 942766Sktlim@umich.edu public: 952178SN/A Status status() const { return _status; } 962178SN/A 976994Snate@binkert.org /// Set the status to Active. Optional delay indicates number of 982178SN/A /// cycles to wait before beginning execution. 992766Sktlim@umich.edu void activate(int delay = 1); 1002766Sktlim@umich.edu 1012788Sktlim@umich.edu /// Set the status to Suspended. 1022178SN/A void suspend(); 1034486Sbinkertn@umich.edu 1044486Sbinkertn@umich.edu /// Set the status to Unallocated. 1054776Sgblack@eecs.umich.edu void deallocate(); 1064776Sgblack@eecs.umich.edu 1078739Sgblack@eecs.umich.edu /// Set the status to Halted. 1086365Sgblack@eecs.umich.edu void halt(); 1094486Sbinkertn@umich.edu 1104202Sbinkertn@umich.edu public: 1114202Sbinkertn@umich.edu RegFile regs; // correct-path register context 1124202Sbinkertn@umich.edu 1134202Sbinkertn@umich.edu // pointer to CPU associated with this context 1144202Sbinkertn@umich.edu BaseCPU *cpu; 1154776Sgblack@eecs.umich.edu 1168739Sgblack@eecs.umich.edu // Current instruction 1176365Sgblack@eecs.umich.edu MachInst inst; 1184202Sbinkertn@umich.edu 1198777Sgblack@eecs.umich.edu // Index of hardware thread context on the CPU that this represents. 1204202Sbinkertn@umich.edu int thread_num; 1219913Ssteve.reinhardt@amd.com 1224202Sbinkertn@umich.edu // ID of this context w.r.t. the System or Process object to which 1234202Sbinkertn@umich.edu // it belongs. For full-system mode, this is the system CPU ID. 1245217Ssaidi@eecs.umich.edu int cpu_id; 1254202Sbinkertn@umich.edu 1262155SN/A#if FULL_SYSTEM 1278793Sgblack@eecs.umich.edu FunctionalMemory *mem; 1288793Sgblack@eecs.umich.edu AlphaITB *itb; 1298793Sgblack@eecs.umich.edu AlphaDTB *dtb; 1304776Sgblack@eecs.umich.edu System *system; 1318887Sgeoffrey.blake@arm.com 1328887Sgeoffrey.blake@arm.com // the following two fields are redundant, since we can always 1339340SAndreas.Sandberg@arm.com // look them up through the system pointer, but we'll leave them 1348887Sgeoffrey.blake@arm.com // here for now for convenience 1355192Ssaidi@eecs.umich.edu MemoryController *memctrl; 1368335Snate@binkert.org PhysicalMemory *physmem; 1378335Snate@binkert.org 1388335Snate@binkert.org Kernel::Binning *kernelBinning; 1398335Snate@binkert.org Kernel::Statistics *kernelStats; 1408335Snate@binkert.org bool bin; 1419534SAndreas.Sandberg@ARM.com bool fnbin; 1429534SAndreas.Sandberg@ARM.com 1439534SAndreas.Sandberg@ARM.com FunctionProfile *profile; 1448335Snate@binkert.org ProfileNode *profileNode; 1459534SAndreas.Sandberg@ARM.com Addr profilePC; 1469534SAndreas.Sandberg@ARM.com void dumpFuncProfile(); 1478335Snate@binkert.org 1489534SAndreas.Sandberg@ARM.com#else 1499534SAndreas.Sandberg@ARM.com Process *process; 1509534SAndreas.Sandberg@ARM.com 1519534SAndreas.Sandberg@ARM.com FunctionalMemory *mem; // functional storage for process address space 1529534SAndreas.Sandberg@ARM.com 1539534SAndreas.Sandberg@ARM.com // Address space ID. Note that this is used for TIMING cache 1549534SAndreas.Sandberg@ARM.com // simulation only; all functional memory accesses should use 1559534SAndreas.Sandberg@ARM.com // one of the FunctionalMemory pointers above. 1569534SAndreas.Sandberg@ARM.com short asid; 1579534SAndreas.Sandberg@ARM.com 1588335Snate@binkert.org#endif 1598335Snate@binkert.org 1608471SGiacomo.Gabrielli@arm.com /** 1618335Snate@binkert.org * Temporary storage to pass the source address from copy_load to 1628335Snate@binkert.org * copy_store. 1635192Ssaidi@eecs.umich.edu * @todo Remove this temporary when we have a better way to do it. 1648232Snate@binkert.org */ 1658232Snate@binkert.org Addr copySrcAddr; 1668232Snate@binkert.org /** 1678300Schander.sudanthi@arm.com * Temp storage for the physical source address of a copy. 1688300Schander.sudanthi@arm.com * @todo Remove this temporary when we have a better way to do it. 1695192Ssaidi@eecs.umich.edu */ 1708300Schander.sudanthi@arm.com Addr copySrcPhysAddr; 1718300Schander.sudanthi@arm.com 1726036Sksewell@umich.edu 1738300Schander.sudanthi@arm.com /* 1748300Schander.sudanthi@arm.com * number of executed instructions, for matching with syscall trace 175 * points in EIO files. 176 */ 177 Counter func_exe_inst; 178 179 // 180 // Count failed store conditionals so we can warn of apparent 181 // application deadlock situations. 182 unsigned storeCondFailures; 183 184 // constructor: initialize context from given process structure 185#if FULL_SYSTEM 186 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 187 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 188#else 189 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 190 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 191 int _asid); 192#endif 193 virtual ~ExecContext(); 194 195 virtual void takeOverFrom(ExecContext *oldContext); 196 197 void regStats(const std::string &name); 198 199 void serialize(std::ostream &os); 200 void unserialize(Checkpoint *cp, const std::string §ion); 201 202#if FULL_SYSTEM 203 bool validInstAddr(Addr addr) { return true; } 204 bool validDataAddr(Addr addr) { return true; } 205 int getInstAsid() { return regs.instAsid(); } 206 int getDataAsid() { return regs.dataAsid(); } 207 208 Fault translateInstReq(MemReqPtr &req) 209 { 210 return itb->translate(req); 211 } 212 213 Fault translateDataReadReq(MemReqPtr &req) 214 { 215 return dtb->translate(req, false); 216 } 217 218 Fault translateDataWriteReq(MemReqPtr &req) 219 { 220 return dtb->translate(req, true); 221 } 222 223#else 224 bool validInstAddr(Addr addr) 225 { return process->validInstAddr(addr); } 226 227 bool validDataAddr(Addr addr) 228 { return process->validDataAddr(addr); } 229 230 int getInstAsid() { return asid; } 231 int getDataAsid() { return asid; } 232 233 Fault dummyTranslation(MemReqPtr &req) 234 { 235#if 0 236 assert((req->vaddr >> 48 & 0xffff) == 0); 237#endif 238 239 // put the asid in the upper 16 bits of the paddr 240 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 241 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 242 return No_Fault; 243 } 244 Fault translateInstReq(MemReqPtr &req) 245 { 246 return dummyTranslation(req); 247 } 248 Fault translateDataReadReq(MemReqPtr &req) 249 { 250 return dummyTranslation(req); 251 } 252 Fault translateDataWriteReq(MemReqPtr &req) 253 { 254 return dummyTranslation(req); 255 } 256 257#endif 258 259 template <class T> 260 Fault read(MemReqPtr &req, T &data) 261 { 262#if FULL_SYSTEM && defined(TARGET_ALPHA) 263 if (req->flags & LOCKED) { 264 MiscRegFile *cregs = &req->xc->regs.miscRegs; 265 cregs->lock_addr = req->paddr; 266 cregs->lock_flag = true; 267 } 268#endif 269 270 Fault error; 271 error = mem->read(req, data); 272 data = LittleEndianGuest::gtoh(data); 273 return error; 274 } 275 276 template <class T> 277 Fault write(MemReqPtr &req, T &data) 278 { 279#if FULL_SYSTEM && defined(TARGET_ALPHA) 280 281 MiscRegFile *cregs; 282 283 // If this is a store conditional, act appropriately 284 if (req->flags & LOCKED) { 285 cregs = &req->xc->regs.miscRegs; 286 287 if (req->flags & UNCACHEABLE) { 288 // Don't update result register (see stq_c in isa_desc) 289 req->result = 2; 290 req->xc->storeCondFailures = 0;//Needed? [RGD] 291 } else { 292 req->result = cregs->lock_flag; 293 if (!cregs->lock_flag || 294 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 295 cregs->lock_flag = false; 296 if (((++req->xc->storeCondFailures) % 100000) == 0) { 297 std::cerr << "Warning: " 298 << req->xc->storeCondFailures 299 << " consecutive store conditional failures " 300 << "on cpu " << req->xc->cpu_id 301 << std::endl; 302 } 303 return No_Fault; 304 } 305 else req->xc->storeCondFailures = 0; 306 } 307 } 308 309 // Need to clear any locked flags on other proccessors for 310 // this address. Only do this for succsful Store Conditionals 311 // and all other stores (WH64?). Unsuccessful Store 312 // Conditionals would have returned above, and wouldn't fall 313 // through. 314 for (int i = 0; i < system->execContexts.size(); i++){ 315 cregs = &system->execContexts[i]->regs.miscRegs; 316 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 317 cregs->lock_flag = false; 318 } 319 } 320 321#endif 322 return mem->write(req, (T)LittleEndianGuest::htog(data)); 323 } 324 325 virtual bool misspeculating(); 326 327 328 MachInst getInst() { return inst; } 329 330 void setInst(MachInst new_inst) 331 { 332 inst = new_inst; 333 } 334 335 Fault instRead(MemReqPtr &req) 336 { 337 return mem->read(req, inst); 338 } 339 340 // 341 // New accessors for new decoder. 342 // 343 uint64_t readIntReg(int reg_idx) 344 { 345 return regs.intRegFile[reg_idx]; 346 } 347 348 float readFloatRegSingle(int reg_idx) 349 { 350 return (float)regs.floatRegFile.d[reg_idx]; 351 } 352 353 double readFloatRegDouble(int reg_idx) 354 { 355 return regs.floatRegFile.d[reg_idx]; 356 } 357 358 uint64_t readFloatRegInt(int reg_idx) 359 { 360 return regs.floatRegFile.q[reg_idx]; 361 } 362 363 void setIntReg(int reg_idx, uint64_t val) 364 { 365 regs.intRegFile[reg_idx] = val; 366 } 367 368 void setFloatRegSingle(int reg_idx, float val) 369 { 370 regs.floatRegFile.d[reg_idx] = (double)val; 371 } 372 373 void setFloatRegDouble(int reg_idx, double val) 374 { 375 regs.floatRegFile.d[reg_idx] = val; 376 } 377 378 void setFloatRegInt(int reg_idx, uint64_t val) 379 { 380 regs.floatRegFile.q[reg_idx] = val; 381 } 382 383 uint64_t readPC() 384 { 385 return regs.pc; 386 } 387 388 void setNextPC(uint64_t val) 389 { 390 regs.npc = val; 391 } 392 393 uint64_t readUniq() 394 { 395 return regs.miscRegs.uniq; 396 } 397 398 void setUniq(uint64_t val) 399 { 400 regs.miscRegs.uniq = val; 401 } 402 403 uint64_t readFpcr() 404 { 405 return regs.miscRegs.fpcr; 406 } 407 408 void setFpcr(uint64_t val) 409 { 410 regs.miscRegs.fpcr = val; 411 } 412 413#if FULL_SYSTEM 414 uint64_t readIpr(int idx, Fault &fault); 415 Fault setIpr(int idx, uint64_t val); 416 int readIntrFlag() { return regs.intrflag; } 417 void setIntrFlag(int val) { regs.intrflag = val; } 418 Fault hwrei(); 419 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 420 void ev5_trap(Fault fault); 421 bool simPalCheck(int palFunc); 422#endif 423 424 /** Meant to be more generic trap function to be 425 * called when an instruction faults. 426 * @param fault The fault generated by executing the instruction. 427 * @todo How to do this properly so it's dependent upon ISA only? 428 */ 429 430 void trap(Fault fault); 431 432#if !FULL_SYSTEM 433 IntReg getSyscallArg(int i) 434 { 435 return regs.intRegFile[ArgumentReg0 + i]; 436 } 437 438 // used to shift args for indirect syscall 439 void setSyscallArg(int i, IntReg val) 440 { 441 regs.intRegFile[ArgumentReg0 + i] = val; 442 } 443 444 void setSyscallReturn(SyscallReturn return_value) 445 { 446 // check for error condition. Alpha syscall convention is to 447 // indicate success/failure in reg a3 (r19) and put the 448 // return value itself in the standard return value reg (v0). 449 const int RegA3 = 19; // only place this is used 450 if (return_value.successful()) { 451 // no error 452 regs.intRegFile[RegA3] = 0; 453 regs.intRegFile[ReturnValueReg] = return_value.value(); 454 } else { 455 // got an error, return details 456 regs.intRegFile[RegA3] = (IntReg) -1; 457 regs.intRegFile[ReturnValueReg] = -return_value.value(); 458 } 459 } 460 461 void syscall() 462 { 463 process->syscall(this); 464 } 465#endif 466}; 467 468 469// for non-speculative execution context, spec_mode is always false 470inline bool 471ExecContext::misspeculating() 472{ 473 return false; 474} 475 476#endif // __CPU_EXEC_CONTEXT_HH__ 477