simple_thread.hh revision 1450
12810Srdreslin@umich.edu/* 29529Sandreas.hansson@arm.com * Copyright (c) 2001-2004 The Regents of The University of Michigan 38702Sandreas.hansson@arm.com * All rights reserved. 48702Sandreas.hansson@arm.com * 58702Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68702Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78702Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88702Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98702Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108702Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118702Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128702Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138702Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu */ 282810Srdreslin@umich.edu 292810Srdreslin@umich.edu#ifndef __EXEC_CONTEXT_HH__ 302810Srdreslin@umich.edu#define __EXEC_CONTEXT_HH__ 312810Srdreslin@umich.edu 322810Srdreslin@umich.edu#include "sim/host.hh" 332810Srdreslin@umich.edu#include "mem/mem_req.hh" 342810Srdreslin@umich.edu#include "mem/functional_mem/functional_memory.hh" 352810Srdreslin@umich.edu#include "sim/serialize.hh" 362810Srdreslin@umich.edu#include "targetarch/byte_swap.hh" 372810Srdreslin@umich.edu 382810Srdreslin@umich.edu// forward declaration: see functional_memory.hh 392810Srdreslin@umich.educlass FunctionalMemory; 402810Srdreslin@umich.educlass PhysicalMemory; 412810Srdreslin@umich.educlass BaseCPU; 422810Srdreslin@umich.edu 434458Sstever@eecs.umich.edu#ifdef FULL_SYSTEM 448856Sandreas.hansson@arm.com 452810Srdreslin@umich.edu#include "sim/system.hh" 462810Srdreslin@umich.edu#include "targetarch/alpha_memory.hh" 472810Srdreslin@umich.edu 482810Srdreslin@umich.educlass MemoryController; 492810Srdreslin@umich.educlass StaticInstBase; 502810Srdreslin@umich.edunamespace Kernel { class Binning; class Statistics; } 512810Srdreslin@umich.edu 522810Srdreslin@umich.edu#else // !FULL_SYSTEM 532810Srdreslin@umich.edu 542810Srdreslin@umich.edu#include "sim/process.hh" 552810Srdreslin@umich.edu 565338Sstever@gmail.com#endif // FULL_SYSTEM 575338Sstever@gmail.com 585338Sstever@gmail.com// 594458Sstever@eecs.umich.edu// The ExecContext object represents a functional context for 604458Sstever@eecs.umich.edu// instruction execution. It incorporates everything required for 612813Srdreslin@umich.edu// architecture-level functional simulation of a single thread. 623861Sstever@eecs.umich.edu// 632810Srdreslin@umich.edu 642810Srdreslin@umich.educlass ExecContext 652810Srdreslin@umich.edu{ 662810Srdreslin@umich.edu public: 679264Sdjordje.kovacevic@arm.com enum Status 682810Srdreslin@umich.edu { 694672Sstever@eecs.umich.edu /// Initialized but not running yet. All CPUs start in 702810Srdreslin@umich.edu /// this state, but most transition to Active on cycle 1. 712810Srdreslin@umich.edu /// In MP or SMT systems, non-primary contexts will stay 722810Srdreslin@umich.edu /// in this state until a thread is assigned to them. 732810Srdreslin@umich.edu Unallocated, 742810Srdreslin@umich.edu 753860Sstever@eecs.umich.edu /// Running. Instructions should be executed only when 763860Sstever@eecs.umich.edu /// the context is in this state. 772810Srdreslin@umich.edu Active, 782810Srdreslin@umich.edu 799347SAndreas.Sandberg@arm.com /// Temporarily inactive. Entered while waiting for 802810Srdreslin@umich.edu /// synchronization, etc. 818856Sandreas.hansson@arm.com Suspended, 828856Sandreas.hansson@arm.com 838856Sandreas.hansson@arm.com /// Permanently shut down. Entered when target executes 848856Sandreas.hansson@arm.com /// m5exit pseudo-instruction. When all contexts enter 858856Sandreas.hansson@arm.com /// this state, the simulation will terminate. 863738Sstever@eecs.umich.edu Halted 878856Sandreas.hansson@arm.com }; 883738Sstever@eecs.umich.edu 898856Sandreas.hansson@arm.com private: 908856Sandreas.hansson@arm.com Status _status; 913738Sstever@eecs.umich.edu 928856Sandreas.hansson@arm.com public: 934478Sstever@eecs.umich.edu Status status() const { return _status; } 948975Sandreas.hansson@arm.com 958948Sandreas.hansson@arm.com /// Set the status to Active. Optional delay indicates number of 968975Sandreas.hansson@arm.com /// cycles to wait before beginning execution. 973738Sstever@eecs.umich.edu void activate(int delay = 1); 983738Sstever@eecs.umich.edu 993738Sstever@eecs.umich.edu /// Set the status to Suspended. 1003738Sstever@eecs.umich.edu void suspend(); 1018856Sandreas.hansson@arm.com 1029090Sandreas.hansson@arm.com /// Set the status to Unallocated. 1038856Sandreas.hansson@arm.com void deallocate(); 1048856Sandreas.hansson@arm.com 1058856Sandreas.hansson@arm.com /// Set the status to Halted. 1068856Sandreas.hansson@arm.com void halt(); 1078856Sandreas.hansson@arm.com 1088856Sandreas.hansson@arm.com public: 1093738Sstever@eecs.umich.edu RegFile regs; // correct-path register context 1103738Sstever@eecs.umich.edu 1118856Sandreas.hansson@arm.com // pointer to CPU associated with this context 1128914Sandreas.hansson@arm.com BaseCPU *cpu; 1138914Sandreas.hansson@arm.com 1148914Sandreas.hansson@arm.com // Current instruction 1158914Sandreas.hansson@arm.com MachInst inst; 1168914Sandreas.hansson@arm.com 1178975Sandreas.hansson@arm.com // Index of hardware thread context on the CPU that this represents. 1188914Sandreas.hansson@arm.com int thread_num; 1198914Sandreas.hansson@arm.com 1208914Sandreas.hansson@arm.com // ID of this context w.r.t. the System or Process object to which 1218914Sandreas.hansson@arm.com // it belongs. For full-system mode, this is the system CPU ID. 1228914Sandreas.hansson@arm.com int cpu_id; 1238914Sandreas.hansson@arm.com 1248914Sandreas.hansson@arm.com#ifdef FULL_SYSTEM 1258914Sandreas.hansson@arm.com FunctionalMemory *mem; 1268975Sandreas.hansson@arm.com AlphaITB *itb; 1278914Sandreas.hansson@arm.com AlphaDTB *dtb; 1288975Sandreas.hansson@arm.com System *system; 1298914Sandreas.hansson@arm.com 1308914Sandreas.hansson@arm.com // the following two fields are redundant, since we can always 1318914Sandreas.hansson@arm.com // look them up through the system pointer, but we'll leave them 1328914Sandreas.hansson@arm.com // here for now for convenience 1338914Sandreas.hansson@arm.com MemoryController *memctrl; 1348914Sandreas.hansson@arm.com PhysicalMemory *physmem; 1358914Sandreas.hansson@arm.com 1368914Sandreas.hansson@arm.com Kernel::Binning *kernelBinning; 1378914Sandreas.hansson@arm.com Kernel::Statistics *kernelStats; 1388914Sandreas.hansson@arm.com bool bin; 1398914Sandreas.hansson@arm.com bool fnbin; 1408856Sandreas.hansson@arm.com void execute(const StaticInstBase *inst); 1418856Sandreas.hansson@arm.com 1428856Sandreas.hansson@arm.com#else 1438856Sandreas.hansson@arm.com Process *process; 1443738Sstever@eecs.umich.edu 1458856Sandreas.hansson@arm.com FunctionalMemory *mem; // functional storage for process address space 1463738Sstever@eecs.umich.edu 1478914Sandreas.hansson@arm.com // Address space ID. Note that this is used for TIMING cache 1488914Sandreas.hansson@arm.com // simulation only; all functional memory accesses should use 1498914Sandreas.hansson@arm.com // one of the FunctionalMemory pointers above. 1508856Sandreas.hansson@arm.com short asid; 1518856Sandreas.hansson@arm.com 1523738Sstever@eecs.umich.edu#endif 1538856Sandreas.hansson@arm.com 1544478Sstever@eecs.umich.edu /** 1558975Sandreas.hansson@arm.com * Temporary storage to pass the source address from copy_load to 1568948Sandreas.hansson@arm.com * copy_store. 1578975Sandreas.hansson@arm.com * @todo Remove this temporary when we have a better way to do it. 1583738Sstever@eecs.umich.edu */ 1598948Sandreas.hansson@arm.com Addr copySrcAddr; 1603738Sstever@eecs.umich.edu /** 1618948Sandreas.hansson@arm.com * Temp storage for the physical source address of a copy. 1624458Sstever@eecs.umich.edu * @todo Remove this temporary when we have a better way to do it. 1638856Sandreas.hansson@arm.com */ 1648856Sandreas.hansson@arm.com Addr copySrcPhysAddr; 1658856Sandreas.hansson@arm.com 1668856Sandreas.hansson@arm.com 1673738Sstever@eecs.umich.edu /* 1683738Sstever@eecs.umich.edu * number of executed instructions, for matching with syscall trace 1692810Srdreslin@umich.edu * points in EIO files. 1702810Srdreslin@umich.edu */ 1714626Sstever@eecs.umich.edu Counter func_exe_inst; 1722810Srdreslin@umich.edu 1733861Sstever@eecs.umich.edu // 1742810Srdreslin@umich.edu // Count failed store conditionals so we can warn of apparent 1754671Sstever@eecs.umich.edu // application deadlock situations. 1764671Sstever@eecs.umich.edu unsigned storeCondFailures; 1774671Sstever@eecs.umich.edu 1782810Srdreslin@umich.edu // constructor: initialize context from given process structure 1795707Shsul@eecs.umich.edu#ifdef FULL_SYSTEM 1803860Sstever@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 1813860Sstever@eecs.umich.edu AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem); 1823860Sstever@eecs.umich.edu#else 1835875Ssteve.reinhardt@amd.com ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 1845875Ssteve.reinhardt@amd.com ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 1855875Ssteve.reinhardt@amd.com int _asid); 1865875Ssteve.reinhardt@amd.com#endif 1873860Sstever@eecs.umich.edu virtual ~ExecContext(); 1883860Sstever@eecs.umich.edu 1899063SAli.Saidi@ARM.com virtual void takeOverFrom(ExecContext *oldContext); 1909063SAli.Saidi@ARM.com 1919063SAli.Saidi@ARM.com void regStats(const std::string &name); 1929063SAli.Saidi@ARM.com 1939063SAli.Saidi@ARM.com void serialize(std::ostream &os); 1949063SAli.Saidi@ARM.com void unserialize(Checkpoint *cp, const std::string §ion); 1959063SAli.Saidi@ARM.com 1963860Sstever@eecs.umich.edu#ifdef FULL_SYSTEM 1973860Sstever@eecs.umich.edu bool validInstAddr(Addr addr) { return true; } 19810048Saminfar@gmail.com bool validDataAddr(Addr addr) { return true; } 1993860Sstever@eecs.umich.edu int getInstAsid() { return regs.instAsid(); } 2003860Sstever@eecs.umich.edu int getDataAsid() { return regs.dataAsid(); } 2015707Shsul@eecs.umich.edu 2023860Sstever@eecs.umich.edu Fault translateInstReq(MemReqPtr &req) 2035388Sstever@gmail.com { 2049288Sandreas.hansson@arm.com return itb->translate(req); 2054219Srdreslin@umich.edu } 2064219Srdreslin@umich.edu 2074219Srdreslin@umich.edu Fault translateDataReadReq(MemReqPtr &req) 2084219Srdreslin@umich.edu { 2094626Sstever@eecs.umich.edu return dtb->translate(req, false); 2103860Sstever@eecs.umich.edu } 2113860Sstever@eecs.umich.edu 21210028SGiacomo.Gabrielli@arm.com Fault translateDataWriteReq(MemReqPtr &req) 21310028SGiacomo.Gabrielli@arm.com { 21410028SGiacomo.Gabrielli@arm.com return dtb->translate(req, true); 21510028SGiacomo.Gabrielli@arm.com } 21610028SGiacomo.Gabrielli@arm.com 2175350Sstever@gmail.com#else 21810028SGiacomo.Gabrielli@arm.com bool validInstAddr(Addr addr) 2195350Sstever@gmail.com { return process->validInstAddr(addr); } 2205350Sstever@gmail.com 2213860Sstever@eecs.umich.edu bool validDataAddr(Addr addr) 2223860Sstever@eecs.umich.edu { return process->validDataAddr(addr); } 2233860Sstever@eecs.umich.edu 2244626Sstever@eecs.umich.edu int getInstAsid() { return asid; } 2253860Sstever@eecs.umich.edu int getDataAsid() { return asid; } 2263860Sstever@eecs.umich.edu 2273860Sstever@eecs.umich.edu Fault dummyTranslation(MemReqPtr &req) 2283860Sstever@eecs.umich.edu { 2294626Sstever@eecs.umich.edu#if 0 2304626Sstever@eecs.umich.edu assert((req->vaddr >> 48 & 0xffff) == 0); 2313860Sstever@eecs.umich.edu#endif 2329548Sandreas.hansson@arm.com 2339548Sandreas.hansson@arm.com // put the asid in the upper 16 bits of the paddr 2349548Sandreas.hansson@arm.com req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 2359548Sandreas.hansson@arm.com req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 2369548Sandreas.hansson@arm.com return No_Fault; 2379548Sandreas.hansson@arm.com } 2389548Sandreas.hansson@arm.com Fault translateInstReq(MemReqPtr &req) 2399548Sandreas.hansson@arm.com { 2409548Sandreas.hansson@arm.com return dummyTranslation(req); 2419548Sandreas.hansson@arm.com } 2429548Sandreas.hansson@arm.com Fault translateDataReadReq(MemReqPtr &req) 2439548Sandreas.hansson@arm.com { 2449548Sandreas.hansson@arm.com return dummyTranslation(req); 2459548Sandreas.hansson@arm.com } 2469548Sandreas.hansson@arm.com Fault translateDataWriteReq(MemReqPtr &req) 2479548Sandreas.hansson@arm.com { 2489548Sandreas.hansson@arm.com return dummyTranslation(req); 2499548Sandreas.hansson@arm.com } 2509548Sandreas.hansson@arm.com 2519548Sandreas.hansson@arm.com#endif 2529548Sandreas.hansson@arm.com 2539548Sandreas.hansson@arm.com template <class T> 2549548Sandreas.hansson@arm.com Fault read(MemReqPtr &req, T &data) 2559548Sandreas.hansson@arm.com { 2569548Sandreas.hansson@arm.com#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 2579548Sandreas.hansson@arm.com if (req->flags & LOCKED) { 2589548Sandreas.hansson@arm.com MiscRegFile *cregs = &req->xc->regs.miscRegs; 2599548Sandreas.hansson@arm.com cregs->lock_addr = req->paddr; 2609548Sandreas.hansson@arm.com cregs->lock_flag = true; 2619782Sandreas.hansson@arm.com } 2629548Sandreas.hansson@arm.com#endif 2639782Sandreas.hansson@arm.com 2649548Sandreas.hansson@arm.com Fault error; 2659548Sandreas.hansson@arm.com error = mem->read(req, data); 2669548Sandreas.hansson@arm.com data = htoa(data); 2679782Sandreas.hansson@arm.com return error; 2689548Sandreas.hansson@arm.com } 2699782Sandreas.hansson@arm.com 2709548Sandreas.hansson@arm.com template <class T> 2719782Sandreas.hansson@arm.com Fault write(MemReqPtr &req, T &data) 2729548Sandreas.hansson@arm.com { 2739548Sandreas.hansson@arm.com#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 2749548Sandreas.hansson@arm.com 2759548Sandreas.hansson@arm.com MiscRegFile *cregs; 2769548Sandreas.hansson@arm.com 2779548Sandreas.hansson@arm.com // If this is a store conditional, act appropriately 2789548Sandreas.hansson@arm.com if (req->flags & LOCKED) { 2799548Sandreas.hansson@arm.com cregs = &req->xc->regs.miscRegs; 2807667Ssteve.reinhardt@amd.com 2817667Ssteve.reinhardt@amd.com if (req->flags & UNCACHEABLE) { 2827667Ssteve.reinhardt@amd.com // Don't update result register (see stq_c in isa_desc) 2834628Sstever@eecs.umich.edu req->result = 2; 2844626Sstever@eecs.umich.edu req->xc->storeCondFailures = 0;//Needed? [RGD] 2854670Sstever@eecs.umich.edu } else { 2865319Sstever@gmail.com req->result = cregs->lock_flag; 2873860Sstever@eecs.umich.edu if (!cregs->lock_flag || 2883860Sstever@eecs.umich.edu ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 2893860Sstever@eecs.umich.edu cregs->lock_flag = false; 2903860Sstever@eecs.umich.edu if (((++req->xc->storeCondFailures) % 100000) == 0) { 2913860Sstever@eecs.umich.edu std::cerr << "Warning: " 2923860Sstever@eecs.umich.edu << req->xc->storeCondFailures 2934670Sstever@eecs.umich.edu << " consecutive store conditional failures " 2945319Sstever@gmail.com << "on cpu " << req->xc->cpu_id 2953860Sstever@eecs.umich.edu << std::endl; 2963860Sstever@eecs.umich.edu } 2973860Sstever@eecs.umich.edu return No_Fault; 2983860Sstever@eecs.umich.edu } 2993860Sstever@eecs.umich.edu else req->xc->storeCondFailures = 0; 3003860Sstever@eecs.umich.edu } 3013860Sstever@eecs.umich.edu } 3023860Sstever@eecs.umich.edu 3039347SAndreas.Sandberg@arm.com // Need to clear any locked flags on other proccessors for 3049347SAndreas.Sandberg@arm.com // this address. Only do this for succsful Store Conditionals 3059347SAndreas.Sandberg@arm.com // and all other stores (WH64?). Unsuccessful Store 3069347SAndreas.Sandberg@arm.com // Conditionals would have returned above, and wouldn't fall 3079347SAndreas.Sandberg@arm.com // through. 3089347SAndreas.Sandberg@arm.com for (int i = 0; i < system->execContexts.size(); i++){ 3099347SAndreas.Sandberg@arm.com cregs = &system->execContexts[i]->regs.miscRegs; 3109347SAndreas.Sandberg@arm.com if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 3119347SAndreas.Sandberg@arm.com cregs->lock_flag = false; 3129347SAndreas.Sandberg@arm.com } 3139347SAndreas.Sandberg@arm.com } 3149347SAndreas.Sandberg@arm.com 3159347SAndreas.Sandberg@arm.com#endif 3169347SAndreas.Sandberg@arm.com return mem->write(req, (T)htoa(data)); 3179347SAndreas.Sandberg@arm.com } 3189347SAndreas.Sandberg@arm.com 3199347SAndreas.Sandberg@arm.com virtual bool misspeculating(); 3209347SAndreas.Sandberg@arm.com 3219347SAndreas.Sandberg@arm.com 3229347SAndreas.Sandberg@arm.com MachInst getInst() { return inst; } 3239347SAndreas.Sandberg@arm.com 3249445SAndreas.Sandberg@ARM.com void setInst(MachInst new_inst) 3259445SAndreas.Sandberg@ARM.com { 3269445SAndreas.Sandberg@ARM.com inst = new_inst; 3279445SAndreas.Sandberg@ARM.com } 3289445SAndreas.Sandberg@ARM.com 3299445SAndreas.Sandberg@ARM.com Fault instRead(MemReqPtr &req) 3309445SAndreas.Sandberg@ARM.com { 3319445SAndreas.Sandberg@ARM.com return mem->read(req, inst); 3329445SAndreas.Sandberg@ARM.com } 3339445SAndreas.Sandberg@ARM.com 3349445SAndreas.Sandberg@ARM.com // 3359445SAndreas.Sandberg@ARM.com // New accessors for new decoder. 3362810Srdreslin@umich.edu // 3372982Sstever@eecs.umich.edu uint64_t readIntReg(int reg_idx) 3382810Srdreslin@umich.edu { 3392982Sstever@eecs.umich.edu return regs.intRegFile[reg_idx]; 3402810Srdreslin@umich.edu } 3414626Sstever@eecs.umich.edu 3424626Sstever@eecs.umich.edu float readFloatRegSingle(int reg_idx) 3434626Sstever@eecs.umich.edu { 3445365Sstever@gmail.com return (float)regs.floatRegFile.d[reg_idx]; 3455365Sstever@gmail.com } 3465365Sstever@gmail.com 3475365Sstever@gmail.com double readFloatRegDouble(int reg_idx) 3485365Sstever@gmail.com { 3495365Sstever@gmail.com return regs.floatRegFile.d[reg_idx]; 3505365Sstever@gmail.com } 3515365Sstever@gmail.com 3525365Sstever@gmail.com uint64_t readFloatRegInt(int reg_idx) 3534626Sstever@eecs.umich.edu { 3544628Sstever@eecs.umich.edu return regs.floatRegFile.q[reg_idx]; 3559529Sandreas.hansson@arm.com } 3565365Sstever@gmail.com 3575365Sstever@gmail.com void setIntReg(int reg_idx, uint64_t val) 3585365Sstever@gmail.com { 3595365Sstever@gmail.com regs.intRegFile[reg_idx] = val; 3605365Sstever@gmail.com } 3615365Sstever@gmail.com 3625365Sstever@gmail.com void setFloatRegSingle(int reg_idx, float val) 3634626Sstever@eecs.umich.edu { 3645365Sstever@gmail.com regs.floatRegFile.d[reg_idx] = (double)val; 3655365Sstever@gmail.com } 3665365Sstever@gmail.com 3675365Sstever@gmail.com void setFloatRegDouble(int reg_idx, double val) 3685365Sstever@gmail.com { 3695365Sstever@gmail.com regs.floatRegFile.d[reg_idx] = val; 3704628Sstever@eecs.umich.edu } 3714626Sstever@eecs.umich.edu 3724626Sstever@eecs.umich.edu void setFloatRegInt(int reg_idx, uint64_t val) 3734626Sstever@eecs.umich.edu { 3744626Sstever@eecs.umich.edu regs.floatRegFile.q[reg_idx] = val; 3754626Sstever@eecs.umich.edu } 3764626Sstever@eecs.umich.edu 3774626Sstever@eecs.umich.edu uint64_t readPC() 3787667Ssteve.reinhardt@amd.com { 3794626Sstever@eecs.umich.edu return regs.pc; 3804626Sstever@eecs.umich.edu } 3814626Sstever@eecs.umich.edu 3824626Sstever@eecs.umich.edu void setNextPC(uint64_t val) 3834626Sstever@eecs.umich.edu { 3842810Srdreslin@umich.edu regs.npc = val; 3854626Sstever@eecs.umich.edu } 3862810Srdreslin@umich.edu 3872810Srdreslin@umich.edu uint64_t readUniq() 38810028SGiacomo.Gabrielli@arm.com { 38910028SGiacomo.Gabrielli@arm.com return regs.miscRegs.uniq; 3902810Srdreslin@umich.edu } 3912810Srdreslin@umich.edu 39210028SGiacomo.Gabrielli@arm.com void setUniq(uint64_t val) 39310028SGiacomo.Gabrielli@arm.com { 3943861Sstever@eecs.umich.edu regs.miscRegs.uniq = val; 3953861Sstever@eecs.umich.edu } 39610028SGiacomo.Gabrielli@arm.com 39710028SGiacomo.Gabrielli@arm.com uint64_t readFpcr() 3983861Sstever@eecs.umich.edu { 3995875Ssteve.reinhardt@amd.com return regs.miscRegs.fpcr; 4005875Ssteve.reinhardt@amd.com } 4015875Ssteve.reinhardt@amd.com 4025875Ssteve.reinhardt@amd.com void setFpcr(uint64_t val) 4039529Sandreas.hansson@arm.com { 4049529Sandreas.hansson@arm.com regs.miscRegs.fpcr = val; 4059529Sandreas.hansson@arm.com } 4069529Sandreas.hansson@arm.com 4079796Sprakash.ramrakhyani@arm.com#ifdef FULL_SYSTEM 4089529Sandreas.hansson@arm.com uint64_t readIpr(int idx, Fault &fault); 4099813Srioshering@gmail.com Fault setIpr(int idx, uint64_t val); 4109813Srioshering@gmail.com int readIntrFlag() { return regs.intrflag; } 4119813Srioshering@gmail.com void setIntrFlag(int val) { regs.intrflag = val; } 4129529Sandreas.hansson@arm.com Fault hwrei(); 4138985SAli.Saidi@ARM.com bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } 4148985SAli.Saidi@ARM.com void ev5_trap(Fault fault); 4158985SAli.Saidi@ARM.com bool simPalCheck(int palFunc); 4168985SAli.Saidi@ARM.com#endif 4178985SAli.Saidi@ARM.com 4188985SAli.Saidi@ARM.com /** Meant to be more generic trap function to be 4192810Srdreslin@umich.edu * called when an instruction faults. 4202810Srdreslin@umich.edu * @param fault The fault generated by executing the instruction. 4212810Srdreslin@umich.edu * @todo How to do this properly so it's dependent upon ISA only? 422 */ 423 424 void trap(Fault fault); 425 426#ifndef FULL_SYSTEM 427 IntReg getSyscallArg(int i) 428 { 429 return regs.intRegFile[ArgumentReg0 + i]; 430 } 431 432 // used to shift args for indirect syscall 433 void setSyscallArg(int i, IntReg val) 434 { 435 regs.intRegFile[ArgumentReg0 + i] = val; 436 } 437 438 void setSyscallReturn(SyscallReturn return_value) 439 { 440 // check for error condition. Alpha syscall convention is to 441 // indicate success/failure in reg a3 (r19) and put the 442 // return value itself in the standard return value reg (v0). 443 const int RegA3 = 19; // only place this is used 444 if (return_value.successful()) { 445 // no error 446 regs.intRegFile[RegA3] = 0; 447 regs.intRegFile[ReturnValueReg] = return_value.value(); 448 } else { 449 // got an error, return details 450 regs.intRegFile[RegA3] = (IntReg) -1; 451 regs.intRegFile[ReturnValueReg] = -return_value.value(); 452 } 453 } 454 455 void syscall() 456 { 457 process->syscall(this); 458 } 459#endif 460}; 461 462 463// for non-speculative execution context, spec_mode is always false 464inline bool 465ExecContext::misspeculating() 466{ 467 return false; 468} 469 470#endif // __EXEC_CONTEXT_HH__ 471