simple_thread.hh revision 13610
12SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 4912406Sgabeblack@google.com#include "arch/generic/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/isa.hh" 512190SN/A#include "arch/isa_traits.hh" 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 6113610Sgiacomo.gabrielli@arm.com#include "debug/VecPredRegs.hh" 6212109SRekai.GonzalezAlberquilla@arm.com#include "debug/VecRegs.hh" 638777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 642395SN/A#include "mem/request.hh" 652190SN/A#include "sim/byteswap.hh" 662188SN/A#include "sim/eventq.hh" 678777Sgblack@eecs.umich.edu#include "sim/process.hh" 68217SN/A#include "sim/serialize.hh" 698777Sgblack@eecs.umich.edu#include "sim/system.hh" 702SN/A 712SN/Aclass BaseCPU; 728887Sgeoffrey.blake@arm.comclass CheckerCPU; 731070SN/A 741917SN/Aclass FunctionProfile; 751917SN/Aclass ProfileNode; 762521SN/A 773548Sgblack@eecs.umich.edunamespace TheISA { 783548Sgblack@eecs.umich.edu namespace Kernel { 793548Sgblack@eecs.umich.edu class Statistics; 808902Sandreas.hansson@arm.com } 818902Sandreas.hansson@arm.com} 822330SN/A 832683Sktlim@umich.edu/** 842683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 852683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 862683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 872683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 882683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 892683Sktlim@umich.edu * the objects needed for simple functional execution, including a 902683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 912683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 922683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 932683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 942683Sktlim@umich.edu * all the necessary state for full architecture-level functional 952683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 962683Sktlim@umich.edu * examples. 972683Sktlim@umich.edu */ 982SN/A 992683Sktlim@umich.educlass SimpleThread : public ThreadState 1002SN/A{ 1012107SN/A protected: 1022107SN/A typedef TheISA::MachInst MachInst; 1039920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 10412109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10512109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10613610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 1072SN/A public: 1082680SN/A typedef ThreadContext::Status Status; 1092SN/A 1102190SN/A protected: 11113557Sgabeblack@google.com RegVal floatRegs[TheISA::NumFloatRegs]; 11213557Sgabeblack@google.com RegVal intRegs[TheISA::NumIntRegs]; 11312109SRekai.GonzalezAlberquilla@arm.com VecRegContainer vecRegs[TheISA::NumVecRegs]; 11413610Sgiacomo.gabrielli@arm.com VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 1159920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1169920Syasuko.eckert@amd.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1179920Syasuko.eckert@amd.com#endif 1189384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1192SN/A 1207720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1216324Sgblack@eecs.umich.edu 1227597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1237597Sminkyu.jeong@arm.com bool predicate; 1247597Sminkyu.jeong@arm.com 1252190SN/A public: 1268357Sksewell@umich.edu std::string name() const 1278357Sksewell@umich.edu { 1288735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1298357Sksewell@umich.edu } 1308357Sksewell@umich.edu 1312683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1322188SN/A 1332378SN/A System *system; 1342400SN/A 13512406Sgabeblack@google.com BaseTLB *itb; 13612406Sgabeblack@google.com BaseTLB *dtb; 1372SN/A 1389020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1398541Sgblack@eecs.umich.edu 1402683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1418793Sgblack@eecs.umich.edu // FS 1422683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14312406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1442683Sktlim@umich.edu bool use_kernel_stats = true); 1458793Sgblack@eecs.umich.edu // SE 1468820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14712406Sgabeblack@google.com Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1489384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1492862Sktlim@umich.edu 1502683Sktlim@umich.edu virtual ~SimpleThread(); 1512SN/A 1522680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 153180SN/A 1542SN/A void regStats(const std::string &name); 1552SN/A 1562862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1572862Sktlim@umich.edu 15811168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15911168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1609461Snilay@cs.wisc.edu void startup(); 161217SN/A 1622683Sktlim@umich.edu /*************************************************************** 1632683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1645891Sgblack@eecs.umich.edu * state. 1652683Sktlim@umich.edu **************************************************************/ 1662190SN/A 1672683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1682683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1692683Sktlim@umich.edu * CPU. 1702683Sktlim@umich.edu */ 1712680SN/A ThreadContext *getTC() { return tc; } 1722190SN/A 1735358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1745358Sgblack@eecs.umich.edu { 1755358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1765358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1775358Sgblack@eecs.umich.edu } 1785358Sgblack@eecs.umich.edu 1795358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1805358Sgblack@eecs.umich.edu { 1815358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu } 1835358Sgblack@eecs.umich.edu 1845358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1855358Sgblack@eecs.umich.edu { 1865358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1875358Sgblack@eecs.umich.edu } 1885358Sgblack@eecs.umich.edu 1892683Sktlim@umich.edu void dumpFuncProfile(); 1902521SN/A 1915702Ssaidi@eecs.umich.edu Fault hwrei(); 1925702Ssaidi@eecs.umich.edu 1935702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1945702Ssaidi@eecs.umich.edu 1952683Sktlim@umich.edu /******************************************* 1962683Sktlim@umich.edu * ThreadContext interface functions. 1972683Sktlim@umich.edu ******************************************/ 1982683Sktlim@umich.edu 1998735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 2002683Sktlim@umich.edu 20112406Sgabeblack@google.com BaseTLB *getITBPtr() { return itb; } 2022683Sktlim@umich.edu 20312406Sgabeblack@google.com BaseTLB *getDTBPtr() { return dtb; } 2042683Sktlim@umich.edu 2058887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2068733Sgeoffrey.blake@arm.com 2079020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2088541Sgblack@eecs.umich.edu 2094997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2104997Sgblack@eecs.umich.edu 2112683Sktlim@umich.edu Status status() const { return _status; } 2122683Sktlim@umich.edu 2132683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2142683Sktlim@umich.edu 21510407Smitch.hayenga@arm.com /// Set the status to Active. 21610407Smitch.hayenga@arm.com void activate(); 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu /// Set the status to Suspended. 2192683Sktlim@umich.edu void suspend(); 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu /// Set the status to Halted. 2222683Sktlim@umich.edu void halt(); 2232683Sktlim@umich.edu 2242683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2252190SN/A 2266315Sgblack@eecs.umich.edu void clearArchRegs() 2276315Sgblack@eecs.umich.edu { 2287720Sgblack@eecs.umich.edu _pcState = 0; 2296316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 23013501Sgabeblack@google.com memset(floatRegs, 0, sizeof(floatRegs)); 23112109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 23212109SRekai.GonzalezAlberquilla@arm.com vecRegs[i].zero(); 23312109SRekai.GonzalezAlberquilla@arm.com } 23413610Sgiacomo.gabrielli@arm.com for (int i = 0; i < TheISA::NumVecPredRegs; i++) { 23513610Sgiacomo.gabrielli@arm.com vecPredRegs[i].reset(); 23613610Sgiacomo.gabrielli@arm.com } 2379920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2389920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2399920Syasuko.eckert@amd.com#endif 2409384SAndreas.Sandberg@arm.com isa->clear(); 2416315Sgblack@eecs.umich.edu } 2422190SN/A 2432SN/A // 2442SN/A // New accessors for new decoder. 2452SN/A // 24613557Sgabeblack@google.com RegVal 24713557Sgabeblack@google.com readIntReg(int reg_idx) 2482SN/A { 2499384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2506323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2519426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2527601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2537601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2546418Sgblack@eecs.umich.edu return regVal; 2552SN/A } 2562SN/A 25713557Sgabeblack@google.com RegVal 25813557Sgabeblack@google.com readFloatRegBits(int reg_idx) 2592455SN/A { 2609384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2616323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 26213557Sgabeblack@google.com RegVal regVal(readFloatRegBitsFlat(flatIndex)); 26313501Sgabeblack@google.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 26413501Sgabeblack@google.com reg_idx, flatIndex, regVal); 2657341Sgblack@eecs.umich.edu return regVal; 2662SN/A } 2672SN/A 26812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 26912109SRekai.GonzalezAlberquilla@arm.com readVecReg(const RegId& reg) const 27012109SRekai.GonzalezAlberquilla@arm.com { 27112109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 27212109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 27312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& regVal = readVecRegFlat(flatIndex); 27412109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 27513610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 27612109SRekai.GonzalezAlberquilla@arm.com return regVal; 27712109SRekai.GonzalezAlberquilla@arm.com } 27812109SRekai.GonzalezAlberquilla@arm.com 27912109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 28012109SRekai.GonzalezAlberquilla@arm.com getWritableVecReg(const RegId& reg) 28112109SRekai.GonzalezAlberquilla@arm.com { 28212109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 28312109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 28412109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 28512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 28613610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 28712109SRekai.GonzalezAlberquilla@arm.com return regVal; 28812109SRekai.GonzalezAlberquilla@arm.com } 28912109SRekai.GonzalezAlberquilla@arm.com 29012109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 29112109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 29212109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector <T> operand. */ 29312109SRekai.GonzalezAlberquilla@arm.com template <typename T> 29412109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> 29512109SRekai.GonzalezAlberquilla@arm.com readVecLane(const RegId& reg) const 29612109SRekai.GonzalezAlberquilla@arm.com { 29712109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 29812109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 29912109SRekai.GonzalezAlberquilla@arm.com auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 30012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 30112109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), regVal); 30212109SRekai.GonzalezAlberquilla@arm.com return regVal; 30312109SRekai.GonzalezAlberquilla@arm.com } 30412109SRekai.GonzalezAlberquilla@arm.com 30512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 30612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 30712109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 30812109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint8_t>(reg); } 30912109SRekai.GonzalezAlberquilla@arm.com 31012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 31112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 31212109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 31312109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint16_t>(reg); } 31412109SRekai.GonzalezAlberquilla@arm.com 31512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 31612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 31712109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 31812109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint32_t>(reg); } 31912109SRekai.GonzalezAlberquilla@arm.com 32012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 32112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 32212109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 32312109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint64_t>(reg); } 32412109SRekai.GonzalezAlberquilla@arm.com 32512109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 32612109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 32712109SRekai.GonzalezAlberquilla@arm.com void setVecLaneT(const RegId& reg, const LD& val) 32812109SRekai.GonzalezAlberquilla@arm.com { 32912109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 33012109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 33112109SRekai.GonzalezAlberquilla@arm.com setVecLaneFlat(flatIndex, reg.elemIndex(), val); 33212109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 33312109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), val); 33412109SRekai.GonzalezAlberquilla@arm.com } 33512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33612109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 33712109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 34012109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 34312109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 34612109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34712109SRekai.GonzalezAlberquilla@arm.com /** @} */ 34812109SRekai.GonzalezAlberquilla@arm.com 34912109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 35012109SRekai.GonzalezAlberquilla@arm.com { 35112109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 35212109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 35312109SRekai.GonzalezAlberquilla@arm.com const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 35412109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 35512109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 35612109SRekai.GonzalezAlberquilla@arm.com return regVal; 35712109SRekai.GonzalezAlberquilla@arm.com } 35812109SRekai.GonzalezAlberquilla@arm.com 35913610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& 36013610Sgiacomo.gabrielli@arm.com readVecPredReg(const RegId& reg) const 36113610Sgiacomo.gabrielli@arm.com { 36213610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 36313610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 36413610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex); 36513610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n", 36613610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 36713610Sgiacomo.gabrielli@arm.com return regVal; 36813610Sgiacomo.gabrielli@arm.com } 36913610Sgiacomo.gabrielli@arm.com 37013610Sgiacomo.gabrielli@arm.com VecPredRegContainer& 37113610Sgiacomo.gabrielli@arm.com getWritableVecPredReg(const RegId& reg) 37213610Sgiacomo.gabrielli@arm.com { 37313610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 37413610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 37513610Sgiacomo.gabrielli@arm.com VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex); 37613610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, 37713610Sgiacomo.gabrielli@arm.com "Reading predicate reg %d (%d) as %s for modify.\n", 37813610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, regVal.print()); 37913610Sgiacomo.gabrielli@arm.com return regVal; 38013610Sgiacomo.gabrielli@arm.com } 38112109SRekai.GonzalezAlberquilla@arm.com 3829920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 3839920Syasuko.eckert@amd.com { 3849920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3859920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 38610338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 3879920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3889920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 3899920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 3909920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 3919920Syasuko.eckert@amd.com return regVal; 3929920Syasuko.eckert@amd.com#else 3939920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 3949920Syasuko.eckert@amd.com return 0; 3959920Syasuko.eckert@amd.com#endif 3969920Syasuko.eckert@amd.com } 3979920Syasuko.eckert@amd.com 39813557Sgabeblack@google.com void 39913557Sgabeblack@google.com setIntReg(int reg_idx, RegVal val) 4002SN/A { 4019384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 4026323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 4037601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 4047601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 4059426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 4062SN/A } 4072SN/A 40813557Sgabeblack@google.com void 40913557Sgabeblack@google.com setFloatRegBits(int reg_idx, RegVal val) 4102455SN/A { 4119384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 4126323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 4138733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 4148733Sgeoffrey.blake@arm.com // when checkercpu enabled 4158733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 4169426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 41713501Sgabeblack@google.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 41813501Sgabeblack@google.com reg_idx, flatIndex, val); 4192SN/A } 4202SN/A 42113557Sgabeblack@google.com void 42213557Sgabeblack@google.com setVecReg(const RegId& reg, const VecRegContainer& val) 42312109SRekai.GonzalezAlberquilla@arm.com { 42412109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 42512109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 42612109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flatIndex, val); 42712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 42812109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, val.print()); 42912109SRekai.GonzalezAlberquilla@arm.com } 43012109SRekai.GonzalezAlberquilla@arm.com 43113557Sgabeblack@google.com void 43213557Sgabeblack@google.com setVecElem(const RegId& reg, const VecElem& val) 43312109SRekai.GonzalezAlberquilla@arm.com { 43412109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 43512109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 43612109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flatIndex, reg.elemIndex(), val); 43712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 43812109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 43912109SRekai.GonzalezAlberquilla@arm.com } 44012109SRekai.GonzalezAlberquilla@arm.com 44113557Sgabeblack@google.com void 44213610Sgiacomo.gabrielli@arm.com setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 44313610Sgiacomo.gabrielli@arm.com { 44413610Sgiacomo.gabrielli@arm.com int flatIndex = isa->flattenVecPredIndex(reg.index()); 44513610Sgiacomo.gabrielli@arm.com assert(flatIndex < TheISA::NumVecPredRegs); 44613610Sgiacomo.gabrielli@arm.com setVecPredRegFlat(flatIndex, val); 44713610Sgiacomo.gabrielli@arm.com DPRINTF(VecPredRegs, "Setting predicate reg %d (%d) to %s.\n", 44813610Sgiacomo.gabrielli@arm.com reg.index(), flatIndex, val.print()); 44913610Sgiacomo.gabrielli@arm.com } 45013610Sgiacomo.gabrielli@arm.com 45113610Sgiacomo.gabrielli@arm.com void 45213557Sgabeblack@google.com setCCReg(int reg_idx, CCReg val) 4539920Syasuko.eckert@amd.com { 4549920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4559920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 4569920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 4579920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 4589920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 4599920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 4609920Syasuko.eckert@amd.com#else 4619920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 4629920Syasuko.eckert@amd.com#endif 4639920Syasuko.eckert@amd.com } 4649920Syasuko.eckert@amd.com 4657720Sgblack@eecs.umich.edu TheISA::PCState 4667720Sgblack@eecs.umich.edu pcState() 4672SN/A { 4687720Sgblack@eecs.umich.edu return _pcState; 4692SN/A } 4702SN/A 4717720Sgblack@eecs.umich.edu void 4727720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 4732190SN/A { 4747720Sgblack@eecs.umich.edu _pcState = val; 4752190SN/A } 4762190SN/A 4778733Sgeoffrey.blake@arm.com void 4788733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 4798733Sgeoffrey.blake@arm.com { 4808733Sgeoffrey.blake@arm.com _pcState = val; 4818733Sgeoffrey.blake@arm.com } 4828733Sgeoffrey.blake@arm.com 4837720Sgblack@eecs.umich.edu Addr 4847720Sgblack@eecs.umich.edu instAddr() 4853276Sgblack@eecs.umich.edu { 4867720Sgblack@eecs.umich.edu return _pcState.instAddr(); 4873276Sgblack@eecs.umich.edu } 4883276Sgblack@eecs.umich.edu 4897720Sgblack@eecs.umich.edu Addr 4907720Sgblack@eecs.umich.edu nextInstAddr() 4913276Sgblack@eecs.umich.edu { 4927720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 4933276Sgblack@eecs.umich.edu } 4943276Sgblack@eecs.umich.edu 49511886Sbrandon.potter@amd.com void 49611886Sbrandon.potter@amd.com setNPC(Addr val) 49711886Sbrandon.potter@amd.com { 49811886Sbrandon.potter@amd.com _pcState.setNPC(val); 49911886Sbrandon.potter@amd.com } 50011886Sbrandon.potter@amd.com 5017720Sgblack@eecs.umich.edu MicroPC 5027720Sgblack@eecs.umich.edu microPC() 5032190SN/A { 5047720Sgblack@eecs.umich.edu return _pcState.microPC(); 5052251SN/A } 5062251SN/A 5077597Sminkyu.jeong@arm.com bool readPredicate() 5087597Sminkyu.jeong@arm.com { 5097597Sminkyu.jeong@arm.com return predicate; 5107597Sminkyu.jeong@arm.com } 5117597Sminkyu.jeong@arm.com 5127597Sminkyu.jeong@arm.com void setPredicate(bool val) 5137597Sminkyu.jeong@arm.com { 5147597Sminkyu.jeong@arm.com predicate = val; 5157597Sminkyu.jeong@arm.com } 5167597Sminkyu.jeong@arm.com 51713557Sgabeblack@google.com RegVal 51813557Sgabeblack@google.com readMiscRegNoEffect(int misc_reg, ThreadID tid=0) const 5194172Ssaidi@eecs.umich.edu { 5209384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 5214172Ssaidi@eecs.umich.edu } 5224172Ssaidi@eecs.umich.edu 52313557Sgabeblack@google.com RegVal 52413557Sgabeblack@google.com readMiscReg(int misc_reg, ThreadID tid=0) 5252SN/A { 5269384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 5272SN/A } 5282SN/A 5296221Snate@binkert.org void 53013582Sgabeblack@google.com setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid = 0) 5312SN/A { 5329384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 5332SN/A } 5342SN/A 5356221Snate@binkert.org void 53613582Sgabeblack@google.com setMiscReg(int misc_reg, RegVal val, ThreadID tid = 0) 5372SN/A { 5389384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 5396313Sgblack@eecs.umich.edu } 5406313Sgblack@eecs.umich.edu 54112106SRekai.GonzalezAlberquilla@arm.com RegId 54212106SRekai.GonzalezAlberquilla@arm.com flattenRegId(const RegId& regId) const 5436313Sgblack@eecs.umich.edu { 54412106SRekai.GonzalezAlberquilla@arm.com return isa->flattenRegId(regId); 54510033SAli.Saidi@ARM.com } 54610033SAli.Saidi@ARM.com 5472190SN/A unsigned readStCondFailures() { return storeCondFailures; } 5482190SN/A 5492190SN/A void setStCondFailures(unsigned sc_failures) 5502190SN/A { storeCondFailures = sc_failures; } 5512190SN/A 55213557Sgabeblack@google.com void 55313557Sgabeblack@google.com syscall(int64_t callnum, Fault *fault) 5542SN/A { 55511877Sbrandon.potter@amd.com process->syscall(callnum, tc, fault); 5562SN/A } 5579426SAndreas.Sandberg@ARM.com 55813557Sgabeblack@google.com RegVal readIntRegFlat(int idx) { return intRegs[idx]; } 55913557Sgabeblack@google.com void setIntRegFlat(int idx, RegVal val) { intRegs[idx] = val; } 5609426SAndreas.Sandberg@ARM.com 56113557Sgabeblack@google.com RegVal readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 56213557Sgabeblack@google.com void setFloatRegBitsFlat(int idx, RegVal val) { floatRegs[idx] = val; } 5639426SAndreas.Sandberg@ARM.com 56413557Sgabeblack@google.com const VecRegContainer & 56513557Sgabeblack@google.com readVecRegFlat(const RegIndex& reg) const 56612109SRekai.GonzalezAlberquilla@arm.com { 56712109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 56812109SRekai.GonzalezAlberquilla@arm.com } 56912109SRekai.GonzalezAlberquilla@arm.com 57013557Sgabeblack@google.com VecRegContainer & 57113557Sgabeblack@google.com getWritableVecRegFlat(const RegIndex& reg) 57212109SRekai.GonzalezAlberquilla@arm.com { 57312109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 57412109SRekai.GonzalezAlberquilla@arm.com } 57512109SRekai.GonzalezAlberquilla@arm.com 57613557Sgabeblack@google.com void 57713557Sgabeblack@google.com setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 57812109SRekai.GonzalezAlberquilla@arm.com { 57912109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg] = val; 58012109SRekai.GonzalezAlberquilla@arm.com } 58112109SRekai.GonzalezAlberquilla@arm.com 58212109SRekai.GonzalezAlberquilla@arm.com template <typename T> 58313557Sgabeblack@google.com VecLaneT<T, true> 58413557Sgabeblack@google.com readVecLaneFlat(const RegIndex& reg, int lId) const 58512109SRekai.GonzalezAlberquilla@arm.com { 58612109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].laneView<T>(lId); 58712109SRekai.GonzalezAlberquilla@arm.com } 58812109SRekai.GonzalezAlberquilla@arm.com 58912109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 59013557Sgabeblack@google.com void 59113557Sgabeblack@google.com setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 59212109SRekai.GonzalezAlberquilla@arm.com { 59312109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 59412109SRekai.GonzalezAlberquilla@arm.com } 59512109SRekai.GonzalezAlberquilla@arm.com 59613557Sgabeblack@google.com const VecElem & 59713557Sgabeblack@google.com readVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex) const 59812109SRekai.GonzalezAlberquilla@arm.com { 59912109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 60012109SRekai.GonzalezAlberquilla@arm.com } 60112109SRekai.GonzalezAlberquilla@arm.com 60213557Sgabeblack@google.com void 60313557Sgabeblack@google.com setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 60413557Sgabeblack@google.com const VecElem val) 60512109SRekai.GonzalezAlberquilla@arm.com { 60612109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 60712109SRekai.GonzalezAlberquilla@arm.com } 60812109SRekai.GonzalezAlberquilla@arm.com 60913610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredRegFlat(const RegIndex& reg) const 61013610Sgiacomo.gabrielli@arm.com { 61113610Sgiacomo.gabrielli@arm.com return vecPredRegs[reg]; 61213610Sgiacomo.gabrielli@arm.com } 61313610Sgiacomo.gabrielli@arm.com 61413610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredRegFlat(const RegIndex& reg) 61513610Sgiacomo.gabrielli@arm.com { 61613610Sgiacomo.gabrielli@arm.com return vecPredRegs[reg]; 61713610Sgiacomo.gabrielli@arm.com } 61813610Sgiacomo.gabrielli@arm.com 61913610Sgiacomo.gabrielli@arm.com void setVecPredRegFlat(const RegIndex& reg, const VecPredRegContainer& val) 62013610Sgiacomo.gabrielli@arm.com { 62113610Sgiacomo.gabrielli@arm.com vecPredRegs[reg] = val; 62213610Sgiacomo.gabrielli@arm.com } 62313610Sgiacomo.gabrielli@arm.com 6249920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 6259920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 6269920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 6279920Syasuko.eckert@amd.com#else 6289920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 6299920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 6309920Syasuko.eckert@amd.com 6319920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 6329920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 6339920Syasuko.eckert@amd.com#endif 6342SN/A}; 6352SN/A 6362SN/A 6372190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 638