simple_thread.hh revision 13501
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2012, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Steve Reinhardt 422665SN/A * Nathan Binkert 432SN/A */ 442SN/A 452683Sktlim@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462683Sktlim@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 472SN/A 489020Sgblack@eecs.umich.edu#include "arch/decoder.hh" 4912406Sgabeblack@google.com#include "arch/generic/tlb.hh" 506313Sgblack@eecs.umich.edu#include "arch/isa.hh" 512190SN/A#include "arch/isa_traits.hh" 526329Sgblack@eecs.umich.edu#include "arch/registers.hh" 536316Sgblack@eecs.umich.edu#include "arch/types.hh" 546216Snate@binkert.org#include "base/types.hh" 556658Snate@binkert.org#include "config/the_isa.hh" 562680SN/A#include "cpu/thread_context.hh" 572683Sktlim@umich.edu#include "cpu/thread_state.hh" 589920Syasuko.eckert@amd.com#include "debug/CCRegs.hh" 598232Snate@binkert.org#include "debug/FloatRegs.hh" 608232Snate@binkert.org#include "debug/IntRegs.hh" 6112109SRekai.GonzalezAlberquilla@arm.com#include "debug/VecRegs.hh" 628777Sgblack@eecs.umich.edu#include "mem/page_table.hh" 632395SN/A#include "mem/request.hh" 642190SN/A#include "sim/byteswap.hh" 652188SN/A#include "sim/eventq.hh" 668777Sgblack@eecs.umich.edu#include "sim/process.hh" 67217SN/A#include "sim/serialize.hh" 688777Sgblack@eecs.umich.edu#include "sim/system.hh" 692SN/A 702SN/Aclass BaseCPU; 718887Sgeoffrey.blake@arm.comclass CheckerCPU; 721070SN/A 731917SN/Aclass FunctionProfile; 741917SN/Aclass ProfileNode; 752521SN/A 763548Sgblack@eecs.umich.edunamespace TheISA { 773548Sgblack@eecs.umich.edu namespace Kernel { 783548Sgblack@eecs.umich.edu class Statistics; 798902Sandreas.hansson@arm.com } 808902Sandreas.hansson@arm.com} 812330SN/A 822683Sktlim@umich.edu/** 832683Sktlim@umich.edu * The SimpleThread object provides a combination of the ThreadState 842683Sktlim@umich.edu * object and the ThreadContext interface. It implements the 852683Sktlim@umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 862683Sktlim@umich.edu * made using SimpleThread as the template parameter (see 872683Sktlim@umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 882683Sktlim@umich.edu * the objects needed for simple functional execution, including a 892683Sktlim@umich.edu * simple architectural register file, and pointers to the ITB and DTB 902683Sktlim@umich.edu * in full system mode. For CPU models that do not need more advanced 912683Sktlim@umich.edu * ways to hold state (i.e. a separate physical register file, or 922683Sktlim@umich.edu * separate fetch and commit PC's), this SimpleThread class provides 932683Sktlim@umich.edu * all the necessary state for full architecture-level functional 942683Sktlim@umich.edu * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 952683Sktlim@umich.edu * examples. 962683Sktlim@umich.edu */ 972SN/A 982683Sktlim@umich.educlass SimpleThread : public ThreadState 992SN/A{ 1002107SN/A protected: 1012107SN/A typedef TheISA::MachInst MachInst; 1022159SN/A typedef TheISA::MiscReg MiscReg; 1032455SN/A typedef TheISA::FloatReg FloatReg; 1042455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1059920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 10612109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 10712109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 1082SN/A public: 1092680SN/A typedef ThreadContext::Status Status; 1102SN/A 1112190SN/A protected: 11213501Sgabeblack@google.com FloatRegBits floatRegs[TheISA::NumFloatRegs]; 1136316Sgblack@eecs.umich.edu TheISA::IntReg intRegs[TheISA::NumIntRegs]; 11412109SRekai.GonzalezAlberquilla@arm.com VecRegContainer vecRegs[TheISA::NumVecRegs]; 1159920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1169920Syasuko.eckert@amd.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1179920Syasuko.eckert@amd.com#endif 1189384SAndreas.Sandberg@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1192SN/A 1207720Sgblack@eecs.umich.edu TheISA::PCState _pcState; 1216324Sgblack@eecs.umich.edu 1227597Sminkyu.jeong@arm.com /** Did this instruction execute or is it predicated false */ 1237597Sminkyu.jeong@arm.com bool predicate; 1247597Sminkyu.jeong@arm.com 1252190SN/A public: 1268357Sksewell@umich.edu std::string name() const 1278357Sksewell@umich.edu { 1288735Sandreas.hanson@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1298357Sksewell@umich.edu } 1308357Sksewell@umich.edu 1312683Sktlim@umich.edu ProxyThreadContext<SimpleThread> *tc; 1322188SN/A 1332378SN/A System *system; 1342400SN/A 13512406Sgabeblack@google.com BaseTLB *itb; 13612406Sgabeblack@google.com BaseTLB *dtb; 1372SN/A 1389020Sgblack@eecs.umich.edu TheISA::Decoder decoder; 1398541Sgblack@eecs.umich.edu 1402683Sktlim@umich.edu // constructor: initialize SimpleThread from given process structure 1418793Sgblack@eecs.umich.edu // FS 1422683Sktlim@umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14312406Sgabeblack@google.com BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa, 1442683Sktlim@umich.edu bool use_kernel_stats = true); 1458793Sgblack@eecs.umich.edu // SE 1468820Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 14712406Sgabeblack@google.com Process *_process, BaseTLB *_itb, BaseTLB *_dtb, 1489384SAndreas.Sandberg@arm.com TheISA::ISA *_isa); 1492862Sktlim@umich.edu 1502683Sktlim@umich.edu virtual ~SimpleThread(); 1512SN/A 1522680SN/A virtual void takeOverFrom(ThreadContext *oldContext); 153180SN/A 1542SN/A void regStats(const std::string &name); 1552SN/A 1562862Sktlim@umich.edu void copyState(ThreadContext *oldContext); 1572862Sktlim@umich.edu 15811168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 15911168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 1609461Snilay@cs.wisc.edu void startup(); 161217SN/A 1622683Sktlim@umich.edu /*************************************************************** 1632683Sktlim@umich.edu * SimpleThread functions to provide CPU with access to various 1645891Sgblack@eecs.umich.edu * state. 1652683Sktlim@umich.edu **************************************************************/ 1662190SN/A 1672683Sktlim@umich.edu /** Returns the pointer to this SimpleThread's ThreadContext. Used 1682683Sktlim@umich.edu * when a ThreadContext must be passed to objects outside of the 1692683Sktlim@umich.edu * CPU. 1702683Sktlim@umich.edu */ 1712680SN/A ThreadContext *getTC() { return tc; } 1722190SN/A 1735358Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1745358Sgblack@eecs.umich.edu { 1755358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1765358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1775358Sgblack@eecs.umich.edu } 1785358Sgblack@eecs.umich.edu 1795358Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1805358Sgblack@eecs.umich.edu { 1815358Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1825358Sgblack@eecs.umich.edu } 1835358Sgblack@eecs.umich.edu 1845358Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1855358Sgblack@eecs.umich.edu { 1865358Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1875358Sgblack@eecs.umich.edu } 1885358Sgblack@eecs.umich.edu 1892683Sktlim@umich.edu void dumpFuncProfile(); 1902521SN/A 1915702Ssaidi@eecs.umich.edu Fault hwrei(); 1925702Ssaidi@eecs.umich.edu 1935702Ssaidi@eecs.umich.edu bool simPalCheck(int palFunc); 1945702Ssaidi@eecs.umich.edu 1952683Sktlim@umich.edu /******************************************* 1962683Sktlim@umich.edu * ThreadContext interface functions. 1972683Sktlim@umich.edu ******************************************/ 1982683Sktlim@umich.edu 1998735Sandreas.hanson@arm.com BaseCPU *getCpuPtr() { return baseCpu; } 2002683Sktlim@umich.edu 20112406Sgabeblack@google.com BaseTLB *getITBPtr() { return itb; } 2022683Sktlim@umich.edu 20312406Sgabeblack@google.com BaseTLB *getDTBPtr() { return dtb; } 2042683Sktlim@umich.edu 2058887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2068733Sgeoffrey.blake@arm.com 2079020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2088541Sgblack@eecs.umich.edu 2094997Sgblack@eecs.umich.edu System *getSystemPtr() { return system; } 2104997Sgblack@eecs.umich.edu 2112683Sktlim@umich.edu Status status() const { return _status; } 2122683Sktlim@umich.edu 2132683Sktlim@umich.edu void setStatus(Status newStatus) { _status = newStatus; } 2142683Sktlim@umich.edu 21510407Smitch.hayenga@arm.com /// Set the status to Active. 21610407Smitch.hayenga@arm.com void activate(); 2172683Sktlim@umich.edu 2182683Sktlim@umich.edu /// Set the status to Suspended. 2192683Sktlim@umich.edu void suspend(); 2202683Sktlim@umich.edu 2212683Sktlim@umich.edu /// Set the status to Halted. 2222683Sktlim@umich.edu void halt(); 2232683Sktlim@umich.edu 2242683Sktlim@umich.edu void copyArchRegs(ThreadContext *tc); 2252190SN/A 2266315Sgblack@eecs.umich.edu void clearArchRegs() 2276315Sgblack@eecs.umich.edu { 2287720Sgblack@eecs.umich.edu _pcState = 0; 2296316Sgblack@eecs.umich.edu memset(intRegs, 0, sizeof(intRegs)); 23013501Sgabeblack@google.com memset(floatRegs, 0, sizeof(floatRegs)); 23112109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < TheISA::NumVecRegs; i++) { 23212109SRekai.GonzalezAlberquilla@arm.com vecRegs[i].zero(); 23312109SRekai.GonzalezAlberquilla@arm.com } 2349920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2359920Syasuko.eckert@amd.com memset(ccRegs, 0, sizeof(ccRegs)); 2369920Syasuko.eckert@amd.com#endif 2379384SAndreas.Sandberg@arm.com isa->clear(); 2386315Sgblack@eecs.umich.edu } 2392190SN/A 2402SN/A // 2412SN/A // New accessors for new decoder. 2422SN/A // 2432SN/A uint64_t readIntReg(int reg_idx) 2442SN/A { 2459384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 2466323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2479426SAndreas.Sandberg@ARM.com uint64_t regVal(readIntRegFlat(flatIndex)); 2487601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2497601Sminkyu.jeong@arm.com reg_idx, flatIndex, regVal); 2506418Sgblack@eecs.umich.edu return regVal; 2512SN/A } 2522SN/A 2532455SN/A FloatRegBits readFloatRegBits(int reg_idx) 2542455SN/A { 2559384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 2566323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2579426SAndreas.Sandberg@ARM.com FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 25813501Sgabeblack@google.com DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x.\n", 25913501Sgabeblack@google.com reg_idx, flatIndex, regVal); 2607341Sgblack@eecs.umich.edu return regVal; 2612SN/A } 2622SN/A 26312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& 26412109SRekai.GonzalezAlberquilla@arm.com readVecReg(const RegId& reg) const 26512109SRekai.GonzalezAlberquilla@arm.com { 26612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 26712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 26812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& regVal = readVecRegFlat(flatIndex); 26912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n", 27012109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 27112109SRekai.GonzalezAlberquilla@arm.com return regVal; 27212109SRekai.GonzalezAlberquilla@arm.com } 27312109SRekai.GonzalezAlberquilla@arm.com 27412109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& 27512109SRekai.GonzalezAlberquilla@arm.com getWritableVecReg(const RegId& reg) 27612109SRekai.GonzalezAlberquilla@arm.com { 27712109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 27812109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 27912109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& regVal = getWritableVecRegFlat(flatIndex); 28012109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n", 28112109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, regVal.as<TheISA::VecElem>().print()); 28212109SRekai.GonzalezAlberquilla@arm.com return regVal; 28312109SRekai.GonzalezAlberquilla@arm.com } 28412109SRekai.GonzalezAlberquilla@arm.com 28512109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 28612109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 28712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector <T> operand. */ 28812109SRekai.GonzalezAlberquilla@arm.com template <typename T> 28912109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> 29012109SRekai.GonzalezAlberquilla@arm.com readVecLane(const RegId& reg) const 29112109SRekai.GonzalezAlberquilla@arm.com { 29212109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 29312109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 29412109SRekai.GonzalezAlberquilla@arm.com auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex()); 29512109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n", 29612109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), regVal); 29712109SRekai.GonzalezAlberquilla@arm.com return regVal; 29812109SRekai.GonzalezAlberquilla@arm.com } 29912109SRekai.GonzalezAlberquilla@arm.com 30012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 30112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 30212109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 30312109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint8_t>(reg); } 30412109SRekai.GonzalezAlberquilla@arm.com 30512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 30612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 30712109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 30812109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint16_t>(reg); } 30912109SRekai.GonzalezAlberquilla@arm.com 31012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 31112109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 31212109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 31312109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint32_t>(reg); } 31412109SRekai.GonzalezAlberquilla@arm.com 31512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 31612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 31712109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 31812109SRekai.GonzalezAlberquilla@arm.com { return readVecLane<uint64_t>(reg); } 31912109SRekai.GonzalezAlberquilla@arm.com 32012109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 32112109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 32212109SRekai.GonzalezAlberquilla@arm.com void setVecLaneT(const RegId& reg, const LD& val) 32312109SRekai.GonzalezAlberquilla@arm.com { 32412109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 32512109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 32612109SRekai.GonzalezAlberquilla@arm.com setVecLaneFlat(flatIndex, reg.elemIndex(), val); 32712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n", 32812109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, reg.elemIndex(), val); 32912109SRekai.GonzalezAlberquilla@arm.com } 33012109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 33212109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33412109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 33512109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 33712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 33812109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 33912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 34012109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 34112109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneT(reg, val); } 34212109SRekai.GonzalezAlberquilla@arm.com /** @} */ 34312109SRekai.GonzalezAlberquilla@arm.com 34412109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 34512109SRekai.GonzalezAlberquilla@arm.com { 34612109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 34712109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 34812109SRekai.GonzalezAlberquilla@arm.com const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex()); 34912109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as" 35012109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal); 35112109SRekai.GonzalezAlberquilla@arm.com return regVal; 35212109SRekai.GonzalezAlberquilla@arm.com } 35312109SRekai.GonzalezAlberquilla@arm.com 35412109SRekai.GonzalezAlberquilla@arm.com 3559920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 3569920Syasuko.eckert@amd.com { 3579920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 3589920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 35910338SCurtis.Dunham@arm.com assert(0 <= flatIndex); 3609920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 3619920Syasuko.eckert@amd.com uint64_t regVal(readCCRegFlat(flatIndex)); 3629920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 3639920Syasuko.eckert@amd.com reg_idx, flatIndex, regVal); 3649920Syasuko.eckert@amd.com return regVal; 3659920Syasuko.eckert@amd.com#else 3669920Syasuko.eckert@amd.com panic("Tried to read a CC register."); 3679920Syasuko.eckert@amd.com return 0; 3689920Syasuko.eckert@amd.com#endif 3699920Syasuko.eckert@amd.com } 3709920Syasuko.eckert@amd.com 3712SN/A void setIntReg(int reg_idx, uint64_t val) 3722SN/A { 3739384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenIntIndex(reg_idx); 3746323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 3757601Sminkyu.jeong@arm.com DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 3767601Sminkyu.jeong@arm.com reg_idx, flatIndex, val); 3779426SAndreas.Sandberg@ARM.com setIntRegFlat(flatIndex, val); 3782SN/A } 3792SN/A 3802455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3812455SN/A { 3829384SAndreas.Sandberg@arm.com int flatIndex = isa->flattenFloatIndex(reg_idx); 3836323Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3848733Sgeoffrey.blake@arm.com // XXX: Fix array out of bounds compiler error for gem5.fast 3858733Sgeoffrey.blake@arm.com // when checkercpu enabled 3868733Sgeoffrey.blake@arm.com if (flatIndex < TheISA::NumFloatRegs) 3879426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 38813501Sgabeblack@google.com DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x.\n", 38913501Sgabeblack@google.com reg_idx, flatIndex, val); 3902SN/A } 3912SN/A 39212109SRekai.GonzalezAlberquilla@arm.com void setVecReg(const RegId& reg, const VecRegContainer& val) 39312109SRekai.GonzalezAlberquilla@arm.com { 39412109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecIndex(reg.index()); 39512109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 39612109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flatIndex, val); 39712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting vector reg %d (%d) to %s.\n", 39812109SRekai.GonzalezAlberquilla@arm.com reg.index(), flatIndex, val.print()); 39912109SRekai.GonzalezAlberquilla@arm.com } 40012109SRekai.GonzalezAlberquilla@arm.com 40112109SRekai.GonzalezAlberquilla@arm.com void setVecElem(const RegId& reg, const VecElem& val) 40212109SRekai.GonzalezAlberquilla@arm.com { 40312109SRekai.GonzalezAlberquilla@arm.com int flatIndex = isa->flattenVecElemIndex(reg.index()); 40412109SRekai.GonzalezAlberquilla@arm.com assert(flatIndex < TheISA::NumVecRegs); 40512109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flatIndex, reg.elemIndex(), val); 40612109SRekai.GonzalezAlberquilla@arm.com DPRINTF(VecRegs, "Setting element %d of vector reg %d (%d) to" 40712109SRekai.GonzalezAlberquilla@arm.com " %#x.\n", reg.elemIndex(), reg.index(), flatIndex, val); 40812109SRekai.GonzalezAlberquilla@arm.com } 40912109SRekai.GonzalezAlberquilla@arm.com 4109920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 4119920Syasuko.eckert@amd.com { 4129920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 4139920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 4149920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 4159920Syasuko.eckert@amd.com DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 4169920Syasuko.eckert@amd.com reg_idx, flatIndex, val); 4179920Syasuko.eckert@amd.com setCCRegFlat(flatIndex, val); 4189920Syasuko.eckert@amd.com#else 4199920Syasuko.eckert@amd.com panic("Tried to set a CC register."); 4209920Syasuko.eckert@amd.com#endif 4219920Syasuko.eckert@amd.com } 4229920Syasuko.eckert@amd.com 4237720Sgblack@eecs.umich.edu TheISA::PCState 4247720Sgblack@eecs.umich.edu pcState() 4252SN/A { 4267720Sgblack@eecs.umich.edu return _pcState; 4272SN/A } 4282SN/A 4297720Sgblack@eecs.umich.edu void 4307720Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 4312190SN/A { 4327720Sgblack@eecs.umich.edu _pcState = val; 4332190SN/A } 4342190SN/A 4358733Sgeoffrey.blake@arm.com void 4368733Sgeoffrey.blake@arm.com pcStateNoRecord(const TheISA::PCState &val) 4378733Sgeoffrey.blake@arm.com { 4388733Sgeoffrey.blake@arm.com _pcState = val; 4398733Sgeoffrey.blake@arm.com } 4408733Sgeoffrey.blake@arm.com 4417720Sgblack@eecs.umich.edu Addr 4427720Sgblack@eecs.umich.edu instAddr() 4433276Sgblack@eecs.umich.edu { 4447720Sgblack@eecs.umich.edu return _pcState.instAddr(); 4453276Sgblack@eecs.umich.edu } 4463276Sgblack@eecs.umich.edu 4477720Sgblack@eecs.umich.edu Addr 4487720Sgblack@eecs.umich.edu nextInstAddr() 4493276Sgblack@eecs.umich.edu { 4507720Sgblack@eecs.umich.edu return _pcState.nextInstAddr(); 4513276Sgblack@eecs.umich.edu } 4523276Sgblack@eecs.umich.edu 45311886Sbrandon.potter@amd.com void 45411886Sbrandon.potter@amd.com setNPC(Addr val) 45511886Sbrandon.potter@amd.com { 45611886Sbrandon.potter@amd.com _pcState.setNPC(val); 45711886Sbrandon.potter@amd.com } 45811886Sbrandon.potter@amd.com 4597720Sgblack@eecs.umich.edu MicroPC 4607720Sgblack@eecs.umich.edu microPC() 4612190SN/A { 4627720Sgblack@eecs.umich.edu return _pcState.microPC(); 4632251SN/A } 4642251SN/A 4657597Sminkyu.jeong@arm.com bool readPredicate() 4667597Sminkyu.jeong@arm.com { 4677597Sminkyu.jeong@arm.com return predicate; 4687597Sminkyu.jeong@arm.com } 4697597Sminkyu.jeong@arm.com 4707597Sminkyu.jeong@arm.com void setPredicate(bool val) 4717597Sminkyu.jeong@arm.com { 4727597Sminkyu.jeong@arm.com predicate = val; 4737597Sminkyu.jeong@arm.com } 4747597Sminkyu.jeong@arm.com 4756221Snate@binkert.org MiscReg 47610698Sandreas.hansson@arm.com readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const 4774172Ssaidi@eecs.umich.edu { 4789384SAndreas.Sandberg@arm.com return isa->readMiscRegNoEffect(misc_reg); 4794172Ssaidi@eecs.umich.edu } 4804172Ssaidi@eecs.umich.edu 4816221Snate@binkert.org MiscReg 4826221Snate@binkert.org readMiscReg(int misc_reg, ThreadID tid = 0) 4832SN/A { 4849384SAndreas.Sandberg@arm.com return isa->readMiscReg(misc_reg, tc); 4852SN/A } 4862SN/A 4876221Snate@binkert.org void 4886221Snate@binkert.org setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 4892SN/A { 4909384SAndreas.Sandberg@arm.com return isa->setMiscRegNoEffect(misc_reg, val); 4912SN/A } 4922SN/A 4936221Snate@binkert.org void 4946221Snate@binkert.org setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 4952SN/A { 4969384SAndreas.Sandberg@arm.com return isa->setMiscReg(misc_reg, val, tc); 4976313Sgblack@eecs.umich.edu } 4986313Sgblack@eecs.umich.edu 49912106SRekai.GonzalezAlberquilla@arm.com RegId 50012106SRekai.GonzalezAlberquilla@arm.com flattenRegId(const RegId& regId) const 5016313Sgblack@eecs.umich.edu { 50212106SRekai.GonzalezAlberquilla@arm.com return isa->flattenRegId(regId); 50310033SAli.Saidi@ARM.com } 50410033SAli.Saidi@ARM.com 5052190SN/A unsigned readStCondFailures() { return storeCondFailures; } 5062190SN/A 5072190SN/A void setStCondFailures(unsigned sc_failures) 5082190SN/A { storeCondFailures = sc_failures; } 5092190SN/A 51011877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 5112SN/A { 51211877Sbrandon.potter@amd.com process->syscall(callnum, tc, fault); 5132SN/A } 5149426SAndreas.Sandberg@ARM.com 5159426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 5169426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 5179426SAndreas.Sandberg@ARM.com 51813501Sgabeblack@google.com FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs[idx]; } 5199426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) { 52013501Sgabeblack@google.com floatRegs[idx] = val; 5219426SAndreas.Sandberg@ARM.com } 5229426SAndreas.Sandberg@ARM.com 52312109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegFlat(const RegIndex& reg) const 52412109SRekai.GonzalezAlberquilla@arm.com { 52512109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 52612109SRekai.GonzalezAlberquilla@arm.com } 52712109SRekai.GonzalezAlberquilla@arm.com 52812109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegFlat(const RegIndex& reg) 52912109SRekai.GonzalezAlberquilla@arm.com { 53012109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg]; 53112109SRekai.GonzalezAlberquilla@arm.com } 53212109SRekai.GonzalezAlberquilla@arm.com 53312109SRekai.GonzalezAlberquilla@arm.com void setVecRegFlat(const RegIndex& reg, const VecRegContainer& val) 53412109SRekai.GonzalezAlberquilla@arm.com { 53512109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg] = val; 53612109SRekai.GonzalezAlberquilla@arm.com } 53712109SRekai.GonzalezAlberquilla@arm.com 53812109SRekai.GonzalezAlberquilla@arm.com template <typename T> 53912109SRekai.GonzalezAlberquilla@arm.com VecLaneT<T, true> readVecLaneFlat(const RegIndex& reg, int lId) const 54012109SRekai.GonzalezAlberquilla@arm.com { 54112109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].laneView<T>(lId); 54212109SRekai.GonzalezAlberquilla@arm.com } 54312109SRekai.GonzalezAlberquilla@arm.com 54412109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 54512109SRekai.GonzalezAlberquilla@arm.com void setVecLaneFlat(const RegIndex& reg, int lId, const LD& val) 54612109SRekai.GonzalezAlberquilla@arm.com { 54712109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val; 54812109SRekai.GonzalezAlberquilla@arm.com } 54912109SRekai.GonzalezAlberquilla@arm.com 55012109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& reg, 55112109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 55212109SRekai.GonzalezAlberquilla@arm.com { 55312109SRekai.GonzalezAlberquilla@arm.com return vecRegs[reg].as<TheISA::VecElem>()[elemIndex]; 55412109SRekai.GonzalezAlberquilla@arm.com } 55512109SRekai.GonzalezAlberquilla@arm.com 55612109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& reg, const ElemIndex& elemIndex, 55712109SRekai.GonzalezAlberquilla@arm.com const VecElem val) 55812109SRekai.GonzalezAlberquilla@arm.com { 55912109SRekai.GonzalezAlberquilla@arm.com vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val; 56012109SRekai.GonzalezAlberquilla@arm.com } 56112109SRekai.GonzalezAlberquilla@arm.com 5629920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 5639920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 5649920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 5659920Syasuko.eckert@amd.com#else 5669920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 5679920Syasuko.eckert@amd.com { panic("readCCRegFlat w/no CC regs!\n"); } 5689920Syasuko.eckert@amd.com 5699920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 5709920Syasuko.eckert@amd.com { panic("setCCRegFlat w/no CC regs!\n"); } 5719920Syasuko.eckert@amd.com#endif 5722SN/A}; 5732SN/A 5742SN/A 5752190SN/A#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 576