simple_thread.hh revision 11168
12847Sksewell@umich.edu/* 27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2011-2012 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47783SGiacomo.Gabrielli@arm.com * All rights reserved 57783SGiacomo.Gabrielli@arm.com * 67783SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77783SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87783SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97783SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107783SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117783SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127783SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137783SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147783SGiacomo.Gabrielli@arm.com * 155596Sgblack@eecs.umich.edu * Copyright (c) 2001-2006 The Regents of The University of Michigan 162847Sksewell@umich.edu * All rights reserved. 172847Sksewell@umich.edu * 182847Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192847Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202847Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222847Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232847Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242847Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252847Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262847Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272847Sksewell@umich.edu * this software without specific prior written permission. 282847Sksewell@umich.edu * 292847Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302847Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312847Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322847Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332847Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342847Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352847Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362847Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372847Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382847Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392847Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402847Sksewell@umich.edu * 415596Sgblack@eecs.umich.edu * Authors: Steve Reinhardt 422847Sksewell@umich.edu * Nathan Binkert 432847Sksewell@umich.edu */ 442847Sksewell@umich.edu 452847Sksewell@umich.edu#ifndef __CPU_SIMPLE_THREAD_HH__ 462847Sksewell@umich.edu#define __CPU_SIMPLE_THREAD_HH__ 4710835Sandreas.hansson@arm.com 4810835Sandreas.hansson@arm.com#include "arch/decoder.hh" 495596Sgblack@eecs.umich.edu#include "arch/isa.hh" 506658Snate@binkert.org#include "arch/isa_traits.hh" 518229Snate@binkert.org#include "arch/registers.hh" 528229Snate@binkert.org#include "arch/tlb.hh" 535596Sgblack@eecs.umich.edu#include "arch/types.hh" 545596Sgblack@eecs.umich.edu#include "base/types.hh" 559913Ssteve.reinhardt@amd.com#include "config/the_isa.hh" 562847Sksewell@umich.edu#include "cpu/thread_context.hh" 575596Sgblack@eecs.umich.edu#include "cpu/thread_state.hh" 585596Sgblack@eecs.umich.edu#include "debug/CCRegs.hh" 595596Sgblack@eecs.umich.edu#include "debug/FloatRegs.hh" 605596Sgblack@eecs.umich.edu#include "debug/IntRegs.hh" 615596Sgblack@eecs.umich.edu#include "mem/page_table.hh" 625596Sgblack@eecs.umich.edu#include "mem/request.hh" 635596Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 645596Sgblack@eecs.umich.edu#include "sim/eventq.hh" 655596Sgblack@eecs.umich.edu#include "sim/process.hh" 665596Sgblack@eecs.umich.edu#include "sim/serialize.hh" 675596Sgblack@eecs.umich.edu#include "sim/system.hh" 685596Sgblack@eecs.umich.edu 695596Sgblack@eecs.umich.educlass BaseCPU; 705596Sgblack@eecs.umich.educlass CheckerCPU; 715596Sgblack@eecs.umich.edu 725596Sgblack@eecs.umich.educlass FunctionProfile; 735596Sgblack@eecs.umich.educlass ProfileNode; 745596Sgblack@eecs.umich.edu 755596Sgblack@eecs.umich.edunamespace TheISA { 769920Syasuko.eckert@amd.com namespace Kernel { 7710319SAndreas.Sandberg@ARM.com class Statistics; 785596Sgblack@eecs.umich.edu } 795596Sgblack@eecs.umich.edu} 805596Sgblack@eecs.umich.edu 815596Sgblack@eecs.umich.edu/** 825596Sgblack@eecs.umich.edu * The SimpleThread object provides a combination of the ThreadState 838902Sandreas.hansson@arm.com * object and the ThreadContext interface. It implements the 845596Sgblack@eecs.umich.edu * ThreadContext interface so that a ProxyThreadContext class can be 855596Sgblack@eecs.umich.edu * made using SimpleThread as the template parameter (see 865596Sgblack@eecs.umich.edu * thread_context.hh). It adds to the ThreadState object by adding all 875596Sgblack@eecs.umich.edu * the objects needed for simple functional execution, including a 8810417Sandreas.hansson@arm.com * simple architectural register file, and pointers to the ITB and DTB 897720Sgblack@eecs.umich.edu * in full system mode. For CPU models that do not need more advanced 907720Sgblack@eecs.umich.edu * ways to hold state (i.e. a separate physical register file, or 915596Sgblack@eecs.umich.edu * separate fetch and commit PC's), this SimpleThread class provides 925596Sgblack@eecs.umich.edu * all the necessary state for full architecture-level functional 9310417Sandreas.hansson@arm.com * simulation. See the AtomicSimpleCPU or TimingSimpleCPU for 9410417Sandreas.hansson@arm.com * examples. 955596Sgblack@eecs.umich.edu */ 969252Sdjordje.kovacevic@arm.com 979252Sdjordje.kovacevic@arm.comclass SimpleThread : public ThreadState 985596Sgblack@eecs.umich.edu{ 995596Sgblack@eecs.umich.edu protected: 1005596Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 1015596Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 1025596Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 1035596Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 1045596Sgblack@eecs.umich.edu typedef TheISA::CCReg CCReg; 1055596Sgblack@eecs.umich.edu public: 1065596Sgblack@eecs.umich.edu typedef ThreadContext::Status Status; 1075596Sgblack@eecs.umich.edu 1085596Sgblack@eecs.umich.edu protected: 1095596Sgblack@eecs.umich.edu union { 1105596Sgblack@eecs.umich.edu FloatReg f[TheISA::NumFloatRegs]; 1117783SGiacomo.Gabrielli@arm.com FloatRegBits i[TheISA::NumFloatRegs]; 1129046SAli.Saidi@ARM.com } floatRegs; 11310835Sandreas.hansson@arm.com TheISA::IntReg intRegs[TheISA::NumIntRegs]; 1149046SAli.Saidi@ARM.com#ifdef ISA_HAS_CC_REGS 1157783SGiacomo.Gabrielli@arm.com TheISA::CCReg ccRegs[TheISA::NumCCRegs]; 1167783SGiacomo.Gabrielli@arm.com#endif 1177783SGiacomo.Gabrielli@arm.com TheISA::ISA *const isa; // one "instance" of the current ISA. 1187783SGiacomo.Gabrielli@arm.com 11910835Sandreas.hansson@arm.com TheISA::PCState _pcState; 1209046SAli.Saidi@ARM.com 1217783SGiacomo.Gabrielli@arm.com /** Did this instruction execute or is it predicated false */ 1229046SAli.Saidi@ARM.com bool predicate; 1239046SAli.Saidi@ARM.com 1247783SGiacomo.Gabrielli@arm.com public: 1255596Sgblack@eecs.umich.edu std::string name() const 1268471SGiacomo.Gabrielli@arm.com { 1278471SGiacomo.Gabrielli@arm.com return csprintf("%s.[tid:%i]", baseCpu->name(), tc->threadId()); 1289252Sdjordje.kovacevic@arm.com } 1299252Sdjordje.kovacevic@arm.com 1309252Sdjordje.kovacevic@arm.com ProxyThreadContext<SimpleThread> *tc; 1319252Sdjordje.kovacevic@arm.com 1329252Sdjordje.kovacevic@arm.com System *system; 1339252Sdjordje.kovacevic@arm.com 1349252Sdjordje.kovacevic@arm.com TheISA::TLB *itb; 1359527SMatt.Horsnell@arm.com TheISA::TLB *dtb; 1368471SGiacomo.Gabrielli@arm.com 1378471SGiacomo.Gabrielli@arm.com TheISA::Decoder decoder; 1385596Sgblack@eecs.umich.edu 1395596Sgblack@eecs.umich.edu // constructor: initialize SimpleThread from given process structure 1405596Sgblack@eecs.umich.edu // FS 1415596Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1425596Sgblack@eecs.umich.edu TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa, 1435596Sgblack@eecs.umich.edu bool use_kernel_stats = true); 1445596Sgblack@eecs.umich.edu // SE 1455596Sgblack@eecs.umich.edu SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 1465596Sgblack@eecs.umich.edu Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb, 1475596Sgblack@eecs.umich.edu TheISA::ISA *_isa); 1485596Sgblack@eecs.umich.edu 1495596Sgblack@eecs.umich.edu virtual ~SimpleThread(); 1505596Sgblack@eecs.umich.edu 1517783SGiacomo.Gabrielli@arm.com virtual void takeOverFrom(ThreadContext *oldContext); 1529532Sgeoffrey.blake@arm.com 1539532Sgeoffrey.blake@arm.com void regStats(const std::string &name); 1549532Sgeoffrey.blake@arm.com 1559532Sgeoffrey.blake@arm.com void copyState(ThreadContext *oldContext); 1567783SGiacomo.Gabrielli@arm.com 1579532Sgeoffrey.blake@arm.com void serialize(CheckpointOut &cp) const override; 1589532Sgeoffrey.blake@arm.com void unserialize(CheckpointIn &cp) override; 1599532Sgeoffrey.blake@arm.com void startup(); 1609532Sgeoffrey.blake@arm.com 1619532Sgeoffrey.blake@arm.com /*************************************************************** 1629532Sgeoffrey.blake@arm.com * SimpleThread functions to provide CPU with access to various 1639532Sgeoffrey.blake@arm.com * state. 1649046SAli.Saidi@ARM.com **************************************************************/ 1657783SGiacomo.Gabrielli@arm.com 1667783SGiacomo.Gabrielli@arm.com /** Returns the pointer to this SimpleThread's ThreadContext. Used 1677783SGiacomo.Gabrielli@arm.com * when a ThreadContext must be passed to objects outside of the 1685596Sgblack@eecs.umich.edu * CPU. 1695596Sgblack@eecs.umich.edu */ 1705596Sgblack@eecs.umich.edu ThreadContext *getTC() { return tc; } 1715596Sgblack@eecs.umich.edu 1725596Sgblack@eecs.umich.edu void demapPage(Addr vaddr, uint64_t asn) 1735596Sgblack@eecs.umich.edu { 1745596Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1755596Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1769918Ssteve.reinhardt@amd.com } 1775596Sgblack@eecs.umich.edu 1785596Sgblack@eecs.umich.edu void demapInstPage(Addr vaddr, uint64_t asn) 1795596Sgblack@eecs.umich.edu { 1805596Sgblack@eecs.umich.edu itb->demapPage(vaddr, asn); 1815596Sgblack@eecs.umich.edu } 1825596Sgblack@eecs.umich.edu 1835596Sgblack@eecs.umich.edu void demapDataPage(Addr vaddr, uint64_t asn) 1845596Sgblack@eecs.umich.edu { 1855596Sgblack@eecs.umich.edu dtb->demapPage(vaddr, asn); 1869918Ssteve.reinhardt@amd.com } 1877783SGiacomo.Gabrielli@arm.com 1887783SGiacomo.Gabrielli@arm.com void dumpFuncProfile(); 1897783SGiacomo.Gabrielli@arm.com 1907783SGiacomo.Gabrielli@arm.com Fault hwrei(); 1917783SGiacomo.Gabrielli@arm.com 1927783SGiacomo.Gabrielli@arm.com bool simPalCheck(int palFunc); 1937783SGiacomo.Gabrielli@arm.com 1947783SGiacomo.Gabrielli@arm.com /******************************************* 1957783SGiacomo.Gabrielli@arm.com * ThreadContext interface functions. 1967783SGiacomo.Gabrielli@arm.com ******************************************/ 1979382SAli.Saidi@ARM.com 1989382SAli.Saidi@ARM.com BaseCPU *getCpuPtr() { return baseCpu; } 1997783SGiacomo.Gabrielli@arm.com 2007783SGiacomo.Gabrielli@arm.com TheISA::TLB *getITBPtr() { return itb; } 2017783SGiacomo.Gabrielli@arm.com 2027783SGiacomo.Gabrielli@arm.com TheISA::TLB *getDTBPtr() { return dtb; } 2037783SGiacomo.Gabrielli@arm.com 2049382SAli.Saidi@ARM.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 2055596Sgblack@eecs.umich.edu 2065596Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return &decoder; } 2077848SAli.Saidi@ARM.com 2087848SAli.Saidi@ARM.com System *getSystemPtr() { return system; } 20910935Snilay@cs.wisc.edu 2107848SAli.Saidi@ARM.com Status status() const { return _status; } 2117848SAli.Saidi@ARM.com 2129913Ssteve.reinhardt@amd.com void setStatus(Status newStatus) { _status = newStatus; } 2139913Ssteve.reinhardt@amd.com 2149913Ssteve.reinhardt@amd.com /// Set the status to Active. 2159913Ssteve.reinhardt@amd.com void activate(); 2169913Ssteve.reinhardt@amd.com 2179913Ssteve.reinhardt@amd.com /// Set the status to Suspended. 2189913Ssteve.reinhardt@amd.com void suspend(); 2199913Ssteve.reinhardt@amd.com 2209913Ssteve.reinhardt@amd.com /// Set the status to Halted. 2219913Ssteve.reinhardt@amd.com void halt(); 2229913Ssteve.reinhardt@amd.com 2239920Syasuko.eckert@amd.com void copyArchRegs(ThreadContext *tc); 2249920Syasuko.eckert@amd.com 2259920Syasuko.eckert@amd.com void clearArchRegs() 2269920Syasuko.eckert@amd.com { 2279913Ssteve.reinhardt@amd.com _pcState = 0; 2289913Ssteve.reinhardt@amd.com memset(intRegs, 0, sizeof(intRegs)); 2299913Ssteve.reinhardt@amd.com memset(floatRegs.i, 0, sizeof(floatRegs.i)); 2309913Ssteve.reinhardt@amd.com#ifdef ISA_HAS_CC_REGS 2317848SAli.Saidi@ARM.com memset(ccRegs, 0, sizeof(ccRegs)); 2327848SAli.Saidi@ARM.com#endif 2335702Ssaidi@eecs.umich.edu isa->clear(); 2345702Ssaidi@eecs.umich.edu } 2355596Sgblack@eecs.umich.edu 23610379Sandreas.hansson@arm.com // 2375702Ssaidi@eecs.umich.edu // New accessors for new decoder. 2388557Sgblack@eecs.umich.edu // 2398557Sgblack@eecs.umich.edu uint64_t readIntReg(int reg_idx) 2405596Sgblack@eecs.umich.edu { 2412847Sksewell@umich.edu int flatIndex = isa->flattenIntIndex(reg_idx); 2425596Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2435596Sgblack@eecs.umich.edu uint64_t regVal(readIntRegFlat(flatIndex)); 2445596Sgblack@eecs.umich.edu DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", 2455596Sgblack@eecs.umich.edu reg_idx, flatIndex, regVal); 2465596Sgblack@eecs.umich.edu return regVal; 2475596Sgblack@eecs.umich.edu } 2485596Sgblack@eecs.umich.edu 2495596Sgblack@eecs.umich.edu FloatReg readFloatReg(int reg_idx) 2505596Sgblack@eecs.umich.edu { 2515596Sgblack@eecs.umich.edu int flatIndex = isa->flattenFloatIndex(reg_idx); 2525596Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2535596Sgblack@eecs.umich.edu FloatReg regVal(readFloatRegFlat(flatIndex)); 2545596Sgblack@eecs.umich.edu DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", 25510319SAndreas.Sandberg@ARM.com reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); 2565596Sgblack@eecs.umich.edu return regVal; 2575596Sgblack@eecs.umich.edu } 2585596Sgblack@eecs.umich.edu 2595596Sgblack@eecs.umich.edu FloatRegBits readFloatRegBits(int reg_idx) 2605596Sgblack@eecs.umich.edu { 2615596Sgblack@eecs.umich.edu int flatIndex = isa->flattenFloatIndex(reg_idx); 2625596Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 2635596Sgblack@eecs.umich.edu FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); 2645596Sgblack@eecs.umich.edu DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", 2655596Sgblack@eecs.umich.edu reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); 2665596Sgblack@eecs.umich.edu return regVal; 2675596Sgblack@eecs.umich.edu } 2685596Sgblack@eecs.umich.edu 2695596Sgblack@eecs.umich.edu CCReg readCCReg(int reg_idx) 27010319SAndreas.Sandberg@ARM.com { 2719920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 2729920Syasuko.eckert@amd.com int flatIndex = isa->flattenCCIndex(reg_idx); 2739920Syasuko.eckert@amd.com assert(0 <= flatIndex); 2749920Syasuko.eckert@amd.com assert(flatIndex < TheISA::NumCCRegs); 2755596Sgblack@eecs.umich.edu uint64_t regVal(readCCRegFlat(flatIndex)); 2765596Sgblack@eecs.umich.edu DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", 2775596Sgblack@eecs.umich.edu reg_idx, flatIndex, regVal); 27810319SAndreas.Sandberg@ARM.com return regVal; 2795596Sgblack@eecs.umich.edu#else 2805596Sgblack@eecs.umich.edu panic("Tried to read a CC register."); 2815596Sgblack@eecs.umich.edu return 0; 2825596Sgblack@eecs.umich.edu#endif 2835596Sgblack@eecs.umich.edu } 2845596Sgblack@eecs.umich.edu 2855596Sgblack@eecs.umich.edu void setIntReg(int reg_idx, uint64_t val) 2865596Sgblack@eecs.umich.edu { 2875596Sgblack@eecs.umich.edu int flatIndex = isa->flattenIntIndex(reg_idx); 2885596Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumIntRegs); 2895596Sgblack@eecs.umich.edu DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", 2905596Sgblack@eecs.umich.edu reg_idx, flatIndex, val); 2915596Sgblack@eecs.umich.edu setIntRegFlat(flatIndex, val); 2925596Sgblack@eecs.umich.edu } 2935596Sgblack@eecs.umich.edu 2945596Sgblack@eecs.umich.edu void setFloatReg(int reg_idx, FloatReg val) 2955596Sgblack@eecs.umich.edu { 2965596Sgblack@eecs.umich.edu int flatIndex = isa->flattenFloatIndex(reg_idx); 29710319SAndreas.Sandberg@ARM.com assert(flatIndex < TheISA::NumFloatRegs); 2989920Syasuko.eckert@amd.com setFloatRegFlat(flatIndex, val); 2999920Syasuko.eckert@amd.com DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", 3009920Syasuko.eckert@amd.com reg_idx, flatIndex, val, floatRegs.i[flatIndex]); 3019920Syasuko.eckert@amd.com } 3029920Syasuko.eckert@amd.com 3035596Sgblack@eecs.umich.edu void setFloatRegBits(int reg_idx, FloatRegBits val) 30410319SAndreas.Sandberg@ARM.com { 3055596Sgblack@eecs.umich.edu int flatIndex = isa->flattenFloatIndex(reg_idx); 3065596Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumFloatRegs); 3075596Sgblack@eecs.umich.edu // XXX: Fix array out of bounds compiler error for gem5.fast 3085596Sgblack@eecs.umich.edu // when checkercpu enabled 3095596Sgblack@eecs.umich.edu if (flatIndex < TheISA::NumFloatRegs) 31010319SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flatIndex, val); 3115596Sgblack@eecs.umich.edu DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", 3125596Sgblack@eecs.umich.edu reg_idx, flatIndex, val, floatRegs.f[flatIndex]); 3135596Sgblack@eecs.umich.edu } 3145596Sgblack@eecs.umich.edu 3155596Sgblack@eecs.umich.edu void setCCReg(int reg_idx, CCReg val) 3165596Sgblack@eecs.umich.edu { 3175596Sgblack@eecs.umich.edu#ifdef ISA_HAS_CC_REGS 3185596Sgblack@eecs.umich.edu int flatIndex = isa->flattenCCIndex(reg_idx); 3195596Sgblack@eecs.umich.edu assert(flatIndex < TheISA::NumCCRegs); 3205596Sgblack@eecs.umich.edu DPRINTF(CCRegs, "Setting CC reg %d (%d) to %#x.\n", 3215596Sgblack@eecs.umich.edu reg_idx, flatIndex, val); 3225596Sgblack@eecs.umich.edu setCCRegFlat(flatIndex, val); 3235596Sgblack@eecs.umich.edu#else 3245596Sgblack@eecs.umich.edu panic("Tried to set a CC register."); 3255596Sgblack@eecs.umich.edu#endif 3265596Sgblack@eecs.umich.edu } 3275596Sgblack@eecs.umich.edu 3285596Sgblack@eecs.umich.edu TheISA::PCState 3295596Sgblack@eecs.umich.edu pcState() 3305596Sgblack@eecs.umich.edu { 3315596Sgblack@eecs.umich.edu return _pcState; 3325596Sgblack@eecs.umich.edu } 3335596Sgblack@eecs.umich.edu 3345596Sgblack@eecs.umich.edu void 3355596Sgblack@eecs.umich.edu pcState(const TheISA::PCState &val) 3365596Sgblack@eecs.umich.edu { 3375596Sgblack@eecs.umich.edu _pcState = val; 338 } 339 340 void 341 pcStateNoRecord(const TheISA::PCState &val) 342 { 343 _pcState = val; 344 } 345 346 Addr 347 instAddr() 348 { 349 return _pcState.instAddr(); 350 } 351 352 Addr 353 nextInstAddr() 354 { 355 return _pcState.nextInstAddr(); 356 } 357 358 MicroPC 359 microPC() 360 { 361 return _pcState.microPC(); 362 } 363 364 bool readPredicate() 365 { 366 return predicate; 367 } 368 369 void setPredicate(bool val) 370 { 371 predicate = val; 372 } 373 374 MiscReg 375 readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const 376 { 377 return isa->readMiscRegNoEffect(misc_reg); 378 } 379 380 MiscReg 381 readMiscReg(int misc_reg, ThreadID tid = 0) 382 { 383 return isa->readMiscReg(misc_reg, tc); 384 } 385 386 void 387 setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0) 388 { 389 return isa->setMiscRegNoEffect(misc_reg, val); 390 } 391 392 void 393 setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0) 394 { 395 return isa->setMiscReg(misc_reg, val, tc); 396 } 397 398 int 399 flattenIntIndex(int reg) 400 { 401 return isa->flattenIntIndex(reg); 402 } 403 404 int 405 flattenFloatIndex(int reg) 406 { 407 return isa->flattenFloatIndex(reg); 408 } 409 410 int 411 flattenCCIndex(int reg) 412 { 413 return isa->flattenCCIndex(reg); 414 } 415 416 int 417 flattenMiscIndex(int reg) 418 { 419 return isa->flattenMiscIndex(reg); 420 } 421 422 unsigned readStCondFailures() { return storeCondFailures; } 423 424 void setStCondFailures(unsigned sc_failures) 425 { storeCondFailures = sc_failures; } 426 427 void syscall(int64_t callnum) 428 { 429 process->syscall(callnum, tc); 430 } 431 432 uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } 433 void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } 434 435 FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } 436 void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } 437 438 FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } 439 void setFloatRegBitsFlat(int idx, FloatRegBits val) { 440 floatRegs.i[idx] = val; 441 } 442 443#ifdef ISA_HAS_CC_REGS 444 CCReg readCCRegFlat(int idx) { return ccRegs[idx]; } 445 void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; } 446#else 447 CCReg readCCRegFlat(int idx) 448 { panic("readCCRegFlat w/no CC regs!\n"); } 449 450 void setCCRegFlat(int idx, CCReg val) 451 { panic("setCCRegFlat w/no CC regs!\n"); } 452#endif 453}; 454 455 456#endif // __CPU_CPU_EXEC_CONTEXT_HH__ 457