simple_thread.cc revision 9384:877293183bdf 
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Lisa Hsu
31 *          Kevin Lim
32 */
33
34#include <string>
35
36#include "arch/isa_traits.hh"
37#include "arch/kernel_stats.hh"
38#include "arch/stacktrace.hh"
39#include "arch/utility.hh"
40#include "base/callback.hh"
41#include "base/cprintf.hh"
42#include "base/output.hh"
43#include "base/trace.hh"
44#include "config/the_isa.hh"
45#include "cpu/base.hh"
46#include "cpu/profile.hh"
47#include "cpu/quiesce_event.hh"
48#include "cpu/simple_thread.hh"
49#include "cpu/thread_context.hh"
50#include "mem/fs_translating_port_proxy.hh"
51#include "mem/se_translating_port_proxy.hh"
52#include "params/BaseCPU.hh"
53#include "sim/full_system.hh"
54#include "sim/process.hh"
55#include "sim/serialize.hh"
56#include "sim/sim_exit.hh"
57#include "sim/system.hh"
58
59using namespace std;
60
61// constructor
62SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
63                           Process *_process, TheISA::TLB *_itb,
64                           TheISA::TLB *_dtb, TheISA::ISA *_isa)
65    : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
66      itb(_itb), dtb(_dtb)
67{
68    clearArchRegs();
69    tc = new ProxyThreadContext<SimpleThread>(this);
70}
71
72SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
73                           TheISA::TLB *_itb, TheISA::TLB *_dtb,
74                           TheISA::ISA *_isa, bool use_kernel_stats)
75    : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
76      dtb(_dtb)
77{
78    tc = new ProxyThreadContext<SimpleThread>(this);
79
80    quiesceEvent = new EndQuiesceEvent(tc);
81
82    clearArchRegs();
83
84    if (baseCpu->params()->profile) {
85        profile = new FunctionProfile(system->kernelSymtab);
86        Callback *cb =
87            new MakeCallback<SimpleThread,
88            &SimpleThread::dumpFuncProfile>(this);
89        registerExitCallback(cb);
90    }
91
92    // let's fill with a dummy node for now so we don't get a segfault
93    // on the first cycle when there's no node available.
94    static ProfileNode dummyNode;
95    profileNode = &dummyNode;
96    profilePC = 3;
97
98    if (use_kernel_stats)
99        kernelStats = new TheISA::Kernel::Statistics(system);
100}
101
102SimpleThread::SimpleThread()
103    : ThreadState(NULL, -1, NULL), isa(NULL)
104{
105    tc = new ProxyThreadContext<SimpleThread>(this);
106}
107
108SimpleThread::~SimpleThread()
109{
110    delete tc;
111}
112
113void
114SimpleThread::takeOverFrom(ThreadContext *oldContext)
115{
116    // some things should already be set up
117    if (FullSystem)
118        assert(system == oldContext->getSystemPtr());
119    assert(process == oldContext->getProcessPtr());
120
121    copyState(oldContext);
122    if (FullSystem) {
123        EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
124        if (quiesce) {
125            // Point the quiesce event's TC at this TC so that it wakes up
126            // the proper CPU.
127            quiesce->tc = tc;
128        }
129        if (quiesceEvent) {
130            quiesceEvent->tc = tc;
131        }
132
133        TheISA::Kernel::Statistics *stats = oldContext->getKernelStats();
134        if (stats) {
135            kernelStats = stats;
136        }
137    }
138
139    storeCondFailures = 0;
140
141    oldContext->setStatus(ThreadContext::Halted);
142}
143
144void
145SimpleThread::copyTC(ThreadContext *context)
146{
147    copyState(context);
148
149    if (FullSystem) {
150        EndQuiesceEvent *quiesce = context->getQuiesceEvent();
151        if (quiesce) {
152            quiesceEvent = quiesce;
153        }
154        TheISA::Kernel::Statistics *stats = context->getKernelStats();
155        if (stats) {
156            kernelStats = stats;
157        }
158    }
159}
160
161void
162SimpleThread::copyState(ThreadContext *oldContext)
163{
164    // copy over functional state
165    _status = oldContext->status();
166    copyArchRegs(oldContext);
167    if (FullSystem)
168        funcExeInst = oldContext->readFuncExeInst();
169
170    _threadId = oldContext->threadId();
171    _contextId = oldContext->contextId();
172}
173
174void
175SimpleThread::serialize(ostream &os)
176{
177    ThreadState::serialize(os);
178    SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
179    SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
180    _pcState.serialize(os);
181    // thread_num and cpu_id are deterministic from the config
182
183    //
184    // Now must serialize all the ISA dependent state
185    //
186    isa->serialize(baseCpu, os);
187}
188
189
190void
191SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
192{
193    ThreadState::unserialize(cp, section);
194    UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
195    UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
196    _pcState.unserialize(cp, section);
197    // thread_num and cpu_id are deterministic from the config
198
199    //
200    // Now must unserialize all the ISA dependent state
201    //
202    isa->unserialize(baseCpu, cp, section);
203}
204
205void
206SimpleThread::dumpFuncProfile()
207{
208    std::ostream *os = simout.create(csprintf("profile.%s.dat",
209                                              baseCpu->name()));
210    profile->dump(tc, *os);
211}
212
213void
214SimpleThread::activate(Cycles delay)
215{
216    if (status() == ThreadContext::Active)
217        return;
218
219    lastActivate = curTick();
220
221//    if (status() == ThreadContext::Unallocated) {
222//      cpu->activateWhenReady(_threadId);
223//      return;
224//   }
225
226    _status = ThreadContext::Active;
227
228    // status() == Suspended
229    baseCpu->activateContext(_threadId, delay);
230}
231
232void
233SimpleThread::suspend()
234{
235    if (status() == ThreadContext::Suspended)
236        return;
237
238    lastActivate = curTick();
239    lastSuspend = curTick();
240    _status = ThreadContext::Suspended;
241    baseCpu->suspendContext(_threadId);
242}
243
244
245void
246SimpleThread::halt()
247{
248    if (status() == ThreadContext::Halted)
249        return;
250
251    _status = ThreadContext::Halted;
252    baseCpu->haltContext(_threadId);
253}
254
255
256void
257SimpleThread::regStats(const string &name)
258{
259    if (FullSystem && kernelStats)
260        kernelStats->regStats(name + ".kern");
261}
262
263void
264SimpleThread::copyArchRegs(ThreadContext *src_tc)
265{
266    TheISA::copyRegs(src_tc, tc);
267}
268
269