simple_thread.cc revision 13759:9941fca869a9 
1/*
2 * Copyright (c) 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 *          Nathan Binkert
42 *          Lisa Hsu
43 *          Kevin Lim
44 */
45
46#include "cpu/simple_thread.hh"
47
48#include <string>
49
50#include "arch/isa_traits.hh"
51#include "arch/kernel_stats.hh"
52#include "arch/stacktrace.hh"
53#include "arch/utility.hh"
54#include "base/callback.hh"
55#include "base/cprintf.hh"
56#include "base/output.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/base.hh"
60#include "cpu/profile.hh"
61#include "cpu/quiesce_event.hh"
62#include "cpu/thread_context.hh"
63#include "mem/fs_translating_port_proxy.hh"
64#include "mem/se_translating_port_proxy.hh"
65#include "params/BaseCPU.hh"
66#include "sim/faults.hh"
67#include "sim/full_system.hh"
68#include "sim/process.hh"
69#include "sim/serialize.hh"
70#include "sim/sim_exit.hh"
71#include "sim/system.hh"
72
73using namespace std;
74
75// constructor
76SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
77                           Process *_process, BaseTLB *_itb,
78                           BaseTLB *_dtb, TheISA::ISA *_isa)
79    : ThreadState(_cpu, _thread_num, _process), isa(_isa),
80      predicate(false), system(_sys),
81      itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
82{
83    clearArchRegs();
84    tc = new ProxyThreadContext<SimpleThread>(this);
85    quiesceEvent = new EndQuiesceEvent(tc);
86}
87
88SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
89                           BaseTLB *_itb, BaseTLB *_dtb,
90                           TheISA::ISA *_isa, bool use_kernel_stats)
91    : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
92      dtb(_dtb), decoder(TheISA::Decoder(_isa))
93{
94    tc = new ProxyThreadContext<SimpleThread>(this);
95
96    quiesceEvent = new EndQuiesceEvent(tc);
97
98    clearArchRegs();
99
100    if (baseCpu->params()->profile) {
101        profile = new FunctionProfile(system->kernelSymtab);
102        Callback *cb =
103            new MakeCallback<SimpleThread,
104            &SimpleThread::dumpFuncProfile>(this);
105        registerExitCallback(cb);
106    }
107
108    // let's fill with a dummy node for now so we don't get a segfault
109    // on the first cycle when there's no node available.
110    static ProfileNode dummyNode;
111    profileNode = &dummyNode;
112    profilePC = 3;
113
114    if (use_kernel_stats)
115        kernelStats = new TheISA::Kernel::Statistics();
116}
117
118SimpleThread::~SimpleThread()
119{
120    delete tc;
121}
122
123void
124SimpleThread::takeOverFrom(ThreadContext *oldContext)
125{
126    ::takeOverFrom(*tc, *oldContext);
127    decoder.takeOverFrom(oldContext->getDecoderPtr());
128
129    kernelStats = oldContext->getKernelStats();
130    funcExeInst = oldContext->readFuncExeInst();
131    storeCondFailures = 0;
132}
133
134void
135SimpleThread::copyState(ThreadContext *oldContext)
136{
137    // copy over functional state
138    _status = oldContext->status();
139    copyArchRegs(oldContext);
140    if (FullSystem)
141        funcExeInst = oldContext->readFuncExeInst();
142
143    _threadId = oldContext->threadId();
144    _contextId = oldContext->contextId();
145}
146
147void
148SimpleThread::serialize(CheckpointOut &cp) const
149{
150    ThreadState::serialize(cp);
151    ::serialize(*tc, cp);
152}
153
154
155void
156SimpleThread::unserialize(CheckpointIn &cp)
157{
158    ThreadState::unserialize(cp);
159    ::unserialize(*tc, cp);
160}
161
162void
163SimpleThread::startup()
164{
165    isa->startup(tc);
166}
167
168void
169SimpleThread::dumpFuncProfile()
170{
171    OutputStream *os(simout.create(csprintf("profile.%s.dat", baseCpu->name())));
172    profile->dump(tc, *os->stream());
173    simout.close(os);
174}
175
176void
177SimpleThread::activate()
178{
179    if (status() == ThreadContext::Active)
180        return;
181
182    lastActivate = curTick();
183    _status = ThreadContext::Active;
184    baseCpu->activateContext(_threadId);
185}
186
187void
188SimpleThread::suspend()
189{
190    if (status() == ThreadContext::Suspended)
191        return;
192
193    lastActivate = curTick();
194    lastSuspend = curTick();
195    _status = ThreadContext::Suspended;
196    baseCpu->suspendContext(_threadId);
197}
198
199
200void
201SimpleThread::halt()
202{
203    if (status() == ThreadContext::Halted)
204        return;
205
206    _status = ThreadContext::Halted;
207    baseCpu->haltContext(_threadId);
208}
209
210
211void
212SimpleThread::regStats(const string &name)
213{
214    if (FullSystem && kernelStats)
215        kernelStats->regStats(name + ".kern");
216}
217
218void
219SimpleThread::copyArchRegs(ThreadContext *src_tc)
220{
221    TheISA::copyRegs(src_tc, tc);
222}
223
224// The following methods are defined in src/arch/alpha/ev5.cc for
225// Alpha.
226#if THE_ISA != ALPHA_ISA
227Fault
228SimpleThread::hwrei()
229{
230    return NoFault;
231}
232
233bool
234SimpleThread::simPalCheck(int palFunc)
235{
236    return true;
237}
238#endif
239