simple_thread.cc revision 4400
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 371717SN/A#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392680SN/A#include "cpu/thread_context.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 423565Sgblack@eecs.umich.edu#include "arch/kernel_stats.hh" 431917SN/A#include "base/callback.hh" 441070SN/A#include "base/cprintf.hh" 451917SN/A#include "base/output.hh" 462188SN/A#include "base/trace.hh" 471917SN/A#include "cpu/profile.hh" 482290SN/A#include "cpu/quiesce_event.hh" 491070SN/A#include "sim/serialize.hh" 501917SN/A#include "sim/sim_exit.hh" 512170SN/A#include "arch/stacktrace.hh" 522SN/A#else 53360SN/A#include "sim/process.hh" 542519SN/A#include "sim/system.hh" 552420SN/A#include "mem/translating_port.hh" 562SN/A#endif 572SN/A 582SN/Ausing namespace std; 592SN/A 602SN/A// constructor 611858SN/A#if FULL_SYSTEM 622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 633453Sgblack@eecs.umich.edu TheISA::ITB *_itb, TheISA::DTB *_dtb, 642683Sktlim@umich.edu bool use_kernel_stats) 653402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 662683Sktlim@umich.edu dtb(_dtb) 672521SN/A 682SN/A{ 692683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 702190SN/A 712680SN/A quiesceEvent = new EndQuiesceEvent(tc); 722290SN/A 732526SN/A regs.clear(); 741917SN/A 751917SN/A if (cpu->params->profile) { 761982SN/A profile = new FunctionProfile(system->kernelSymtab); 771917SN/A Callback *cb = 782683Sktlim@umich.edu new MakeCallback<SimpleThread, 792683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 801917SN/A registerExitCallback(cb); 811917SN/A } 821917SN/A 831917SN/A // let's fill with a dummy node for now so we don't get a segfault 841917SN/A // on the first cycle when there's no node available. 851917SN/A static ProfileNode dummyNode; 861917SN/A profileNode = &dummyNode; 871917SN/A profilePC = 3; 882521SN/A 892341SN/A if (use_kernel_stats) { 903548Sgblack@eecs.umich.edu kernelStats = new TheISA::Kernel::Statistics(system); 912341SN/A } else { 922341SN/A kernelStats = NULL; 932341SN/A } 942SN/A} 952SN/A#else 962683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, 973402Sktlim@umich.edu Process *_process, int _asid) 983402Sktlim@umich.edu : ThreadState(_cpu, -1, _thread_num, _process, _asid), 992683Sktlim@umich.edu cpu(_cpu) 1002SN/A{ 1012526SN/A regs.clear(); 1022683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1032SN/A} 1042190SN/A 1052862Sktlim@umich.edu#endif 1062862Sktlim@umich.edu 1072864Sktlim@umich.eduSimpleThread::SimpleThread() 1082862Sktlim@umich.edu#if FULL_SYSTEM 1093402Sktlim@umich.edu : ThreadState(NULL, -1, -1) 1102862Sktlim@umich.edu#else 1113402Sktlim@umich.edu : ThreadState(NULL, -1, -1, NULL, -1) 1122862Sktlim@umich.edu#endif 1132190SN/A{ 1142683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1152862Sktlim@umich.edu regs.clear(); 1162190SN/A} 1172190SN/A 1182683Sktlim@umich.eduSimpleThread::~SimpleThread() 1191070SN/A{ 1203486Sktlim@umich.edu#if FULL_SYSTEM 1213486Sktlim@umich.edu delete physPort; 1223486Sktlim@umich.edu delete virtPort; 1233486Sktlim@umich.edu#endif 1242680SN/A delete tc; 1251070SN/A} 1261070SN/A 1271917SN/Avoid 1282683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 129180SN/A{ 130180SN/A // some things should already be set up 1311858SN/A#if FULL_SYSTEM 1322235SN/A assert(system == oldContext->getSystemPtr()); 133180SN/A#else 1342235SN/A assert(process == oldContext->getProcessPtr()); 135180SN/A#endif 136180SN/A 1372862Sktlim@umich.edu copyState(oldContext); 1382862Sktlim@umich.edu#if FULL_SYSTEM 1392313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1402313SN/A if (quiesce) { 1412680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1422313SN/A // the proper CPU. 1432680SN/A quiesce->tc = tc; 1442313SN/A } 1452313SN/A if (quiesceEvent) { 1462680SN/A quiesceEvent->tc = tc; 1472313SN/A } 1482361SN/A 1493548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); 1502361SN/A if (stats) { 1512361SN/A kernelStats = stats; 1522361SN/A } 1532235SN/A#endif 154180SN/A 155180SN/A storeCondFailures = 0; 156180SN/A 1572680SN/A oldContext->setStatus(ThreadContext::Unallocated); 158180SN/A} 159180SN/A 1602SN/Avoid 1612864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context) 1622864Sktlim@umich.edu{ 1632864Sktlim@umich.edu copyState(context); 1642864Sktlim@umich.edu 1652864Sktlim@umich.edu#if FULL_SYSTEM 1662864Sktlim@umich.edu EndQuiesceEvent *quiesce = context->getQuiesceEvent(); 1672864Sktlim@umich.edu if (quiesce) { 1682864Sktlim@umich.edu quiesceEvent = quiesce; 1692864Sktlim@umich.edu } 1703548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *stats = context->getKernelStats(); 1712864Sktlim@umich.edu if (stats) { 1722864Sktlim@umich.edu kernelStats = stats; 1732864Sktlim@umich.edu } 1742864Sktlim@umich.edu#endif 1752864Sktlim@umich.edu} 1762864Sktlim@umich.edu 1772864Sktlim@umich.eduvoid 1782862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext) 1792862Sktlim@umich.edu{ 1802862Sktlim@umich.edu // copy over functional state 1812862Sktlim@umich.edu _status = oldContext->status(); 1822862Sktlim@umich.edu copyArchRegs(oldContext); 1832862Sktlim@umich.edu cpuId = oldContext->readCpuId(); 1842862Sktlim@umich.edu#if !FULL_SYSTEM 1852862Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1862862Sktlim@umich.edu#endif 1872915Sktlim@umich.edu inst = oldContext->getInst(); 1882862Sktlim@umich.edu} 1892862Sktlim@umich.edu 1902862Sktlim@umich.eduvoid 1912683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 192217SN/A{ 1932862Sktlim@umich.edu ThreadState::serialize(os); 194223SN/A regs.serialize(os); 195223SN/A // thread_num and cpu_id are deterministic from the config 196217SN/A} 197217SN/A 198217SN/A 199217SN/Avoid 2002683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 201217SN/A{ 2022862Sktlim@umich.edu ThreadState::unserialize(cp, section); 203237SN/A regs.unserialize(cp, section); 204223SN/A // thread_num and cpu_id are deterministic from the config 205217SN/A} 206217SN/A 2072683Sktlim@umich.edu#if FULL_SYSTEM 2082683Sktlim@umich.eduvoid 2092683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2102683Sktlim@umich.edu{ 2112683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2122683Sktlim@umich.edu profile->dump(tc, *os); 2132683Sktlim@umich.edu} 2142683Sktlim@umich.edu#endif 215217SN/A 216217SN/Avoid 2172683Sktlim@umich.eduSimpleThread::activate(int delay) 2182SN/A{ 2192680SN/A if (status() == ThreadContext::Active) 2202SN/A return; 2212SN/A 2222188SN/A lastActivate = curTick; 2232188SN/A 2244400Srdreslin@umich.edu// if (status() == ThreadContext::Unallocated) { 2254400Srdreslin@umich.edu// cpu->activateWhenReady(tid); 2264400Srdreslin@umich.edu// return; 2274400Srdreslin@umich.edu// } 2282290SN/A 2292680SN/A _status = ThreadContext::Active; 2302290SN/A 2312290SN/A // status() == Suspended 2322683Sktlim@umich.edu cpu->activateContext(tid, delay); 233393SN/A} 234393SN/A 235393SN/Avoid 2362683Sktlim@umich.eduSimpleThread::suspend() 237393SN/A{ 2382680SN/A if (status() == ThreadContext::Suspended) 239393SN/A return; 240393SN/A 2412188SN/A lastActivate = curTick; 2422188SN/A lastSuspend = curTick; 2432188SN/A/* 2441858SN/A#if FULL_SYSTEM 2452SN/A // Don't change the status from active if there are pending interrupts 246393SN/A if (cpu->check_interrupts()) { 2472680SN/A assert(status() == ThreadContext::Active); 2482SN/A return; 2492SN/A } 2502SN/A#endif 2512188SN/A*/ 2522680SN/A _status = ThreadContext::Suspended; 2532683Sktlim@umich.edu cpu->suspendContext(tid); 2542SN/A} 2552SN/A 2562SN/Avoid 2572683Sktlim@umich.eduSimpleThread::deallocate() 258393SN/A{ 2592680SN/A if (status() == ThreadContext::Unallocated) 260393SN/A return; 261393SN/A 2622680SN/A _status = ThreadContext::Unallocated; 2632683Sktlim@umich.edu cpu->deallocateContext(tid); 264393SN/A} 265393SN/A 266393SN/Avoid 2672683Sktlim@umich.eduSimpleThread::halt() 268393SN/A{ 2692680SN/A if (status() == ThreadContext::Halted) 270393SN/A return; 271393SN/A 2722680SN/A _status = ThreadContext::Halted; 2732683Sktlim@umich.edu cpu->haltContext(tid); 274393SN/A} 275393SN/A 276393SN/A 277393SN/Avoid 2782683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2792SN/A{ 2802330SN/A#if FULL_SYSTEM 2812341SN/A if (kernelStats) 2822341SN/A kernelStats->regStats(name + ".kern"); 2832330SN/A#endif 2842SN/A} 285716SN/A 286716SN/Avoid 2872683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2882190SN/A{ 2892680SN/A TheISA::copyRegs(src_tc, tc); 2902190SN/A} 2912190SN/A 2922521SN/A#if FULL_SYSTEM 2932521SN/AVirtualPort* 2942683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc) 2952521SN/A{ 2962680SN/A if (!src_tc) 2972521SN/A return virtPort; 2982521SN/A 2993486Sktlim@umich.edu VirtualPort *vp = new VirtualPort("tc-vport", src_tc); 3003675Sktlim@umich.edu connectToMemFunc(vp); 3012521SN/A return vp; 3022521SN/A} 3032521SN/A 3042521SN/Avoid 3052683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp) 3062521SN/A{ 3072684Ssaidi@eecs.umich.edu if (vp != virtPort) { 3084217Ssaidi@eecs.umich.edu vp->removeConn(); 3092684Ssaidi@eecs.umich.edu delete vp; 3102684Ssaidi@eecs.umich.edu } 3112521SN/A} 3122521SN/A 3132521SN/A#endif 3142521SN/A 315