simple_thread.cc revision 3453
12SN/A/*
22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Steve Reinhardt
292665SN/A *          Nathan Binkert
302665SN/A *          Lisa Hsu
312665SN/A *          Kevin Lim
322SN/A */
332SN/A
342SN/A#include <string>
352SN/A
362465SN/A#include "arch/isa_traits.hh"
371717SN/A#include "cpu/base.hh"
382683Sktlim@umich.edu#include "cpu/simple_thread.hh"
392680SN/A#include "cpu/thread_context.hh"
402SN/A
411858SN/A#if FULL_SYSTEM
421917SN/A#include "base/callback.hh"
431070SN/A#include "base/cprintf.hh"
441917SN/A#include "base/output.hh"
452188SN/A#include "base/trace.hh"
461917SN/A#include "cpu/profile.hh"
472290SN/A#include "cpu/quiesce_event.hh"
481070SN/A#include "kern/kernel_stats.hh"
491070SN/A#include "sim/serialize.hh"
501917SN/A#include "sim/sim_exit.hh"
512170SN/A#include "arch/stacktrace.hh"
522SN/A#else
53360SN/A#include "sim/process.hh"
542519SN/A#include "sim/system.hh"
552420SN/A#include "mem/translating_port.hh"
562SN/A#endif
572SN/A
582SN/Ausing namespace std;
592SN/A
602SN/A// constructor
611858SN/A#if FULL_SYSTEM
622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
633453Sgblack@eecs.umich.edu                           TheISA::ITB *_itb, TheISA::DTB *_dtb,
642683Sktlim@umich.edu                           bool use_kernel_stats)
652683Sktlim@umich.edu    : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
662683Sktlim@umich.edu      dtb(_dtb)
672521SN/A
682SN/A{
692683Sktlim@umich.edu    tc = new ProxyThreadContext<SimpleThread>(this);
702190SN/A
712680SN/A    quiesceEvent = new EndQuiesceEvent(tc);
722290SN/A
732526SN/A    regs.clear();
741917SN/A
751917SN/A    if (cpu->params->profile) {
761982SN/A        profile = new FunctionProfile(system->kernelSymtab);
771917SN/A        Callback *cb =
782683Sktlim@umich.edu            new MakeCallback<SimpleThread,
792683Sktlim@umich.edu            &SimpleThread::dumpFuncProfile>(this);
801917SN/A        registerExitCallback(cb);
811917SN/A    }
821917SN/A
831917SN/A    // let's fill with a dummy node for now so we don't get a segfault
841917SN/A    // on the first cycle when there's no node available.
851917SN/A    static ProfileNode dummyNode;
861917SN/A    profileNode = &dummyNode;
871917SN/A    profilePC = 3;
882521SN/A
892341SN/A    if (use_kernel_stats) {
902341SN/A        kernelStats = new Kernel::Statistics(system);
912341SN/A    } else {
922341SN/A        kernelStats = NULL;
932341SN/A    }
942521SN/A    Port *mem_port;
952640SN/A    physPort = new FunctionalPort(csprintf("%s-%d-funcport",
962683Sktlim@umich.edu                                           cpu->name(), tid));
972521SN/A    mem_port = system->physmem->getPort("functional");
982521SN/A    mem_port->setPeer(physPort);
992521SN/A    physPort->setPeer(mem_port);
1002521SN/A
1012640SN/A    virtPort = new VirtualPort(csprintf("%s-%d-vport",
1022683Sktlim@umich.edu                                        cpu->name(), tid));
1032521SN/A    mem_port = system->physmem->getPort("functional");
1042521SN/A    mem_port->setPeer(virtPort);
1052521SN/A    virtPort->setPeer(mem_port);
1062SN/A}
1072SN/A#else
1082683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num,
1092520SN/A                         Process *_process, int _asid, MemObject* memobj)
1102791Sktlim@umich.edu    : ThreadState(-1, _thread_num, _process, _asid, memobj),
1112683Sktlim@umich.edu      cpu(_cpu)
1122SN/A{
1132519SN/A    /* Use this port to for syscall emulation writes to memory. */
1142519SN/A    Port *mem_port;
1152640SN/A    port = new TranslatingPort(csprintf("%s-%d-funcport",
1162683Sktlim@umich.edu                                        cpu->name(), tid),
1172640SN/A                               process->pTable, false);
1182520SN/A    mem_port = memobj->getPort("functional");
1192519SN/A    mem_port->setPeer(port);
1202519SN/A    port->setPeer(mem_port);
1212519SN/A
1222526SN/A    regs.clear();
1232683Sktlim@umich.edu    tc = new ProxyThreadContext<SimpleThread>(this);
1242SN/A}
1252190SN/A
1262862Sktlim@umich.edu#endif
1272862Sktlim@umich.edu
1282864Sktlim@umich.eduSimpleThread::SimpleThread()
1292862Sktlim@umich.edu#if FULL_SYSTEM
1302862Sktlim@umich.edu    : ThreadState(-1, -1)
1312862Sktlim@umich.edu#else
1322862Sktlim@umich.edu    : ThreadState(-1, -1, NULL, -1, NULL)
1332862Sktlim@umich.edu#endif
1342190SN/A{
1352683Sktlim@umich.edu    tc = new ProxyThreadContext<SimpleThread>(this);
1362862Sktlim@umich.edu    regs.clear();
1372190SN/A}
1382190SN/A
1392683Sktlim@umich.eduSimpleThread::~SimpleThread()
1401070SN/A{
1412680SN/A    delete tc;
1421070SN/A}
1431070SN/A
1441917SN/Avoid
1452683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext)
146180SN/A{
147180SN/A    // some things should already be set up
1481858SN/A#if FULL_SYSTEM
1492235SN/A    assert(system == oldContext->getSystemPtr());
150180SN/A#else
1512235SN/A    assert(process == oldContext->getProcessPtr());
152180SN/A#endif
153180SN/A
1542862Sktlim@umich.edu    copyState(oldContext);
1552862Sktlim@umich.edu#if FULL_SYSTEM
1562313SN/A    EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
1572313SN/A    if (quiesce) {
1582680SN/A        // Point the quiesce event's TC at this TC so that it wakes up
1592313SN/A        // the proper CPU.
1602680SN/A        quiesce->tc = tc;
1612313SN/A    }
1622313SN/A    if (quiesceEvent) {
1632680SN/A        quiesceEvent->tc = tc;
1642313SN/A    }
1652361SN/A
1662361SN/A    Kernel::Statistics *stats = oldContext->getKernelStats();
1672361SN/A    if (stats) {
1682361SN/A        kernelStats = stats;
1692361SN/A    }
1702235SN/A#endif
171180SN/A
172180SN/A    storeCondFailures = 0;
173180SN/A
1742680SN/A    oldContext->setStatus(ThreadContext::Unallocated);
175180SN/A}
176180SN/A
1772SN/Avoid
1782864Sktlim@umich.eduSimpleThread::copyTC(ThreadContext *context)
1792864Sktlim@umich.edu{
1802864Sktlim@umich.edu    copyState(context);
1812864Sktlim@umich.edu
1822864Sktlim@umich.edu#if FULL_SYSTEM
1832864Sktlim@umich.edu    EndQuiesceEvent *quiesce = context->getQuiesceEvent();
1842864Sktlim@umich.edu    if (quiesce) {
1852864Sktlim@umich.edu        quiesceEvent = quiesce;
1862864Sktlim@umich.edu    }
1872864Sktlim@umich.edu    Kernel::Statistics *stats = context->getKernelStats();
1882864Sktlim@umich.edu    if (stats) {
1892864Sktlim@umich.edu        kernelStats = stats;
1902864Sktlim@umich.edu    }
1912864Sktlim@umich.edu#endif
1922864Sktlim@umich.edu}
1932864Sktlim@umich.edu
1942864Sktlim@umich.eduvoid
1952862Sktlim@umich.eduSimpleThread::copyState(ThreadContext *oldContext)
1962862Sktlim@umich.edu{
1972862Sktlim@umich.edu    // copy over functional state
1982862Sktlim@umich.edu    _status = oldContext->status();
1992862Sktlim@umich.edu    copyArchRegs(oldContext);
2002862Sktlim@umich.edu    cpuId = oldContext->readCpuId();
2012862Sktlim@umich.edu#if !FULL_SYSTEM
2022862Sktlim@umich.edu    funcExeInst = oldContext->readFuncExeInst();
2032862Sktlim@umich.edu#endif
2042915Sktlim@umich.edu    inst = oldContext->getInst();
2052862Sktlim@umich.edu}
2062862Sktlim@umich.edu
2072862Sktlim@umich.eduvoid
2082683Sktlim@umich.eduSimpleThread::serialize(ostream &os)
209217SN/A{
2102862Sktlim@umich.edu    ThreadState::serialize(os);
211223SN/A    regs.serialize(os);
212223SN/A    // thread_num and cpu_id are deterministic from the config
213217SN/A}
214217SN/A
215217SN/A
216217SN/Avoid
2172683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string &section)
218217SN/A{
2192862Sktlim@umich.edu    ThreadState::unserialize(cp, section);
220237SN/A    regs.unserialize(cp, section);
221223SN/A    // thread_num and cpu_id are deterministic from the config
222217SN/A}
223217SN/A
2242683Sktlim@umich.edu#if FULL_SYSTEM
2252683Sktlim@umich.eduvoid
2262683Sktlim@umich.eduSimpleThread::dumpFuncProfile()
2272683Sktlim@umich.edu{
2282683Sktlim@umich.edu    std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
2292683Sktlim@umich.edu    profile->dump(tc, *os);
2302683Sktlim@umich.edu}
2312683Sktlim@umich.edu#endif
232217SN/A
233217SN/Avoid
2342683Sktlim@umich.eduSimpleThread::activate(int delay)
2352SN/A{
2362680SN/A    if (status() == ThreadContext::Active)
2372SN/A        return;
2382SN/A
2392188SN/A    lastActivate = curTick;
2402188SN/A
2412680SN/A    if (status() == ThreadContext::Unallocated) {
2422683Sktlim@umich.edu        cpu->activateWhenReady(tid);
2432290SN/A        return;
2442290SN/A    }
2452290SN/A
2462680SN/A    _status = ThreadContext::Active;
2472290SN/A
2482290SN/A    // status() == Suspended
2492683Sktlim@umich.edu    cpu->activateContext(tid, delay);
250393SN/A}
251393SN/A
252393SN/Avoid
2532683Sktlim@umich.eduSimpleThread::suspend()
254393SN/A{
2552680SN/A    if (status() == ThreadContext::Suspended)
256393SN/A        return;
257393SN/A
2582188SN/A    lastActivate = curTick;
2592188SN/A    lastSuspend = curTick;
2602188SN/A/*
2611858SN/A#if FULL_SYSTEM
2622SN/A    // Don't change the status from active if there are pending interrupts
263393SN/A    if (cpu->check_interrupts()) {
2642680SN/A        assert(status() == ThreadContext::Active);
2652SN/A        return;
2662SN/A    }
2672SN/A#endif
2682188SN/A*/
2692680SN/A    _status = ThreadContext::Suspended;
2702683Sktlim@umich.edu    cpu->suspendContext(tid);
2712SN/A}
2722SN/A
2732SN/Avoid
2742683Sktlim@umich.eduSimpleThread::deallocate()
275393SN/A{
2762680SN/A    if (status() == ThreadContext::Unallocated)
277393SN/A        return;
278393SN/A
2792680SN/A    _status = ThreadContext::Unallocated;
2802683Sktlim@umich.edu    cpu->deallocateContext(tid);
281393SN/A}
282393SN/A
283393SN/Avoid
2842683Sktlim@umich.eduSimpleThread::halt()
285393SN/A{
2862680SN/A    if (status() == ThreadContext::Halted)
287393SN/A        return;
288393SN/A
2892680SN/A    _status = ThreadContext::Halted;
2902683Sktlim@umich.edu    cpu->haltContext(tid);
291393SN/A}
292393SN/A
293393SN/A
294393SN/Avoid
2952683Sktlim@umich.eduSimpleThread::regStats(const string &name)
2962SN/A{
2972330SN/A#if FULL_SYSTEM
2982341SN/A    if (kernelStats)
2992341SN/A        kernelStats->regStats(name + ".kern");
3002330SN/A#endif
3012SN/A}
302716SN/A
303716SN/Avoid
3042683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc)
3052190SN/A{
3062680SN/A    TheISA::copyRegs(src_tc, tc);
3072190SN/A}
3082190SN/A
3092521SN/A#if FULL_SYSTEM
3102521SN/AVirtualPort*
3112683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc)
3122521SN/A{
3132680SN/A    if (!src_tc)
3142521SN/A        return virtPort;
3152521SN/A
3162521SN/A    VirtualPort *vp;
3172521SN/A    Port *mem_port;
3182521SN/A
3192680SN/A    vp = new VirtualPort("tc-vport", src_tc);
3202521SN/A    mem_port = system->physmem->getPort("functional");
3212521SN/A    mem_port->setPeer(vp);
3222521SN/A    vp->setPeer(mem_port);
3232521SN/A    return vp;
3242521SN/A}
3252521SN/A
3262521SN/Avoid
3272683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp)
3282521SN/A{
3292684Ssaidi@eecs.umich.edu    if (vp != virtPort) {
3302684Ssaidi@eecs.umich.edu        delete vp->getPeer();
3312684Ssaidi@eecs.umich.edu        delete vp;
3322684Ssaidi@eecs.umich.edu    }
3332521SN/A}
3342521SN/A
3352521SN/A
3362521SN/A#endif
3372521SN/A
338