simple_thread.cc revision 2683
12SN/A/* 22188SN/A * Copyright (c) 2001-2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Steve Reinhardt 292665SN/A * Nathan Binkert 302665SN/A * Lisa Hsu 312665SN/A * Kevin Lim 322SN/A */ 332SN/A 342SN/A#include <string> 352SN/A 362465SN/A#include "arch/isa_traits.hh" 371717SN/A#include "cpu/base.hh" 382683Sktlim@umich.edu#include "cpu/simple_thread.hh" 392680SN/A#include "cpu/thread_context.hh" 402SN/A 411858SN/A#if FULL_SYSTEM 421917SN/A#include "base/callback.hh" 431070SN/A#include "base/cprintf.hh" 441917SN/A#include "base/output.hh" 452188SN/A#include "base/trace.hh" 461917SN/A#include "cpu/profile.hh" 472290SN/A#include "cpu/quiesce_event.hh" 481070SN/A#include "kern/kernel_stats.hh" 491070SN/A#include "sim/serialize.hh" 501917SN/A#include "sim/sim_exit.hh" 512170SN/A#include "arch/stacktrace.hh" 522SN/A#else 53360SN/A#include "sim/process.hh" 542519SN/A#include "sim/system.hh" 552420SN/A#include "mem/translating_port.hh" 562SN/A#endif 572SN/A 582SN/Ausing namespace std; 592SN/A 602SN/A// constructor 611858SN/A#if FULL_SYSTEM 622683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, 632683Sktlim@umich.edu AlphaITB *_itb, AlphaDTB *_dtb, 642683Sktlim@umich.edu bool use_kernel_stats) 652683Sktlim@umich.edu : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), 662683Sktlim@umich.edu dtb(_dtb) 672521SN/A 682SN/A{ 692683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 702190SN/A 712680SN/A quiesceEvent = new EndQuiesceEvent(tc); 722290SN/A 732526SN/A regs.clear(); 741917SN/A 751917SN/A if (cpu->params->profile) { 761982SN/A profile = new FunctionProfile(system->kernelSymtab); 771917SN/A Callback *cb = 782683Sktlim@umich.edu new MakeCallback<SimpleThread, 792683Sktlim@umich.edu &SimpleThread::dumpFuncProfile>(this); 801917SN/A registerExitCallback(cb); 811917SN/A } 821917SN/A 831917SN/A // let's fill with a dummy node for now so we don't get a segfault 841917SN/A // on the first cycle when there's no node available. 851917SN/A static ProfileNode dummyNode; 861917SN/A profileNode = &dummyNode; 871917SN/A profilePC = 3; 882521SN/A 892341SN/A if (use_kernel_stats) { 902341SN/A kernelStats = new Kernel::Statistics(system); 912341SN/A } else { 922341SN/A kernelStats = NULL; 932341SN/A } 942521SN/A Port *mem_port; 952640SN/A physPort = new FunctionalPort(csprintf("%s-%d-funcport", 962683Sktlim@umich.edu cpu->name(), tid)); 972521SN/A mem_port = system->physmem->getPort("functional"); 982521SN/A mem_port->setPeer(physPort); 992521SN/A physPort->setPeer(mem_port); 1002521SN/A 1012640SN/A virtPort = new VirtualPort(csprintf("%s-%d-vport", 1022683Sktlim@umich.edu cpu->name(), tid)); 1032521SN/A mem_port = system->physmem->getPort("functional"); 1042521SN/A mem_port->setPeer(virtPort); 1052521SN/A virtPort->setPeer(mem_port); 1062SN/A} 1072SN/A#else 1082683Sktlim@umich.eduSimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, 1092520SN/A Process *_process, int _asid, MemObject* memobj) 1102683Sktlim@umich.edu : ThreadState(-1, _thread_num, memobj, _process, _asid), 1112683Sktlim@umich.edu cpu(_cpu) 1122SN/A{ 1132519SN/A /* Use this port to for syscall emulation writes to memory. */ 1142519SN/A Port *mem_port; 1152640SN/A port = new TranslatingPort(csprintf("%s-%d-funcport", 1162683Sktlim@umich.edu cpu->name(), tid), 1172640SN/A process->pTable, false); 1182520SN/A mem_port = memobj->getPort("functional"); 1192519SN/A mem_port->setPeer(port); 1202519SN/A port->setPeer(mem_port); 1212519SN/A 1222526SN/A regs.clear(); 1232683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1242SN/A} 1252190SN/A 1262683Sktlim@umich.eduSimpleThread::SimpleThread(RegFile *regFile) 1272683Sktlim@umich.edu : ThreadState(-1, -1, NULL, NULL, -1), cpu(NULL) 1282190SN/A{ 1292190SN/A regs = *regFile; 1302683Sktlim@umich.edu tc = new ProxyThreadContext<SimpleThread>(this); 1312190SN/A} 1322190SN/A 1332SN/A#endif 1342SN/A 1352683Sktlim@umich.eduSimpleThread::~SimpleThread() 1361070SN/A{ 1372680SN/A delete tc; 1381070SN/A} 1391070SN/A 1401917SN/Avoid 1412683Sktlim@umich.eduSimpleThread::takeOverFrom(ThreadContext *oldContext) 142180SN/A{ 143180SN/A // some things should already be set up 1441858SN/A#if FULL_SYSTEM 1452235SN/A assert(system == oldContext->getSystemPtr()); 146180SN/A#else 1472235SN/A assert(process == oldContext->getProcessPtr()); 148180SN/A#endif 149180SN/A 150180SN/A // copy over functional state 1512235SN/A _status = oldContext->status(); 1522235SN/A copyArchRegs(oldContext); 1532683Sktlim@umich.edu cpuId = oldContext->readCpuId(); 1542235SN/A#if !FULL_SYSTEM 1552683Sktlim@umich.edu funcExeInst = oldContext->readFuncExeInst(); 1562324SN/A#else 1572313SN/A EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); 1582313SN/A if (quiesce) { 1592680SN/A // Point the quiesce event's TC at this TC so that it wakes up 1602313SN/A // the proper CPU. 1612680SN/A quiesce->tc = tc; 1622313SN/A } 1632313SN/A if (quiesceEvent) { 1642680SN/A quiesceEvent->tc = tc; 1652313SN/A } 1662235SN/A#endif 167180SN/A 168180SN/A storeCondFailures = 0; 169180SN/A 1702680SN/A oldContext->setStatus(ThreadContext::Unallocated); 171180SN/A} 172180SN/A 1732SN/Avoid 1742683Sktlim@umich.eduSimpleThread::serialize(ostream &os) 175217SN/A{ 176223SN/A SERIALIZE_ENUM(_status); 177223SN/A regs.serialize(os); 178223SN/A // thread_num and cpu_id are deterministic from the config 1792683Sktlim@umich.edu SERIALIZE_SCALAR(funcExeInst); 180716SN/A SERIALIZE_SCALAR(inst); 1812132SN/A 1822132SN/A#if FULL_SYSTEM 1832188SN/A Tick quiesceEndTick = 0; 1842290SN/A if (quiesceEvent->scheduled()) 1852290SN/A quiesceEndTick = quiesceEvent->when(); 1862188SN/A SERIALIZE_SCALAR(quiesceEndTick); 1872330SN/A if (kernelStats) 1882330SN/A kernelStats->serialize(os); 1892132SN/A#endif 190217SN/A} 191217SN/A 192217SN/A 193217SN/Avoid 1942683Sktlim@umich.eduSimpleThread::unserialize(Checkpoint *cp, const std::string §ion) 195217SN/A{ 196223SN/A UNSERIALIZE_ENUM(_status); 197237SN/A regs.unserialize(cp, section); 198223SN/A // thread_num and cpu_id are deterministic from the config 1992683Sktlim@umich.edu UNSERIALIZE_SCALAR(funcExeInst); 200716SN/A UNSERIALIZE_SCALAR(inst); 2012132SN/A 2022132SN/A#if FULL_SYSTEM 2032188SN/A Tick quiesceEndTick; 2042188SN/A UNSERIALIZE_SCALAR(quiesceEndTick); 2052188SN/A if (quiesceEndTick) 2062290SN/A quiesceEvent->schedule(quiesceEndTick); 2072330SN/A if (kernelStats) 2082330SN/A kernelStats->unserialize(cp, section); 2092132SN/A#endif 210217SN/A} 211217SN/A 2122683Sktlim@umich.edu#if FULL_SYSTEM 2132683Sktlim@umich.eduvoid 2142683Sktlim@umich.eduSimpleThread::dumpFuncProfile() 2152683Sktlim@umich.edu{ 2162683Sktlim@umich.edu std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); 2172683Sktlim@umich.edu profile->dump(tc, *os); 2182683Sktlim@umich.edu} 2192683Sktlim@umich.edu#endif 220217SN/A 221217SN/Avoid 2222683Sktlim@umich.eduSimpleThread::activate(int delay) 2232SN/A{ 2242680SN/A if (status() == ThreadContext::Active) 2252SN/A return; 2262SN/A 2272188SN/A lastActivate = curTick; 2282188SN/A 2292680SN/A if (status() == ThreadContext::Unallocated) { 2302683Sktlim@umich.edu cpu->activateWhenReady(tid); 2312290SN/A return; 2322290SN/A } 2332290SN/A 2342680SN/A _status = ThreadContext::Active; 2352290SN/A 2362290SN/A // status() == Suspended 2372683Sktlim@umich.edu cpu->activateContext(tid, delay); 238393SN/A} 239393SN/A 240393SN/Avoid 2412683Sktlim@umich.eduSimpleThread::suspend() 242393SN/A{ 2432680SN/A if (status() == ThreadContext::Suspended) 244393SN/A return; 245393SN/A 2462188SN/A lastActivate = curTick; 2472188SN/A lastSuspend = curTick; 2482188SN/A/* 2491858SN/A#if FULL_SYSTEM 2502SN/A // Don't change the status from active if there are pending interrupts 251393SN/A if (cpu->check_interrupts()) { 2522680SN/A assert(status() == ThreadContext::Active); 2532SN/A return; 2542SN/A } 2552SN/A#endif 2562188SN/A*/ 2572680SN/A _status = ThreadContext::Suspended; 2582683Sktlim@umich.edu cpu->suspendContext(tid); 2592SN/A} 2602SN/A 2612SN/Avoid 2622683Sktlim@umich.eduSimpleThread::deallocate() 263393SN/A{ 2642680SN/A if (status() == ThreadContext::Unallocated) 265393SN/A return; 266393SN/A 2672680SN/A _status = ThreadContext::Unallocated; 2682683Sktlim@umich.edu cpu->deallocateContext(tid); 269393SN/A} 270393SN/A 271393SN/Avoid 2722683Sktlim@umich.eduSimpleThread::halt() 273393SN/A{ 2742680SN/A if (status() == ThreadContext::Halted) 275393SN/A return; 276393SN/A 2772680SN/A _status = ThreadContext::Halted; 2782683Sktlim@umich.edu cpu->haltContext(tid); 279393SN/A} 280393SN/A 281393SN/A 282393SN/Avoid 2832683Sktlim@umich.eduSimpleThread::regStats(const string &name) 2842SN/A{ 2852330SN/A#if FULL_SYSTEM 2862341SN/A if (kernelStats) 2872341SN/A kernelStats->regStats(name + ".kern"); 2882330SN/A#endif 2892SN/A} 290716SN/A 291716SN/Avoid 2922683Sktlim@umich.eduSimpleThread::copyArchRegs(ThreadContext *src_tc) 2932190SN/A{ 2942680SN/A TheISA::copyRegs(src_tc, tc); 2952190SN/A} 2962190SN/A 2972521SN/A#if FULL_SYSTEM 2982521SN/AVirtualPort* 2992683Sktlim@umich.eduSimpleThread::getVirtPort(ThreadContext *src_tc) 3002521SN/A{ 3012680SN/A if (!src_tc) 3022521SN/A return virtPort; 3032521SN/A 3042521SN/A VirtualPort *vp; 3052521SN/A Port *mem_port; 3062521SN/A 3072680SN/A vp = new VirtualPort("tc-vport", src_tc); 3082521SN/A mem_port = system->physmem->getPort("functional"); 3092521SN/A mem_port->setPeer(vp); 3102521SN/A vp->setPeer(mem_port); 3112521SN/A return vp; 3122521SN/A} 3132521SN/A 3142521SN/Avoid 3152683Sktlim@umich.eduSimpleThread::delVirtPort(VirtualPort *vp) 3162521SN/A{ 3172680SN/A// assert(!vp->nullThreadContext()); 3182521SN/A delete vp->getPeer(); 3192521SN/A delete vp; 3202521SN/A} 3212521SN/A 3222521SN/A 3232521SN/A#endif 3242521SN/A 325