timing.cc revision 7520 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "config/the_isa.hh"
36#include "cpu/exetrace.hh"
37#include "cpu/simple/timing.hh"
38#include "mem/packet.hh"
39#include "mem/packet_access.hh"
40#include "params/TimingSimpleCPU.hh"
41#include "sim/system.hh"
42
43using namespace std;
44using namespace TheISA;
45
46Port *
47TimingSimpleCPU::getPort(const std::string &if_name, int idx)
48{
49    if (if_name == "dcache_port")
50        return &dcachePort;
51    else if (if_name == "icache_port")
52        return &icachePort;
53    else
54        panic("No Such Port\n");
55}
56
57void
58TimingSimpleCPU::init()
59{
60    BaseCPU::init();
61#if FULL_SYSTEM
62    for (int i = 0; i < threadContexts.size(); ++i) {
63        ThreadContext *tc = threadContexts[i];
64
65        // initialize CPU, including PC
66        TheISA::initCPU(tc, _cpuId);
67    }
68#endif
69}
70
71Tick
72TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
73{
74    panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
75    return curTick;
76}
77
78void
79TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
80{
81    //No internal storage to update, jusst return
82    return;
83}
84
85void
86TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
87{
88    if (status == RangeChange) {
89        if (!snoopRangeSent) {
90            snoopRangeSent = true;
91            sendStatusChange(Port::RangeChange);
92        }
93        return;
94    }
95
96    panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
97}
98
99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103    pkt = _pkt;
104    cpu->schedule(this, t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
108    : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
109    dcachePort(this, p->clock), fetchEvent(this)
110{
111    _status = Idle;
112
113    icachePort.snoopRangeSent = false;
114    dcachePort.snoopRangeSent = false;
115
116    ifetch_pkt = dcache_pkt = NULL;
117    drainEvent = NULL;
118    previousTick = 0;
119    changeState(SimObject::Running);
120}
121
122
123TimingSimpleCPU::~TimingSimpleCPU()
124{
125}
126
127void
128TimingSimpleCPU::serialize(ostream &os)
129{
130    SimObject::State so_state = SimObject::getState();
131    SERIALIZE_ENUM(so_state);
132    BaseSimpleCPU::serialize(os);
133}
134
135void
136TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
137{
138    SimObject::State so_state;
139    UNSERIALIZE_ENUM(so_state);
140    BaseSimpleCPU::unserialize(cp, section);
141}
142
143unsigned int
144TimingSimpleCPU::drain(Event *drain_event)
145{
146    // TimingSimpleCPU is ready to drain if it's not waiting for
147    // an access to complete.
148    if (_status == Idle || _status == Running || _status == SwitchedOut) {
149        changeState(SimObject::Drained);
150        return 0;
151    } else {
152        changeState(SimObject::Draining);
153        drainEvent = drain_event;
154        return 1;
155    }
156}
157
158void
159TimingSimpleCPU::resume()
160{
161    DPRINTF(SimpleCPU, "Resume\n");
162    if (_status != SwitchedOut && _status != Idle) {
163        assert(system->getMemoryMode() == Enums::timing);
164
165        if (fetchEvent.scheduled())
166           deschedule(fetchEvent);
167
168        schedule(fetchEvent, nextCycle());
169    }
170
171    changeState(SimObject::Running);
172}
173
174void
175TimingSimpleCPU::switchOut()
176{
177    assert(_status == Running || _status == Idle);
178    _status = SwitchedOut;
179    numCycles += tickToCycles(curTick - previousTick);
180
181    // If we've been scheduled to resume but are then told to switch out,
182    // we'll need to cancel it.
183    if (fetchEvent.scheduled())
184        deschedule(fetchEvent);
185}
186
187
188void
189TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
190{
191    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
192
193    // if any of this CPU's ThreadContexts are active, mark the CPU as
194    // running and schedule its tick event.
195    for (int i = 0; i < threadContexts.size(); ++i) {
196        ThreadContext *tc = threadContexts[i];
197        if (tc->status() == ThreadContext::Active && _status != Running) {
198            _status = Running;
199            break;
200        }
201    }
202
203    if (_status != Running) {
204        _status = Idle;
205    }
206    assert(threadContexts.size() == 1);
207    previousTick = curTick;
208}
209
210
211void
212TimingSimpleCPU::activateContext(int thread_num, int delay)
213{
214    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
215
216    assert(thread_num == 0);
217    assert(thread);
218
219    assert(_status == Idle);
220
221    notIdleFraction++;
222    _status = Running;
223
224    // kick things off by initiating the fetch of the next instruction
225    schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
226}
227
228
229void
230TimingSimpleCPU::suspendContext(int thread_num)
231{
232    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
233
234    assert(thread_num == 0);
235    assert(thread);
236
237    if (_status == Idle)
238        return;
239
240    assert(_status == Running);
241
242    // just change status to Idle... if status != Running,
243    // completeInst() will not initiate fetch of next instruction.
244
245    notIdleFraction--;
246    _status = Idle;
247}
248
249bool
250TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
251{
252    RequestPtr req = pkt->req;
253    if (req->isMmapedIpr()) {
254        Tick delay;
255        delay = TheISA::handleIprRead(thread->getTC(), pkt);
256        new IprEvent(pkt, this, nextCycle(curTick + delay));
257        _status = DcacheWaitResponse;
258        dcache_pkt = NULL;
259    } else if (!dcachePort.sendTiming(pkt)) {
260        _status = DcacheRetry;
261        dcache_pkt = pkt;
262    } else {
263        _status = DcacheWaitResponse;
264        // memory system takes ownership of packet
265        dcache_pkt = NULL;
266    }
267    return dcache_pkt == NULL;
268}
269
270void
271TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
272                          bool read)
273{
274    PacketPtr pkt;
275    buildPacket(pkt, req, read);
276    pkt->dataDynamic<uint8_t>(data);
277    if (req->getFlags().isSet(Request::NO_ACCESS)) {
278        assert(!dcache_pkt);
279        pkt->makeResponse();
280        completeDataAccess(pkt);
281    } else if (read) {
282        handleReadPacket(pkt);
283    } else {
284        bool do_access = true;  // flag to suppress cache access
285
286        if (req->isLLSC()) {
287            do_access = TheISA::handleLockedWrite(thread, req);
288        } else if (req->isCondSwap()) {
289            assert(res);
290            req->setExtraData(*res);
291        }
292
293        if (do_access) {
294            dcache_pkt = pkt;
295            handleWritePacket();
296        } else {
297            _status = DcacheWaitResponse;
298            completeDataAccess(pkt);
299        }
300    }
301}
302
303void
304TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
305                               RequestPtr req, uint8_t *data, bool read)
306{
307    PacketPtr pkt1, pkt2;
308    buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
309    if (req->getFlags().isSet(Request::NO_ACCESS)) {
310        assert(!dcache_pkt);
311        pkt1->makeResponse();
312        completeDataAccess(pkt1);
313    } else if (read) {
314        if (handleReadPacket(pkt1)) {
315            SplitFragmentSenderState * send_state =
316                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
317            send_state->clearFromParent();
318            if (handleReadPacket(pkt2)) {
319                send_state = dynamic_cast<SplitFragmentSenderState *>(
320                        pkt1->senderState);
321                send_state->clearFromParent();
322            }
323        }
324    } else {
325        dcache_pkt = pkt1;
326        if (handleWritePacket()) {
327            SplitFragmentSenderState * send_state =
328                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
329            send_state->clearFromParent();
330            dcache_pkt = pkt2;
331            if (handleWritePacket()) {
332                send_state = dynamic_cast<SplitFragmentSenderState *>(
333                        pkt1->senderState);
334                send_state->clearFromParent();
335            }
336        }
337    }
338}
339
340void
341TimingSimpleCPU::translationFault(Fault fault)
342{
343    // fault may be NoFault in cases where a fault is suppressed,
344    // for instance prefetches.
345    numCycles += tickToCycles(curTick - previousTick);
346    previousTick = curTick;
347
348    if (traceData) {
349        // Since there was a fault, we shouldn't trace this instruction.
350        delete traceData;
351        traceData = NULL;
352    }
353
354    postExecute();
355
356    if (getState() == SimObject::Draining) {
357        advancePC(fault);
358        completeDrain();
359    } else {
360        advanceInst(fault);
361    }
362}
363
364void
365TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
366{
367    MemCmd cmd;
368    if (read) {
369        cmd = MemCmd::ReadReq;
370        if (req->isLLSC())
371            cmd = MemCmd::LoadLockedReq;
372    } else {
373        cmd = MemCmd::WriteReq;
374        if (req->isLLSC()) {
375            cmd = MemCmd::StoreCondReq;
376        } else if (req->isSwap()) {
377            cmd = MemCmd::SwapReq;
378        }
379    }
380    pkt = new Packet(req, cmd, Packet::Broadcast);
381}
382
383void
384TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
385        RequestPtr req1, RequestPtr req2, RequestPtr req,
386        uint8_t *data, bool read)
387{
388    pkt1 = pkt2 = NULL;
389
390    assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
391
392    if (req->getFlags().isSet(Request::NO_ACCESS)) {
393        buildPacket(pkt1, req, read);
394        return;
395    }
396
397    buildPacket(pkt1, req1, read);
398    buildPacket(pkt2, req2, read);
399
400    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
401    PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
402                               Packet::Broadcast);
403
404    pkt->dataDynamic<uint8_t>(data);
405    pkt1->dataStatic<uint8_t>(data);
406    pkt2->dataStatic<uint8_t>(data + req1->getSize());
407
408    SplitMainSenderState * main_send_state = new SplitMainSenderState;
409    pkt->senderState = main_send_state;
410    main_send_state->fragments[0] = pkt1;
411    main_send_state->fragments[1] = pkt2;
412    main_send_state->outstanding = 2;
413    pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
414    pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
415}
416
417Fault
418TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
419                           unsigned size, unsigned flags)
420{
421    Fault fault;
422    const int asid = 0;
423    const ThreadID tid = 0;
424    const Addr pc = thread->readPC();
425    unsigned block_size = dcachePort.peerBlockSize();
426    BaseTLB::Mode mode = BaseTLB::Read;
427
428    if (traceData) {
429        traceData->setAddr(addr);
430    }
431
432    RequestPtr req  = new Request(asid, addr, size,
433                                  flags, pc, _cpuId, tid);
434
435    Addr split_addr = roundDown(addr + size - 1, block_size);
436    assert(split_addr <= addr || split_addr - addr < block_size);
437
438    _status = DTBWaitResponse;
439    if (split_addr > addr) {
440        RequestPtr req1, req2;
441        assert(!req->isLLSC() && !req->isSwap());
442        req->splitOnVaddr(split_addr, req1, req2);
443
444        WholeTranslationState *state =
445            new WholeTranslationState(req, req1, req2, new uint8_t[size],
446                                      NULL, mode);
447        DataTranslation<TimingSimpleCPU> *trans1 =
448            new DataTranslation<TimingSimpleCPU>(this, state, 0);
449        DataTranslation<TimingSimpleCPU> *trans2 =
450            new DataTranslation<TimingSimpleCPU>(this, state, 1);
451
452        thread->dtb->translateTiming(req1, tc, trans1, mode);
453        thread->dtb->translateTiming(req2, tc, trans2, mode);
454    } else {
455        WholeTranslationState *state =
456            new WholeTranslationState(req, new uint8_t[size], NULL, mode);
457        DataTranslation<TimingSimpleCPU> *translation
458            = new DataTranslation<TimingSimpleCPU>(this, state);
459        thread->dtb->translateTiming(req, tc, translation, mode);
460    }
461
462    return NoFault;
463}
464
465template <class T>
466Fault
467TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
468{
469    return readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
470}
471
472#ifndef DOXYGEN_SHOULD_SKIP_THIS
473
474template
475Fault
476TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
477
478template
479Fault
480TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
481
482template
483Fault
484TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
485
486template
487Fault
488TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
489
490template
491Fault
492TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
493
494template
495Fault
496TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
497
498#endif //DOXYGEN_SHOULD_SKIP_THIS
499
500template<>
501Fault
502TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
503{
504    return read(addr, *(uint64_t*)&data, flags);
505}
506
507template<>
508Fault
509TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
510{
511    return read(addr, *(uint32_t*)&data, flags);
512}
513
514template<>
515Fault
516TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
517{
518    return read(addr, (uint32_t&)data, flags);
519}
520
521bool
522TimingSimpleCPU::handleWritePacket()
523{
524    RequestPtr req = dcache_pkt->req;
525    if (req->isMmapedIpr()) {
526        Tick delay;
527        delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
528        new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
529        _status = DcacheWaitResponse;
530        dcache_pkt = NULL;
531    } else if (!dcachePort.sendTiming(dcache_pkt)) {
532        _status = DcacheRetry;
533    } else {
534        _status = DcacheWaitResponse;
535        // memory system takes ownership of packet
536        dcache_pkt = NULL;
537    }
538    return dcache_pkt == NULL;
539}
540
541Fault
542TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
543                                 Addr addr, unsigned flags, uint64_t *res)
544{
545    const int asid = 0;
546    const ThreadID tid = 0;
547    const Addr pc = thread->readPC();
548    unsigned block_size = dcachePort.peerBlockSize();
549    BaseTLB::Mode mode = BaseTLB::Write;
550
551    if (traceData) {
552        traceData->setAddr(addr);
553    }
554
555    RequestPtr req = new Request(asid, addr, size,
556                                 flags, pc, _cpuId, tid);
557
558    Addr split_addr = roundDown(addr + size - 1, block_size);
559    assert(split_addr <= addr || split_addr - addr < block_size);
560
561    _status = DTBWaitResponse;
562    if (split_addr > addr) {
563        RequestPtr req1, req2;
564        assert(!req->isLLSC() && !req->isSwap());
565        req->splitOnVaddr(split_addr, req1, req2);
566
567        WholeTranslationState *state =
568            new WholeTranslationState(req, req1, req2, data, res, mode);
569        DataTranslation<TimingSimpleCPU> *trans1 =
570            new DataTranslation<TimingSimpleCPU>(this, state, 0);
571        DataTranslation<TimingSimpleCPU> *trans2 =
572            new DataTranslation<TimingSimpleCPU>(this, state, 1);
573
574        thread->dtb->translateTiming(req1, tc, trans1, mode);
575        thread->dtb->translateTiming(req2, tc, trans2, mode);
576    } else {
577        WholeTranslationState *state =
578            new WholeTranslationState(req, data, res, mode);
579        DataTranslation<TimingSimpleCPU> *translation =
580            new DataTranslation<TimingSimpleCPU>(this, state);
581        thread->dtb->translateTiming(req, tc, translation, mode);
582    }
583
584    // Translation faults will be returned via finishTranslation()
585    return NoFault;
586}
587
588Fault
589TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
590                            Addr addr, unsigned flags, uint64_t *res)
591{
592    uint8_t *newData = new uint8_t[size];
593    memcpy(newData, data, size);
594    return writeTheseBytes(newData, size, addr, flags, res);
595}
596
597template <class T>
598Fault
599TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
600{
601    if (traceData) {
602        traceData->setData(data);
603    }
604    T *dataP = new T;
605    *dataP = TheISA::htog(data);
606
607    return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
608}
609
610
611#ifndef DOXYGEN_SHOULD_SKIP_THIS
612template
613Fault
614TimingSimpleCPU::write(Twin32_t data, Addr addr,
615                       unsigned flags, uint64_t *res);
616
617template
618Fault
619TimingSimpleCPU::write(Twin64_t data, Addr addr,
620                       unsigned flags, uint64_t *res);
621
622template
623Fault
624TimingSimpleCPU::write(uint64_t data, Addr addr,
625                       unsigned flags, uint64_t *res);
626
627template
628Fault
629TimingSimpleCPU::write(uint32_t data, Addr addr,
630                       unsigned flags, uint64_t *res);
631
632template
633Fault
634TimingSimpleCPU::write(uint16_t data, Addr addr,
635                       unsigned flags, uint64_t *res);
636
637template
638Fault
639TimingSimpleCPU::write(uint8_t data, Addr addr,
640                       unsigned flags, uint64_t *res);
641
642#endif //DOXYGEN_SHOULD_SKIP_THIS
643
644template<>
645Fault
646TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
647{
648    return write(*(uint64_t*)&data, addr, flags, res);
649}
650
651template<>
652Fault
653TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
654{
655    return write(*(uint32_t*)&data, addr, flags, res);
656}
657
658
659template<>
660Fault
661TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
662{
663    return write((uint32_t)data, addr, flags, res);
664}
665
666
667void
668TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
669{
670    _status = Running;
671
672    if (state->getFault() != NoFault) {
673        if (state->isPrefetch()) {
674            state->setNoFault();
675        }
676        delete state->data;
677        state->deleteReqs();
678        translationFault(state->getFault());
679    } else {
680        if (!state->isSplit) {
681            sendData(state->mainReq, state->data, state->res,
682                     state->mode == BaseTLB::Read);
683        } else {
684            sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
685                          state->data, state->mode == BaseTLB::Read);
686        }
687    }
688
689    delete state;
690}
691
692
693void
694TimingSimpleCPU::fetch()
695{
696    DPRINTF(SimpleCPU, "Fetch\n");
697
698    if (!curStaticInst || !curStaticInst->isDelayedCommit())
699        checkForInterrupts();
700
701    checkPcEventQueue();
702
703    bool fromRom = isRomMicroPC(thread->readMicroPC());
704
705    if (!fromRom && !curMacroStaticInst) {
706        Request *ifetch_req = new Request();
707        ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
708        setupFetchRequest(ifetch_req);
709        thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
710                BaseTLB::Execute);
711    } else {
712        _status = IcacheWaitResponse;
713        completeIfetch(NULL);
714
715        numCycles += tickToCycles(curTick - previousTick);
716        previousTick = curTick;
717    }
718}
719
720
721void
722TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
723{
724    if (fault == NoFault) {
725        ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
726        ifetch_pkt->dataStatic(&inst);
727
728        if (!icachePort.sendTiming(ifetch_pkt)) {
729            // Need to wait for retry
730            _status = IcacheRetry;
731        } else {
732            // Need to wait for cache to respond
733            _status = IcacheWaitResponse;
734            // ownership of packet transferred to memory system
735            ifetch_pkt = NULL;
736        }
737    } else {
738        delete req;
739        // fetch fault: advance directly to next instruction (fault handler)
740        advanceInst(fault);
741    }
742
743    numCycles += tickToCycles(curTick - previousTick);
744    previousTick = curTick;
745}
746
747
748void
749TimingSimpleCPU::advanceInst(Fault fault)
750{
751    if (fault != NoFault || !stayAtPC)
752        advancePC(fault);
753
754    if (_status == Running) {
755        // kick off fetch of next instruction... callback from icache
756        // response will cause that instruction to be executed,
757        // keeping the CPU running.
758        fetch();
759    }
760}
761
762
763void
764TimingSimpleCPU::completeIfetch(PacketPtr pkt)
765{
766    DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
767
768    // received a response from the icache: execute the received
769    // instruction
770
771    assert(!pkt || !pkt->isError());
772    assert(_status == IcacheWaitResponse);
773
774    _status = Running;
775
776    numCycles += tickToCycles(curTick - previousTick);
777    previousTick = curTick;
778
779    if (getState() == SimObject::Draining) {
780        if (pkt) {
781            delete pkt->req;
782            delete pkt;
783        }
784
785        completeDrain();
786        return;
787    }
788
789    preExecute();
790    if (curStaticInst &&
791            curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
792        // load or store: just send to dcache
793        Fault fault = curStaticInst->initiateAcc(this, traceData);
794        if (_status != Running) {
795            // instruction will complete in dcache response callback
796            assert(_status == DcacheWaitResponse ||
797                    _status == DcacheRetry || DTBWaitResponse);
798            assert(fault == NoFault);
799        } else {
800            if (fault != NoFault && traceData) {
801                // If there was a fault, we shouldn't trace this instruction.
802                delete traceData;
803                traceData = NULL;
804            }
805
806            postExecute();
807            // @todo remove me after debugging with legion done
808            if (curStaticInst && (!curStaticInst->isMicroop() ||
809                        curStaticInst->isFirstMicroop()))
810                instCnt++;
811            advanceInst(fault);
812        }
813    } else if (curStaticInst) {
814        // non-memory instruction: execute completely now
815        Fault fault = curStaticInst->execute(this, traceData);
816
817        // keep an instruction count
818        if (fault == NoFault)
819            countInst();
820        else if (traceData) {
821            // If there was a fault, we shouldn't trace this instruction.
822            delete traceData;
823            traceData = NULL;
824        }
825
826        postExecute();
827        // @todo remove me after debugging with legion done
828        if (curStaticInst && (!curStaticInst->isMicroop() ||
829                    curStaticInst->isFirstMicroop()))
830            instCnt++;
831        advanceInst(fault);
832    } else {
833        advanceInst(NoFault);
834    }
835
836    if (pkt) {
837        delete pkt->req;
838        delete pkt;
839    }
840}
841
842void
843TimingSimpleCPU::IcachePort::ITickEvent::process()
844{
845    cpu->completeIfetch(pkt);
846}
847
848bool
849TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
850{
851    if (pkt->isResponse() && !pkt->wasNacked()) {
852        // delay processing of returned data until next CPU clock edge
853        Tick next_tick = cpu->nextCycle(curTick);
854
855        if (next_tick == curTick)
856            cpu->completeIfetch(pkt);
857        else
858            tickEvent.schedule(pkt, next_tick);
859
860        return true;
861    }
862    else if (pkt->wasNacked()) {
863        assert(cpu->_status == IcacheWaitResponse);
864        pkt->reinitNacked();
865        if (!sendTiming(pkt)) {
866            cpu->_status = IcacheRetry;
867            cpu->ifetch_pkt = pkt;
868        }
869    }
870    //Snooping a Coherence Request, do nothing
871    return true;
872}
873
874void
875TimingSimpleCPU::IcachePort::recvRetry()
876{
877    // we shouldn't get a retry unless we have a packet that we're
878    // waiting to transmit
879    assert(cpu->ifetch_pkt != NULL);
880    assert(cpu->_status == IcacheRetry);
881    PacketPtr tmp = cpu->ifetch_pkt;
882    if (sendTiming(tmp)) {
883        cpu->_status = IcacheWaitResponse;
884        cpu->ifetch_pkt = NULL;
885    }
886}
887
888void
889TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
890{
891    // received a response from the dcache: complete the load or store
892    // instruction
893    assert(!pkt->isError());
894
895    numCycles += tickToCycles(curTick - previousTick);
896    previousTick = curTick;
897
898    if (pkt->senderState) {
899        SplitFragmentSenderState * send_state =
900            dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
901        assert(send_state);
902        delete pkt->req;
903        delete pkt;
904        PacketPtr big_pkt = send_state->bigPkt;
905        delete send_state;
906
907        SplitMainSenderState * main_send_state =
908            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
909        assert(main_send_state);
910        // Record the fact that this packet is no longer outstanding.
911        assert(main_send_state->outstanding != 0);
912        main_send_state->outstanding--;
913
914        if (main_send_state->outstanding) {
915            return;
916        } else {
917            delete main_send_state;
918            big_pkt->senderState = NULL;
919            pkt = big_pkt;
920        }
921    }
922
923    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
924    _status = Running;
925
926    Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
927
928    // keep an instruction count
929    if (fault == NoFault)
930        countInst();
931    else if (traceData) {
932        // If there was a fault, we shouldn't trace this instruction.
933        delete traceData;
934        traceData = NULL;
935    }
936
937    // the locked flag may be cleared on the response packet, so check
938    // pkt->req and not pkt to see if it was a load-locked
939    if (pkt->isRead() && pkt->req->isLLSC()) {
940        TheISA::handleLockedRead(thread, pkt->req);
941    }
942
943    delete pkt->req;
944    delete pkt;
945
946    postExecute();
947
948    if (getState() == SimObject::Draining) {
949        advancePC(fault);
950        completeDrain();
951
952        return;
953    }
954
955    advanceInst(fault);
956}
957
958
959void
960TimingSimpleCPU::completeDrain()
961{
962    DPRINTF(Config, "Done draining\n");
963    changeState(SimObject::Drained);
964    drainEvent->process();
965}
966
967void
968TimingSimpleCPU::DcachePort::setPeer(Port *port)
969{
970    Port::setPeer(port);
971
972#if FULL_SYSTEM
973    // Update the ThreadContext's memory ports (Functional/Virtual
974    // Ports)
975    cpu->tcBase()->connectMemPorts(cpu->tcBase());
976#endif
977}
978
979bool
980TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
981{
982    if (pkt->isResponse() && !pkt->wasNacked()) {
983        // delay processing of returned data until next CPU clock edge
984        Tick next_tick = cpu->nextCycle(curTick);
985
986        if (next_tick == curTick) {
987            cpu->completeDataAccess(pkt);
988        } else {
989            tickEvent.schedule(pkt, next_tick);
990        }
991
992        return true;
993    }
994    else if (pkt->wasNacked()) {
995        assert(cpu->_status == DcacheWaitResponse);
996        pkt->reinitNacked();
997        if (!sendTiming(pkt)) {
998            cpu->_status = DcacheRetry;
999            cpu->dcache_pkt = pkt;
1000        }
1001    }
1002    //Snooping a Coherence Request, do nothing
1003    return true;
1004}
1005
1006void
1007TimingSimpleCPU::DcachePort::DTickEvent::process()
1008{
1009    cpu->completeDataAccess(pkt);
1010}
1011
1012void
1013TimingSimpleCPU::DcachePort::recvRetry()
1014{
1015    // we shouldn't get a retry unless we have a packet that we're
1016    // waiting to transmit
1017    assert(cpu->dcache_pkt != NULL);
1018    assert(cpu->_status == DcacheRetry);
1019    PacketPtr tmp = cpu->dcache_pkt;
1020    if (tmp->senderState) {
1021        // This is a packet from a split access.
1022        SplitFragmentSenderState * send_state =
1023            dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
1024        assert(send_state);
1025        PacketPtr big_pkt = send_state->bigPkt;
1026
1027        SplitMainSenderState * main_send_state =
1028            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
1029        assert(main_send_state);
1030
1031        if (sendTiming(tmp)) {
1032            // If we were able to send without retrying, record that fact
1033            // and try sending the other fragment.
1034            send_state->clearFromParent();
1035            int other_index = main_send_state->getPendingFragment();
1036            if (other_index > 0) {
1037                tmp = main_send_state->fragments[other_index];
1038                cpu->dcache_pkt = tmp;
1039                if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
1040                        (big_pkt->isWrite() && cpu->handleWritePacket())) {
1041                    main_send_state->fragments[other_index] = NULL;
1042                }
1043            } else {
1044                cpu->_status = DcacheWaitResponse;
1045                // memory system takes ownership of packet
1046                cpu->dcache_pkt = NULL;
1047            }
1048        }
1049    } else if (sendTiming(tmp)) {
1050        cpu->_status = DcacheWaitResponse;
1051        // memory system takes ownership of packet
1052        cpu->dcache_pkt = NULL;
1053    }
1054}
1055
1056TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
1057    Tick t)
1058    : pkt(_pkt), cpu(_cpu)
1059{
1060    cpu->schedule(this, t);
1061}
1062
1063void
1064TimingSimpleCPU::IprEvent::process()
1065{
1066    cpu->completeDataAccess(pkt);
1067}
1068
1069const char *
1070TimingSimpleCPU::IprEvent::description() const
1071{
1072    return "Timing Simple CPU Delay IPR event";
1073}
1074
1075
1076void
1077TimingSimpleCPU::printAddr(Addr a)
1078{
1079    dcachePort.printAddr(a);
1080}
1081
1082
1083////////////////////////////////////////////////////////////////////////
1084//
1085//  TimingSimpleCPU Simulation Object
1086//
1087TimingSimpleCPU *
1088TimingSimpleCPUParams::create()
1089{
1090    numThreads = 1;
1091#if !FULL_SYSTEM
1092    if (workload.size() != 1)
1093        panic("only one workload allowed");
1094#endif
1095    return new TimingSimpleCPU(this);
1096}
1097