timing.cc revision 7045:e21fe6a62b1c 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "config/the_isa.hh"
36#include "cpu/exetrace.hh"
37#include "cpu/simple/timing.hh"
38#include "mem/packet.hh"
39#include "mem/packet_access.hh"
40#include "params/TimingSimpleCPU.hh"
41#include "sim/system.hh"
42
43using namespace std;
44using namespace TheISA;
45
46Port *
47TimingSimpleCPU::getPort(const std::string &if_name, int idx)
48{
49    if (if_name == "dcache_port")
50        return &dcachePort;
51    else if (if_name == "icache_port")
52        return &icachePort;
53    else
54        panic("No Such Port\n");
55}
56
57void
58TimingSimpleCPU::init()
59{
60    BaseCPU::init();
61#if FULL_SYSTEM
62    for (int i = 0; i < threadContexts.size(); ++i) {
63        ThreadContext *tc = threadContexts[i];
64
65        // initialize CPU, including PC
66        TheISA::initCPU(tc, _cpuId);
67    }
68#endif
69}
70
71Tick
72TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
73{
74    panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
75    return curTick;
76}
77
78void
79TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
80{
81    //No internal storage to update, jusst return
82    return;
83}
84
85void
86TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
87{
88    if (status == RangeChange) {
89        if (!snoopRangeSent) {
90            snoopRangeSent = true;
91            sendStatusChange(Port::RangeChange);
92        }
93        return;
94    }
95
96    panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
97}
98
99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103    pkt = _pkt;
104    cpu->schedule(this, t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
108    : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
109    dcachePort(this, p->clock), fetchEvent(this)
110{
111    _status = Idle;
112
113    icachePort.snoopRangeSent = false;
114    dcachePort.snoopRangeSent = false;
115
116    ifetch_pkt = dcache_pkt = NULL;
117    drainEvent = NULL;
118    previousTick = 0;
119    changeState(SimObject::Running);
120}
121
122
123TimingSimpleCPU::~TimingSimpleCPU()
124{
125}
126
127void
128TimingSimpleCPU::serialize(ostream &os)
129{
130    SimObject::State so_state = SimObject::getState();
131    SERIALIZE_ENUM(so_state);
132    BaseSimpleCPU::serialize(os);
133}
134
135void
136TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
137{
138    SimObject::State so_state;
139    UNSERIALIZE_ENUM(so_state);
140    BaseSimpleCPU::unserialize(cp, section);
141}
142
143unsigned int
144TimingSimpleCPU::drain(Event *drain_event)
145{
146    // TimingSimpleCPU is ready to drain if it's not waiting for
147    // an access to complete.
148    if (_status == Idle || _status == Running || _status == SwitchedOut) {
149        changeState(SimObject::Drained);
150        return 0;
151    } else {
152        changeState(SimObject::Draining);
153        drainEvent = drain_event;
154        return 1;
155    }
156}
157
158void
159TimingSimpleCPU::resume()
160{
161    DPRINTF(SimpleCPU, "Resume\n");
162    if (_status != SwitchedOut && _status != Idle) {
163        assert(system->getMemoryMode() == Enums::timing);
164
165        if (fetchEvent.scheduled())
166           deschedule(fetchEvent);
167
168        schedule(fetchEvent, nextCycle());
169    }
170
171    changeState(SimObject::Running);
172}
173
174void
175TimingSimpleCPU::switchOut()
176{
177    assert(_status == Running || _status == Idle);
178    _status = SwitchedOut;
179    numCycles += tickToCycles(curTick - previousTick);
180
181    // If we've been scheduled to resume but are then told to switch out,
182    // we'll need to cancel it.
183    if (fetchEvent.scheduled())
184        deschedule(fetchEvent);
185}
186
187
188void
189TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
190{
191    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
192
193    // if any of this CPU's ThreadContexts are active, mark the CPU as
194    // running and schedule its tick event.
195    for (int i = 0; i < threadContexts.size(); ++i) {
196        ThreadContext *tc = threadContexts[i];
197        if (tc->status() == ThreadContext::Active && _status != Running) {
198            _status = Running;
199            break;
200        }
201    }
202
203    if (_status != Running) {
204        _status = Idle;
205    }
206    assert(threadContexts.size() == 1);
207    previousTick = curTick;
208}
209
210
211void
212TimingSimpleCPU::activateContext(int thread_num, int delay)
213{
214    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
215
216    assert(thread_num == 0);
217    assert(thread);
218
219    assert(_status == Idle);
220
221    notIdleFraction++;
222    _status = Running;
223
224    // kick things off by initiating the fetch of the next instruction
225    schedule(fetchEvent, nextCycle(curTick + ticks(delay)));
226}
227
228
229void
230TimingSimpleCPU::suspendContext(int thread_num)
231{
232    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
233
234    assert(thread_num == 0);
235    assert(thread);
236
237    if (_status == Idle)
238        return;
239
240    assert(_status == Running);
241
242    // just change status to Idle... if status != Running,
243    // completeInst() will not initiate fetch of next instruction.
244
245    notIdleFraction--;
246    _status = Idle;
247}
248
249bool
250TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
251{
252    RequestPtr req = pkt->req;
253    if (req->isMmapedIpr()) {
254        Tick delay;
255        delay = TheISA::handleIprRead(thread->getTC(), pkt);
256        new IprEvent(pkt, this, nextCycle(curTick + delay));
257        _status = DcacheWaitResponse;
258        dcache_pkt = NULL;
259    } else if (!dcachePort.sendTiming(pkt)) {
260        _status = DcacheRetry;
261        dcache_pkt = pkt;
262    } else {
263        _status = DcacheWaitResponse;
264        // memory system takes ownership of packet
265        dcache_pkt = NULL;
266    }
267    return dcache_pkt == NULL;
268}
269
270void
271TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
272                          bool read)
273{
274    PacketPtr pkt;
275    buildPacket(pkt, req, read);
276    pkt->dataDynamic<uint8_t>(data);
277    if (req->getFlags().isSet(Request::NO_ACCESS)) {
278        assert(!dcache_pkt);
279        pkt->makeResponse();
280        completeDataAccess(pkt);
281    } else if (read) {
282        handleReadPacket(pkt);
283    } else {
284        bool do_access = true;  // flag to suppress cache access
285
286        if (req->isLLSC()) {
287            do_access = TheISA::handleLockedWrite(thread, req);
288        } else if (req->isCondSwap()) {
289            assert(res);
290            req->setExtraData(*res);
291        }
292
293        if (do_access) {
294            dcache_pkt = pkt;
295            handleWritePacket();
296        } else {
297            _status = DcacheWaitResponse;
298            completeDataAccess(pkt);
299        }
300    }
301}
302
303void
304TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
305                               RequestPtr req, uint8_t *data, bool read)
306{
307    PacketPtr pkt1, pkt2;
308    buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
309    if (req->getFlags().isSet(Request::NO_ACCESS)) {
310        assert(!dcache_pkt);
311        pkt1->makeResponse();
312        completeDataAccess(pkt1);
313    } else if (read) {
314        if (handleReadPacket(pkt1)) {
315            SplitFragmentSenderState * send_state =
316                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
317            send_state->clearFromParent();
318            if (handleReadPacket(pkt2)) {
319                send_state = dynamic_cast<SplitFragmentSenderState *>(
320                        pkt1->senderState);
321                send_state->clearFromParent();
322            }
323        }
324    } else {
325        dcache_pkt = pkt1;
326        if (handleWritePacket()) {
327            SplitFragmentSenderState * send_state =
328                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
329            send_state->clearFromParent();
330            dcache_pkt = pkt2;
331            if (handleWritePacket()) {
332                send_state = dynamic_cast<SplitFragmentSenderState *>(
333                        pkt1->senderState);
334                send_state->clearFromParent();
335            }
336        }
337    }
338}
339
340void
341TimingSimpleCPU::translationFault(Fault fault)
342{
343    // fault may be NoFault in cases where a fault is suppressed,
344    // for instance prefetches.
345    numCycles += tickToCycles(curTick - previousTick);
346    previousTick = curTick;
347
348    if (traceData) {
349        // Since there was a fault, we shouldn't trace this instruction.
350        delete traceData;
351        traceData = NULL;
352    }
353
354    postExecute();
355
356    if (getState() == SimObject::Draining) {
357        advancePC(fault);
358        completeDrain();
359    } else {
360        advanceInst(fault);
361    }
362}
363
364void
365TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
366{
367    MemCmd cmd;
368    if (read) {
369        cmd = MemCmd::ReadReq;
370        if (req->isLLSC())
371            cmd = MemCmd::LoadLockedReq;
372    } else {
373        cmd = MemCmd::WriteReq;
374        if (req->isLLSC()) {
375            cmd = MemCmd::StoreCondReq;
376        } else if (req->isSwap()) {
377            cmd = MemCmd::SwapReq;
378        }
379    }
380    pkt = new Packet(req, cmd, Packet::Broadcast);
381}
382
383void
384TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
385        RequestPtr req1, RequestPtr req2, RequestPtr req,
386        uint8_t *data, bool read)
387{
388    pkt1 = pkt2 = NULL;
389
390    assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
391
392    if (req->getFlags().isSet(Request::NO_ACCESS)) {
393        buildPacket(pkt1, req, read);
394        return;
395    }
396
397    buildPacket(pkt1, req1, read);
398    buildPacket(pkt2, req2, read);
399
400    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
401    PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
402                               Packet::Broadcast);
403
404    pkt->dataDynamic<uint8_t>(data);
405    pkt1->dataStatic<uint8_t>(data);
406    pkt2->dataStatic<uint8_t>(data + req1->getSize());
407
408    SplitMainSenderState * main_send_state = new SplitMainSenderState;
409    pkt->senderState = main_send_state;
410    main_send_state->fragments[0] = pkt1;
411    main_send_state->fragments[1] = pkt2;
412    main_send_state->outstanding = 2;
413    pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
414    pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
415}
416
417template <class T>
418Fault
419TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
420{
421    Fault fault;
422    const int asid = 0;
423    const ThreadID tid = 0;
424    const Addr pc = thread->readPC();
425    unsigned block_size = dcachePort.peerBlockSize();
426    int data_size = sizeof(T);
427    BaseTLB::Mode mode = BaseTLB::Read;
428
429    if (traceData) {
430        traceData->setAddr(addr);
431    }
432
433    RequestPtr req  = new Request(asid, addr, data_size,
434                                  flags, pc, _cpuId, tid);
435
436    Addr split_addr = roundDown(addr + data_size - 1, block_size);
437    assert(split_addr <= addr || split_addr - addr < block_size);
438
439    // This will need a new way to tell if it's hooked up to a cache or not.
440    if (req->isUncacheable())
441        recordEvent("Uncached Write");
442
443    _status = DTBWaitResponse;
444    if (split_addr > addr) {
445        RequestPtr req1, req2;
446        assert(!req->isLLSC() && !req->isSwap());
447        req->splitOnVaddr(split_addr, req1, req2);
448
449        WholeTranslationState *state =
450            new WholeTranslationState(req, req1, req2, (uint8_t *)(new T),
451                                      NULL, mode);
452        DataTranslation<TimingSimpleCPU> *trans1 =
453            new DataTranslation<TimingSimpleCPU>(this, state, 0);
454        DataTranslation<TimingSimpleCPU> *trans2 =
455            new DataTranslation<TimingSimpleCPU>(this, state, 1);
456
457        thread->dtb->translateTiming(req1, tc, trans1, mode);
458        thread->dtb->translateTiming(req2, tc, trans2, mode);
459    } else {
460        WholeTranslationState *state =
461            new WholeTranslationState(req, (uint8_t *)(new T), NULL, mode);
462        DataTranslation<TimingSimpleCPU> *translation
463            = new DataTranslation<TimingSimpleCPU>(this, state);
464        thread->dtb->translateTiming(req, tc, translation, mode);
465    }
466
467    return NoFault;
468}
469
470#ifndef DOXYGEN_SHOULD_SKIP_THIS
471
472template
473Fault
474TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
475
476template
477Fault
478TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
479
480template
481Fault
482TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
483
484template
485Fault
486TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
487
488template
489Fault
490TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
491
492template
493Fault
494TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
495
496#endif //DOXYGEN_SHOULD_SKIP_THIS
497
498template<>
499Fault
500TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
501{
502    return read(addr, *(uint64_t*)&data, flags);
503}
504
505template<>
506Fault
507TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
508{
509    return read(addr, *(uint32_t*)&data, flags);
510}
511
512template<>
513Fault
514TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
515{
516    return read(addr, (uint32_t&)data, flags);
517}
518
519bool
520TimingSimpleCPU::handleWritePacket()
521{
522    RequestPtr req = dcache_pkt->req;
523    if (req->isMmapedIpr()) {
524        Tick delay;
525        delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
526        new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
527        _status = DcacheWaitResponse;
528        dcache_pkt = NULL;
529    } else if (!dcachePort.sendTiming(dcache_pkt)) {
530        _status = DcacheRetry;
531    } else {
532        _status = DcacheWaitResponse;
533        // memory system takes ownership of packet
534        dcache_pkt = NULL;
535    }
536    return dcache_pkt == NULL;
537}
538
539template <class T>
540Fault
541TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
542{
543    const int asid = 0;
544    const ThreadID tid = 0;
545    const Addr pc = thread->readPC();
546    unsigned block_size = dcachePort.peerBlockSize();
547    int data_size = sizeof(T);
548    BaseTLB::Mode mode = BaseTLB::Write;
549
550    if (traceData) {
551        traceData->setAddr(addr);
552        traceData->setData(data);
553    }
554
555    RequestPtr req = new Request(asid, addr, data_size,
556                                 flags, pc, _cpuId, tid);
557
558    Addr split_addr = roundDown(addr + data_size - 1, block_size);
559    assert(split_addr <= addr || split_addr - addr < block_size);
560
561    // This will need a new way to tell if it's hooked up to a cache or not.
562    if (req->isUncacheable())
563        recordEvent("Uncached Write");
564
565    T *dataP = new T;
566    *dataP = TheISA::htog(data);
567    _status = DTBWaitResponse;
568    if (split_addr > addr) {
569        RequestPtr req1, req2;
570        assert(!req->isLLSC() && !req->isSwap());
571        req->splitOnVaddr(split_addr, req1, req2);
572
573        WholeTranslationState *state =
574            new WholeTranslationState(req, req1, req2, (uint8_t *)dataP,
575                                      res, mode);
576        DataTranslation<TimingSimpleCPU> *trans1 =
577            new DataTranslation<TimingSimpleCPU>(this, state, 0);
578        DataTranslation<TimingSimpleCPU> *trans2 =
579            new DataTranslation<TimingSimpleCPU>(this, state, 1);
580
581        thread->dtb->translateTiming(req1, tc, trans1, mode);
582        thread->dtb->translateTiming(req2, tc, trans2, mode);
583    } else {
584        WholeTranslationState *state =
585            new WholeTranslationState(req, (uint8_t *)dataP, res, mode);
586        DataTranslation<TimingSimpleCPU> *translation =
587            new DataTranslation<TimingSimpleCPU>(this, state);
588        thread->dtb->translateTiming(req, tc, translation, mode);
589    }
590
591    // Translation faults will be returned via finishTranslation()
592    return NoFault;
593}
594
595
596#ifndef DOXYGEN_SHOULD_SKIP_THIS
597template
598Fault
599TimingSimpleCPU::write(Twin32_t data, Addr addr,
600                       unsigned flags, uint64_t *res);
601
602template
603Fault
604TimingSimpleCPU::write(Twin64_t data, Addr addr,
605                       unsigned flags, uint64_t *res);
606
607template
608Fault
609TimingSimpleCPU::write(uint64_t data, Addr addr,
610                       unsigned flags, uint64_t *res);
611
612template
613Fault
614TimingSimpleCPU::write(uint32_t data, Addr addr,
615                       unsigned flags, uint64_t *res);
616
617template
618Fault
619TimingSimpleCPU::write(uint16_t data, Addr addr,
620                       unsigned flags, uint64_t *res);
621
622template
623Fault
624TimingSimpleCPU::write(uint8_t data, Addr addr,
625                       unsigned flags, uint64_t *res);
626
627#endif //DOXYGEN_SHOULD_SKIP_THIS
628
629template<>
630Fault
631TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
632{
633    return write(*(uint64_t*)&data, addr, flags, res);
634}
635
636template<>
637Fault
638TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
639{
640    return write(*(uint32_t*)&data, addr, flags, res);
641}
642
643
644template<>
645Fault
646TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
647{
648    return write((uint32_t)data, addr, flags, res);
649}
650
651
652void
653TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
654{
655    _status = Running;
656
657    if (state->getFault() != NoFault) {
658        if (state->isPrefetch()) {
659            state->setNoFault();
660        }
661        delete state->data;
662        state->deleteReqs();
663        translationFault(state->getFault());
664    } else {
665        if (!state->isSplit) {
666            sendData(state->mainReq, state->data, state->res,
667                     state->mode == BaseTLB::Read);
668        } else {
669            sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
670                          state->data, state->mode == BaseTLB::Read);
671        }
672    }
673
674    delete state;
675}
676
677
678void
679TimingSimpleCPU::fetch()
680{
681    DPRINTF(SimpleCPU, "Fetch\n");
682
683    if (!curStaticInst || !curStaticInst->isDelayedCommit())
684        checkForInterrupts();
685
686    checkPcEventQueue();
687
688    bool fromRom = isRomMicroPC(thread->readMicroPC());
689
690    if (!fromRom && !curMacroStaticInst) {
691        Request *ifetch_req = new Request();
692        ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
693        setupFetchRequest(ifetch_req);
694        thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
695                BaseTLB::Execute);
696    } else {
697        _status = IcacheWaitResponse;
698        completeIfetch(NULL);
699
700        numCycles += tickToCycles(curTick - previousTick);
701        previousTick = curTick;
702    }
703}
704
705
706void
707TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
708{
709    if (fault == NoFault) {
710        ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
711        ifetch_pkt->dataStatic(&inst);
712
713        if (!icachePort.sendTiming(ifetch_pkt)) {
714            // Need to wait for retry
715            _status = IcacheRetry;
716        } else {
717            // Need to wait for cache to respond
718            _status = IcacheWaitResponse;
719            // ownership of packet transferred to memory system
720            ifetch_pkt = NULL;
721        }
722    } else {
723        delete req;
724        // fetch fault: advance directly to next instruction (fault handler)
725        advanceInst(fault);
726    }
727
728    numCycles += tickToCycles(curTick - previousTick);
729    previousTick = curTick;
730}
731
732
733void
734TimingSimpleCPU::advanceInst(Fault fault)
735{
736    if (fault != NoFault || !stayAtPC)
737        advancePC(fault);
738
739    if (_status == Running) {
740        // kick off fetch of next instruction... callback from icache
741        // response will cause that instruction to be executed,
742        // keeping the CPU running.
743        fetch();
744    }
745}
746
747
748void
749TimingSimpleCPU::completeIfetch(PacketPtr pkt)
750{
751    DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
752
753    // received a response from the icache: execute the received
754    // instruction
755
756    assert(!pkt || !pkt->isError());
757    assert(_status == IcacheWaitResponse);
758
759    _status = Running;
760
761    numCycles += tickToCycles(curTick - previousTick);
762    previousTick = curTick;
763
764    if (getState() == SimObject::Draining) {
765        if (pkt) {
766            delete pkt->req;
767            delete pkt;
768        }
769
770        completeDrain();
771        return;
772    }
773
774    preExecute();
775    if (curStaticInst &&
776            curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
777        // load or store: just send to dcache
778        Fault fault = curStaticInst->initiateAcc(this, traceData);
779        if (_status != Running) {
780            // instruction will complete in dcache response callback
781            assert(_status == DcacheWaitResponse ||
782                    _status == DcacheRetry || DTBWaitResponse);
783            assert(fault == NoFault);
784        } else {
785            if (fault != NoFault && traceData) {
786                // If there was a fault, we shouldn't trace this instruction.
787                delete traceData;
788                traceData = NULL;
789            }
790
791            postExecute();
792            // @todo remove me after debugging with legion done
793            if (curStaticInst && (!curStaticInst->isMicroop() ||
794                        curStaticInst->isFirstMicroop()))
795                instCnt++;
796            advanceInst(fault);
797        }
798    } else if (curStaticInst) {
799        // non-memory instruction: execute completely now
800        Fault fault = curStaticInst->execute(this, traceData);
801
802        // keep an instruction count
803        if (fault == NoFault)
804            countInst();
805        else if (traceData) {
806            // If there was a fault, we shouldn't trace this instruction.
807            delete traceData;
808            traceData = NULL;
809        }
810
811        postExecute();
812        // @todo remove me after debugging with legion done
813        if (curStaticInst && (!curStaticInst->isMicroop() ||
814                    curStaticInst->isFirstMicroop()))
815            instCnt++;
816        advanceInst(fault);
817    } else {
818        advanceInst(NoFault);
819    }
820
821    if (pkt) {
822        delete pkt->req;
823        delete pkt;
824    }
825}
826
827void
828TimingSimpleCPU::IcachePort::ITickEvent::process()
829{
830    cpu->completeIfetch(pkt);
831}
832
833bool
834TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
835{
836    if (pkt->isResponse() && !pkt->wasNacked()) {
837        // delay processing of returned data until next CPU clock edge
838        Tick next_tick = cpu->nextCycle(curTick);
839
840        if (next_tick == curTick)
841            cpu->completeIfetch(pkt);
842        else
843            tickEvent.schedule(pkt, next_tick);
844
845        return true;
846    }
847    else if (pkt->wasNacked()) {
848        assert(cpu->_status == IcacheWaitResponse);
849        pkt->reinitNacked();
850        if (!sendTiming(pkt)) {
851            cpu->_status = IcacheRetry;
852            cpu->ifetch_pkt = pkt;
853        }
854    }
855    //Snooping a Coherence Request, do nothing
856    return true;
857}
858
859void
860TimingSimpleCPU::IcachePort::recvRetry()
861{
862    // we shouldn't get a retry unless we have a packet that we're
863    // waiting to transmit
864    assert(cpu->ifetch_pkt != NULL);
865    assert(cpu->_status == IcacheRetry);
866    PacketPtr tmp = cpu->ifetch_pkt;
867    if (sendTiming(tmp)) {
868        cpu->_status = IcacheWaitResponse;
869        cpu->ifetch_pkt = NULL;
870    }
871}
872
873void
874TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
875{
876    // received a response from the dcache: complete the load or store
877    // instruction
878    assert(!pkt->isError());
879
880    numCycles += tickToCycles(curTick - previousTick);
881    previousTick = curTick;
882
883    if (pkt->senderState) {
884        SplitFragmentSenderState * send_state =
885            dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
886        assert(send_state);
887        delete pkt->req;
888        delete pkt;
889        PacketPtr big_pkt = send_state->bigPkt;
890        delete send_state;
891
892        SplitMainSenderState * main_send_state =
893            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
894        assert(main_send_state);
895        // Record the fact that this packet is no longer outstanding.
896        assert(main_send_state->outstanding != 0);
897        main_send_state->outstanding--;
898
899        if (main_send_state->outstanding) {
900            return;
901        } else {
902            delete main_send_state;
903            big_pkt->senderState = NULL;
904            pkt = big_pkt;
905        }
906    }
907
908    assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
909    _status = Running;
910
911    Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
912
913    // keep an instruction count
914    if (fault == NoFault)
915        countInst();
916    else if (traceData) {
917        // If there was a fault, we shouldn't trace this instruction.
918        delete traceData;
919        traceData = NULL;
920    }
921
922    // the locked flag may be cleared on the response packet, so check
923    // pkt->req and not pkt to see if it was a load-locked
924    if (pkt->isRead() && pkt->req->isLLSC()) {
925        TheISA::handleLockedRead(thread, pkt->req);
926    }
927
928    delete pkt->req;
929    delete pkt;
930
931    postExecute();
932
933    if (getState() == SimObject::Draining) {
934        advancePC(fault);
935        completeDrain();
936
937        return;
938    }
939
940    advanceInst(fault);
941}
942
943
944void
945TimingSimpleCPU::completeDrain()
946{
947    DPRINTF(Config, "Done draining\n");
948    changeState(SimObject::Drained);
949    drainEvent->process();
950}
951
952void
953TimingSimpleCPU::DcachePort::setPeer(Port *port)
954{
955    Port::setPeer(port);
956
957#if FULL_SYSTEM
958    // Update the ThreadContext's memory ports (Functional/Virtual
959    // Ports)
960    cpu->tcBase()->connectMemPorts(cpu->tcBase());
961#endif
962}
963
964bool
965TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
966{
967    if (pkt->isResponse() && !pkt->wasNacked()) {
968        // delay processing of returned data until next CPU clock edge
969        Tick next_tick = cpu->nextCycle(curTick);
970
971        if (next_tick == curTick) {
972            cpu->completeDataAccess(pkt);
973        } else {
974            tickEvent.schedule(pkt, next_tick);
975        }
976
977        return true;
978    }
979    else if (pkt->wasNacked()) {
980        assert(cpu->_status == DcacheWaitResponse);
981        pkt->reinitNacked();
982        if (!sendTiming(pkt)) {
983            cpu->_status = DcacheRetry;
984            cpu->dcache_pkt = pkt;
985        }
986    }
987    //Snooping a Coherence Request, do nothing
988    return true;
989}
990
991void
992TimingSimpleCPU::DcachePort::DTickEvent::process()
993{
994    cpu->completeDataAccess(pkt);
995}
996
997void
998TimingSimpleCPU::DcachePort::recvRetry()
999{
1000    // we shouldn't get a retry unless we have a packet that we're
1001    // waiting to transmit
1002    assert(cpu->dcache_pkt != NULL);
1003    assert(cpu->_status == DcacheRetry);
1004    PacketPtr tmp = cpu->dcache_pkt;
1005    if (tmp->senderState) {
1006        // This is a packet from a split access.
1007        SplitFragmentSenderState * send_state =
1008            dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
1009        assert(send_state);
1010        PacketPtr big_pkt = send_state->bigPkt;
1011
1012        SplitMainSenderState * main_send_state =
1013            dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
1014        assert(main_send_state);
1015
1016        if (sendTiming(tmp)) {
1017            // If we were able to send without retrying, record that fact
1018            // and try sending the other fragment.
1019            send_state->clearFromParent();
1020            int other_index = main_send_state->getPendingFragment();
1021            if (other_index > 0) {
1022                tmp = main_send_state->fragments[other_index];
1023                cpu->dcache_pkt = tmp;
1024                if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
1025                        (big_pkt->isWrite() && cpu->handleWritePacket())) {
1026                    main_send_state->fragments[other_index] = NULL;
1027                }
1028            } else {
1029                cpu->_status = DcacheWaitResponse;
1030                // memory system takes ownership of packet
1031                cpu->dcache_pkt = NULL;
1032            }
1033        }
1034    } else if (sendTiming(tmp)) {
1035        cpu->_status = DcacheWaitResponse;
1036        // memory system takes ownership of packet
1037        cpu->dcache_pkt = NULL;
1038    }
1039}
1040
1041TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
1042    Tick t)
1043    : pkt(_pkt), cpu(_cpu)
1044{
1045    cpu->schedule(this, t);
1046}
1047
1048void
1049TimingSimpleCPU::IprEvent::process()
1050{
1051    cpu->completeDataAccess(pkt);
1052}
1053
1054const char *
1055TimingSimpleCPU::IprEvent::description() const
1056{
1057    return "Timing Simple CPU Delay IPR event";
1058}
1059
1060
1061void
1062TimingSimpleCPU::printAddr(Addr a)
1063{
1064    dcachePort.printAddr(a);
1065}
1066
1067
1068////////////////////////////////////////////////////////////////////////
1069//
1070//  TimingSimpleCPU Simulation Object
1071//
1072TimingSimpleCPU *
1073TimingSimpleCPUParams::create()
1074{
1075    numThreads = 1;
1076#if !FULL_SYSTEM
1077    if (workload.size() != 1)
1078        panic("only one workload allowed");
1079#endif
1080    return new TimingSimpleCPU(this);
1081}
1082