timing.cc revision 5348
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/timing.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/TimingSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45Port *
46TimingSimpleCPU::getPort(const std::string &if_name, int idx)
47{
48    if (if_name == "dcache_port")
49        return &dcachePort;
50    else if (if_name == "icache_port")
51        return &icachePort;
52    else
53        panic("No Such Port\n");
54}
55
56void
57TimingSimpleCPU::init()
58{
59    BaseCPU::init();
60    cpuId = tc->readCpuId();
61#if FULL_SYSTEM
62    for (int i = 0; i < threadContexts.size(); ++i) {
63        ThreadContext *tc = threadContexts[i];
64
65        // initialize CPU, including PC
66        TheISA::initCPU(tc, cpuId);
67    }
68#endif
69}
70
71Tick
72TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
73{
74    panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
75    return curTick;
76}
77
78void
79TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
80{
81    //No internal storage to update, jusst return
82    return;
83}
84
85void
86TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
87{
88    if (status == RangeChange) {
89        if (!snoopRangeSent) {
90            snoopRangeSent = true;
91            sendStatusChange(Port::RangeChange);
92        }
93        return;
94    }
95
96    panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
97}
98
99
100void
101TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
102{
103    pkt = _pkt;
104    Event::schedule(t);
105}
106
107TimingSimpleCPU::TimingSimpleCPU(Params *p)
108    : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
109{
110    _status = Idle;
111
112    icachePort.snoopRangeSent = false;
113    dcachePort.snoopRangeSent = false;
114
115    ifetch_pkt = dcache_pkt = NULL;
116    drainEvent = NULL;
117    fetchEvent = NULL;
118    previousTick = 0;
119    changeState(SimObject::Running);
120}
121
122
123TimingSimpleCPU::~TimingSimpleCPU()
124{
125}
126
127void
128TimingSimpleCPU::serialize(ostream &os)
129{
130    SimObject::State so_state = SimObject::getState();
131    SERIALIZE_ENUM(so_state);
132    BaseSimpleCPU::serialize(os);
133}
134
135void
136TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
137{
138    SimObject::State so_state;
139    UNSERIALIZE_ENUM(so_state);
140    BaseSimpleCPU::unserialize(cp, section);
141}
142
143unsigned int
144TimingSimpleCPU::drain(Event *drain_event)
145{
146    // TimingSimpleCPU is ready to drain if it's not waiting for
147    // an access to complete.
148    if (status() == Idle || status() == Running || status() == SwitchedOut) {
149        changeState(SimObject::Drained);
150        return 0;
151    } else {
152        changeState(SimObject::Draining);
153        drainEvent = drain_event;
154        return 1;
155    }
156}
157
158void
159TimingSimpleCPU::resume()
160{
161    DPRINTF(SimpleCPU, "Resume\n");
162    if (_status != SwitchedOut && _status != Idle) {
163        assert(system->getMemoryMode() == Enums::timing);
164
165        // Delete the old event if it existed.
166        if (fetchEvent) {
167            if (fetchEvent->scheduled())
168                fetchEvent->deschedule();
169
170            delete fetchEvent;
171        }
172
173        fetchEvent = new FetchEvent(this, nextCycle());
174    }
175
176    changeState(SimObject::Running);
177}
178
179void
180TimingSimpleCPU::switchOut()
181{
182    assert(status() == Running || status() == Idle);
183    _status = SwitchedOut;
184    numCycles += tickToCycles(curTick - previousTick);
185
186    // If we've been scheduled to resume but are then told to switch out,
187    // we'll need to cancel it.
188    if (fetchEvent && fetchEvent->scheduled())
189        fetchEvent->deschedule();
190}
191
192
193void
194TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
195{
196    BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
197
198    // if any of this CPU's ThreadContexts are active, mark the CPU as
199    // running and schedule its tick event.
200    for (int i = 0; i < threadContexts.size(); ++i) {
201        ThreadContext *tc = threadContexts[i];
202        if (tc->status() == ThreadContext::Active && _status != Running) {
203            _status = Running;
204            break;
205        }
206    }
207
208    if (_status != Running) {
209        _status = Idle;
210    }
211    assert(threadContexts.size() == 1);
212    cpuId = tc->readCpuId();
213    previousTick = curTick;
214}
215
216
217void
218TimingSimpleCPU::activateContext(int thread_num, int delay)
219{
220    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
221
222    assert(thread_num == 0);
223    assert(thread);
224
225    assert(_status == Idle);
226
227    notIdleFraction++;
228    _status = Running;
229
230    // kick things off by initiating the fetch of the next instruction
231    fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
232}
233
234
235void
236TimingSimpleCPU::suspendContext(int thread_num)
237{
238    DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
239
240    assert(thread_num == 0);
241    assert(thread);
242
243    assert(_status == Running);
244
245    // just change status to Idle... if status != Running,
246    // completeInst() will not initiate fetch of next instruction.
247
248    notIdleFraction--;
249    _status = Idle;
250}
251
252
253template <class T>
254Fault
255TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
256{
257    Request *req =
258        new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
259                    cpuId, /* thread ID */ 0);
260
261    if (traceData) {
262        traceData->setAddr(req->getVaddr());
263    }
264
265   // translate to physical address
266    Fault fault = thread->translateDataReadReq(req);
267
268    // Now do the access.
269    if (fault == NoFault) {
270        PacketPtr pkt =
271            new Packet(req,
272                       (req->isLocked() ?
273                        MemCmd::LoadLockedReq : MemCmd::ReadReq),
274                       Packet::Broadcast);
275        pkt->dataDynamic<T>(new T);
276
277        if (req->isMmapedIpr()) {
278            Tick delay;
279            delay = TheISA::handleIprRead(thread->getTC(), pkt);
280            new IprEvent(pkt, this, nextCycle(curTick + delay));
281            _status = DcacheWaitResponse;
282            dcache_pkt = NULL;
283        } else if (!dcachePort.sendTiming(pkt)) {
284            _status = DcacheRetry;
285            dcache_pkt = pkt;
286        } else {
287            _status = DcacheWaitResponse;
288            // memory system takes ownership of packet
289            dcache_pkt = NULL;
290        }
291
292        // This will need a new way to tell if it has a dcache attached.
293        if (req->isUncacheable())
294            recordEvent("Uncached Read");
295    } else {
296        delete req;
297    }
298
299    return fault;
300}
301
302Fault
303TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
304        int size, unsigned flags)
305{
306    Request *req =
307        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
308
309    if (traceData) {
310        traceData->setAddr(vaddr);
311    }
312
313    Fault fault = thread->translateDataWriteReq(req);
314
315    if (fault == NoFault)
316        paddr = req->getPaddr();
317
318    delete req;
319    return fault;
320}
321
322#ifndef DOXYGEN_SHOULD_SKIP_THIS
323
324template
325Fault
326TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
327
328template
329Fault
330TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
331
332template
333Fault
334TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
335
336template
337Fault
338TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
339
340template
341Fault
342TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
343
344template
345Fault
346TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
347
348#endif //DOXYGEN_SHOULD_SKIP_THIS
349
350template<>
351Fault
352TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
353{
354    return read(addr, *(uint64_t*)&data, flags);
355}
356
357template<>
358Fault
359TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
360{
361    return read(addr, *(uint32_t*)&data, flags);
362}
363
364
365template<>
366Fault
367TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
368{
369    return read(addr, (uint32_t&)data, flags);
370}
371
372
373template <class T>
374Fault
375TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
376{
377    Request *req =
378        new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
379                    cpuId, /* thread ID */ 0);
380
381    if (traceData) {
382        traceData->setAddr(req->getVaddr());
383    }
384
385    // translate to physical address
386    Fault fault = thread->translateDataWriteReq(req);
387
388    // Now do the access.
389    if (fault == NoFault) {
390        MemCmd cmd = MemCmd::WriteReq; // default
391        bool do_access = true;  // flag to suppress cache access
392
393        if (req->isLocked()) {
394            cmd = MemCmd::StoreCondReq;
395            do_access = TheISA::handleLockedWrite(thread, req);
396        } else if (req->isSwap()) {
397            cmd = MemCmd::SwapReq;
398            if (req->isCondSwap()) {
399                assert(res);
400                req->setExtraData(*res);
401            }
402        }
403
404        // Note: need to allocate dcache_pkt even if do_access is
405        // false, as it's used unconditionally to call completeAcc().
406        assert(dcache_pkt == NULL);
407        dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
408        dcache_pkt->allocate();
409        dcache_pkt->set(data);
410
411        if (do_access) {
412            if (req->isMmapedIpr()) {
413                Tick delay;
414                dcache_pkt->set(htog(data));
415                delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
416                new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
417                _status = DcacheWaitResponse;
418                dcache_pkt = NULL;
419            } else if (!dcachePort.sendTiming(dcache_pkt)) {
420                _status = DcacheRetry;
421            } else {
422                _status = DcacheWaitResponse;
423                // memory system takes ownership of packet
424                dcache_pkt = NULL;
425            }
426        }
427        // This will need a new way to tell if it's hooked up to a cache or not.
428        if (req->isUncacheable())
429            recordEvent("Uncached Write");
430    } else {
431        delete req;
432    }
433
434
435    // If the write needs to have a fault on the access, consider calling
436    // changeStatus() and changing it to "bad addr write" or something.
437    return fault;
438}
439
440Fault
441TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
442        int size, unsigned flags)
443{
444    Request *req =
445        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
446
447    if (traceData) {
448        traceData->setAddr(vaddr);
449    }
450
451    Fault fault = thread->translateDataWriteReq(req);
452
453    if (fault == NoFault)
454        paddr = req->getPaddr();
455
456    delete req;
457    return fault;
458}
459
460
461#ifndef DOXYGEN_SHOULD_SKIP_THIS
462template
463Fault
464TimingSimpleCPU::write(Twin32_t data, Addr addr,
465                       unsigned flags, uint64_t *res);
466
467template
468Fault
469TimingSimpleCPU::write(Twin64_t data, Addr addr,
470                       unsigned flags, uint64_t *res);
471
472template
473Fault
474TimingSimpleCPU::write(uint64_t data, Addr addr,
475                       unsigned flags, uint64_t *res);
476
477template
478Fault
479TimingSimpleCPU::write(uint32_t data, Addr addr,
480                       unsigned flags, uint64_t *res);
481
482template
483Fault
484TimingSimpleCPU::write(uint16_t data, Addr addr,
485                       unsigned flags, uint64_t *res);
486
487template
488Fault
489TimingSimpleCPU::write(uint8_t data, Addr addr,
490                       unsigned flags, uint64_t *res);
491
492#endif //DOXYGEN_SHOULD_SKIP_THIS
493
494template<>
495Fault
496TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
497{
498    return write(*(uint64_t*)&data, addr, flags, res);
499}
500
501template<>
502Fault
503TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
504{
505    return write(*(uint32_t*)&data, addr, flags, res);
506}
507
508
509template<>
510Fault
511TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
512{
513    return write((uint32_t)data, addr, flags, res);
514}
515
516
517void
518TimingSimpleCPU::fetch()
519{
520    DPRINTF(SimpleCPU, "Fetch\n");
521
522    if (!curStaticInst || !curStaticInst->isDelayedCommit())
523        checkForInterrupts();
524
525    checkPcEventQueue();
526
527    Request *ifetch_req = new Request();
528    ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
529    Fault fault = setupFetchRequest(ifetch_req);
530
531    ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
532    ifetch_pkt->dataStatic(&inst);
533
534    if (fault == NoFault) {
535        if (!icachePort.sendTiming(ifetch_pkt)) {
536            // Need to wait for retry
537            _status = IcacheRetry;
538        } else {
539            // Need to wait for cache to respond
540            _status = IcacheWaitResponse;
541            // ownership of packet transferred to memory system
542            ifetch_pkt = NULL;
543        }
544    } else {
545        delete ifetch_req;
546        delete ifetch_pkt;
547        // fetch fault: advance directly to next instruction (fault handler)
548        advanceInst(fault);
549    }
550
551    numCycles += tickToCycles(curTick - previousTick);
552    previousTick = curTick;
553}
554
555
556void
557TimingSimpleCPU::advanceInst(Fault fault)
558{
559    advancePC(fault);
560
561    if (_status == Running) {
562        // kick off fetch of next instruction... callback from icache
563        // response will cause that instruction to be executed,
564        // keeping the CPU running.
565        fetch();
566    }
567}
568
569
570void
571TimingSimpleCPU::completeIfetch(PacketPtr pkt)
572{
573    DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
574
575    // received a response from the icache: execute the received
576    // instruction
577    assert(!pkt->isError());
578    assert(_status == IcacheWaitResponse);
579
580    _status = Running;
581
582    numCycles += tickToCycles(curTick - previousTick);
583    previousTick = curTick;
584
585    if (getState() == SimObject::Draining) {
586        delete pkt->req;
587        delete pkt;
588
589        completeDrain();
590        return;
591    }
592
593    preExecute();
594    if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
595        // load or store: just send to dcache
596        Fault fault = curStaticInst->initiateAcc(this, traceData);
597        if (_status != Running) {
598            // instruction will complete in dcache response callback
599            assert(_status == DcacheWaitResponse || _status == DcacheRetry);
600            assert(fault == NoFault);
601        } else {
602            if (fault == NoFault) {
603                // Note that ARM can have NULL packets if the instruction gets
604                // squashed due to predication
605                // early fail on store conditional: complete now
606                assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
607
608                fault = curStaticInst->completeAcc(dcache_pkt, this,
609                                                   traceData);
610                if (dcache_pkt != NULL)
611                {
612                    delete dcache_pkt->req;
613                    delete dcache_pkt;
614                    dcache_pkt = NULL;
615                }
616
617                // keep an instruction count
618                if (fault == NoFault)
619                    countInst();
620            } else if (traceData) {
621                // If there was a fault, we shouldn't trace this instruction.
622                delete traceData;
623                traceData = NULL;
624            }
625
626            postExecute();
627            // @todo remove me after debugging with legion done
628            if (curStaticInst && (!curStaticInst->isMicroop() ||
629                        curStaticInst->isFirstMicroop()))
630                instCnt++;
631            advanceInst(fault);
632        }
633    } else {
634        // non-memory instruction: execute completely now
635        Fault fault = curStaticInst->execute(this, traceData);
636
637        // keep an instruction count
638        if (fault == NoFault)
639            countInst();
640        else if (traceData) {
641            // If there was a fault, we shouldn't trace this instruction.
642            delete traceData;
643            traceData = NULL;
644        }
645
646        postExecute();
647        // @todo remove me after debugging with legion done
648        if (curStaticInst && (!curStaticInst->isMicroop() ||
649                    curStaticInst->isFirstMicroop()))
650            instCnt++;
651        advanceInst(fault);
652    }
653
654    delete pkt->req;
655    delete pkt;
656}
657
658void
659TimingSimpleCPU::IcachePort::ITickEvent::process()
660{
661    cpu->completeIfetch(pkt);
662}
663
664bool
665TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
666{
667    if (pkt->isResponse() && !pkt->wasNacked()) {
668        // delay processing of returned data until next CPU clock edge
669        Tick next_tick = cpu->nextCycle(curTick);
670
671        if (next_tick == curTick)
672            cpu->completeIfetch(pkt);
673        else
674            tickEvent.schedule(pkt, next_tick);
675
676        return true;
677    }
678    else if (pkt->wasNacked()) {
679        assert(cpu->_status == IcacheWaitResponse);
680        pkt->reinitNacked();
681        if (!sendTiming(pkt)) {
682            cpu->_status = IcacheRetry;
683            cpu->ifetch_pkt = pkt;
684        }
685    }
686    //Snooping a Coherence Request, do nothing
687    return true;
688}
689
690void
691TimingSimpleCPU::IcachePort::recvRetry()
692{
693    // we shouldn't get a retry unless we have a packet that we're
694    // waiting to transmit
695    assert(cpu->ifetch_pkt != NULL);
696    assert(cpu->_status == IcacheRetry);
697    PacketPtr tmp = cpu->ifetch_pkt;
698    if (sendTiming(tmp)) {
699        cpu->_status = IcacheWaitResponse;
700        cpu->ifetch_pkt = NULL;
701    }
702}
703
704void
705TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
706{
707    // received a response from the dcache: complete the load or store
708    // instruction
709    assert(!pkt->isError());
710    assert(_status == DcacheWaitResponse);
711    _status = Running;
712
713    numCycles += tickToCycles(curTick - previousTick);
714    previousTick = curTick;
715
716    Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
717
718    // keep an instruction count
719    if (fault == NoFault)
720        countInst();
721    else if (traceData) {
722        // If there was a fault, we shouldn't trace this instruction.
723        delete traceData;
724        traceData = NULL;
725    }
726
727    if (pkt->isRead() && pkt->isLocked()) {
728        TheISA::handleLockedRead(thread, pkt->req);
729    }
730
731    delete pkt->req;
732    delete pkt;
733
734    postExecute();
735
736    if (getState() == SimObject::Draining) {
737        advancePC(fault);
738        completeDrain();
739
740        return;
741    }
742
743    advanceInst(fault);
744}
745
746
747void
748TimingSimpleCPU::completeDrain()
749{
750    DPRINTF(Config, "Done draining\n");
751    changeState(SimObject::Drained);
752    drainEvent->process();
753}
754
755void
756TimingSimpleCPU::DcachePort::setPeer(Port *port)
757{
758    Port::setPeer(port);
759
760#if FULL_SYSTEM
761    // Update the ThreadContext's memory ports (Functional/Virtual
762    // Ports)
763    cpu->tcBase()->connectMemPorts();
764#endif
765}
766
767bool
768TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
769{
770    if (pkt->isResponse() && !pkt->wasNacked()) {
771        // delay processing of returned data until next CPU clock edge
772        Tick next_tick = cpu->nextCycle(curTick);
773
774        if (next_tick == curTick)
775            cpu->completeDataAccess(pkt);
776        else
777            tickEvent.schedule(pkt, next_tick);
778
779        return true;
780    }
781    else if (pkt->wasNacked()) {
782        assert(cpu->_status == DcacheWaitResponse);
783        pkt->reinitNacked();
784        if (!sendTiming(pkt)) {
785            cpu->_status = DcacheRetry;
786            cpu->dcache_pkt = pkt;
787        }
788    }
789    //Snooping a Coherence Request, do nothing
790    return true;
791}
792
793void
794TimingSimpleCPU::DcachePort::DTickEvent::process()
795{
796    cpu->completeDataAccess(pkt);
797}
798
799void
800TimingSimpleCPU::DcachePort::recvRetry()
801{
802    // we shouldn't get a retry unless we have a packet that we're
803    // waiting to transmit
804    assert(cpu->dcache_pkt != NULL);
805    assert(cpu->_status == DcacheRetry);
806    PacketPtr tmp = cpu->dcache_pkt;
807    if (sendTiming(tmp)) {
808        cpu->_status = DcacheWaitResponse;
809        // memory system takes ownership of packet
810        cpu->dcache_pkt = NULL;
811    }
812}
813
814TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
815    : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
816{
817    schedule(t);
818}
819
820void
821TimingSimpleCPU::IprEvent::process()
822{
823    cpu->completeDataAccess(pkt);
824}
825
826const char *
827TimingSimpleCPU::IprEvent::description() const
828{
829    return "Timing Simple CPU Delay IPR event";
830}
831
832
833void
834TimingSimpleCPU::printAddr(Addr a)
835{
836    dcachePort.printAddr(a);
837}
838
839
840////////////////////////////////////////////////////////////////////////
841//
842//  TimingSimpleCPU Simulation Object
843//
844TimingSimpleCPU *
845TimingSimpleCPUParams::create()
846{
847    TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
848    params->name = name;
849    params->numberOfThreads = 1;
850    params->max_insts_any_thread = max_insts_any_thread;
851    params->max_insts_all_threads = max_insts_all_threads;
852    params->max_loads_any_thread = max_loads_any_thread;
853    params->max_loads_all_threads = max_loads_all_threads;
854    params->progress_interval = progress_interval;
855    params->deferRegistration = defer_registration;
856    params->clock = clock;
857    params->phase = phase;
858    params->functionTrace = function_trace;
859    params->functionTraceStart = function_trace_start;
860    params->system = system;
861    params->cpu_id = cpu_id;
862    params->tracer = tracer;
863
864    params->itb = itb;
865    params->dtb = dtb;
866#if FULL_SYSTEM
867    params->profile = profile;
868    params->do_quiesce = do_quiesce;
869    params->do_checkpoint_insts = do_checkpoint_insts;
870    params->do_statistics_insts = do_statistics_insts;
871#else
872    if (workload.size() != 1)
873        panic("only one workload allowed");
874    params->process = workload[0];
875#endif
876
877    TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
878    return cpu;
879}
880