timing.cc revision 3172:2c84db071850
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" 32#include "arch/utility.hh" 33#include "cpu/exetrace.hh" 34#include "cpu/simple/timing.hh" 35#include "mem/packet_impl.hh" 36#include "sim/builder.hh" 37#include "sim/system.hh" 38 39using namespace std; 40using namespace TheISA; 41 42Port * 43TimingSimpleCPU::getPort(const std::string &if_name, int idx) 44{ 45 if (if_name == "dcache_port") 46 return &dcachePort; 47 else if (if_name == "icache_port") 48 return &icachePort; 49 else 50 panic("No Such Port\n"); 51} 52 53void 54TimingSimpleCPU::init() 55{ 56 BaseCPU::init(); 57#if FULL_SYSTEM 58 for (int i = 0; i < threadContexts.size(); ++i) { 59 ThreadContext *tc = threadContexts[i]; 60 61 // initialize CPU, including PC 62 TheISA::initCPU(tc, tc->readCpuId()); 63 } 64#endif 65} 66 67Tick 68TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt) 69{ 70 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); 71 return curTick; 72} 73 74void 75TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt) 76{ 77 panic("TimingSimpleCPU doesn't expect recvFunctional callback!"); 78} 79 80void 81TimingSimpleCPU::CpuPort::recvStatusChange(Status status) 82{ 83 if (status == RangeChange) 84 return; 85 86 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); 87} 88 89 90void 91TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t) 92{ 93 pkt = _pkt; 94 Event::schedule(t); 95} 96 97TimingSimpleCPU::TimingSimpleCPU(Params *p) 98 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock), 99 cpu_id(p->cpu_id) 100{ 101 _status = Idle; 102 ifetch_pkt = dcache_pkt = NULL; 103 drainEvent = NULL; 104 fetchEvent = NULL; 105 changeState(SimObject::Running); 106} 107 108 109TimingSimpleCPU::~TimingSimpleCPU() 110{ 111} 112 113void 114TimingSimpleCPU::serialize(ostream &os) 115{ 116 SimObject::State so_state = SimObject::getState(); 117 SERIALIZE_ENUM(so_state); 118 BaseSimpleCPU::serialize(os); 119} 120 121void 122TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 123{ 124 SimObject::State so_state; 125 UNSERIALIZE_ENUM(so_state); 126 BaseSimpleCPU::unserialize(cp, section); 127} 128 129unsigned int 130TimingSimpleCPU::drain(Event *drain_event) 131{ 132 // TimingSimpleCPU is ready to drain if it's not waiting for 133 // an access to complete. 134 if (status() == Idle || status() == Running || status() == SwitchedOut) { 135 changeState(SimObject::Drained); 136 return 0; 137 } else { 138 changeState(SimObject::Draining); 139 drainEvent = drain_event; 140 return 1; 141 } 142} 143 144void 145TimingSimpleCPU::resume() 146{ 147 if (_status != SwitchedOut && _status != Idle) { 148 // Delete the old event if it existed. 149 if (fetchEvent) { 150 if (fetchEvent->scheduled()) 151 fetchEvent->deschedule(); 152 153 delete fetchEvent; 154 } 155 156 fetchEvent = 157 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 158 fetchEvent->schedule(curTick); 159 } 160 161 assert(system->getMemoryMode() == System::Timing); 162 changeState(SimObject::Running); 163} 164 165void 166TimingSimpleCPU::switchOut() 167{ 168 assert(status() == Running || status() == Idle); 169 _status = SwitchedOut; 170 171 // If we've been scheduled to resume but are then told to switch out, 172 // we'll need to cancel it. 173 if (fetchEvent && fetchEvent->scheduled()) 174 fetchEvent->deschedule(); 175} 176 177 178void 179TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 180{ 181 BaseCPU::takeOverFrom(oldCPU); 182 183 // if any of this CPU's ThreadContexts are active, mark the CPU as 184 // running and schedule its tick event. 185 for (int i = 0; i < threadContexts.size(); ++i) { 186 ThreadContext *tc = threadContexts[i]; 187 if (tc->status() == ThreadContext::Active && _status != Running) { 188 _status = Running; 189 break; 190 } 191 } 192} 193 194 195void 196TimingSimpleCPU::activateContext(int thread_num, int delay) 197{ 198 assert(thread_num == 0); 199 assert(thread); 200 201 assert(_status == Idle); 202 203 notIdleFraction++; 204 _status = Running; 205 // kick things off by initiating the fetch of the next instruction 206 fetchEvent = 207 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 208 fetchEvent->schedule(curTick + cycles(delay)); 209} 210 211 212void 213TimingSimpleCPU::suspendContext(int thread_num) 214{ 215 assert(thread_num == 0); 216 assert(thread); 217 218 assert(_status == Running); 219 220 // just change status to Idle... if status != Running, 221 // completeInst() will not initiate fetch of next instruction. 222 223 notIdleFraction--; 224 _status = Idle; 225} 226 227 228template <class T> 229Fault 230TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 231{ 232 Request *req = 233 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 234 cpu_id, /* thread ID */ 0); 235 236 if (traceData) { 237 traceData->setAddr(req->getVaddr()); 238 } 239 240 // translate to physical address 241 Fault fault = thread->translateDataReadReq(req); 242 243 // Now do the access. 244 if (fault == NoFault) { 245 Packet *pkt = 246 new Packet(req, Packet::ReadReq, Packet::Broadcast); 247 pkt->dataDynamic<T>(new T); 248 249 if (!dcachePort.sendTiming(pkt)) { 250 _status = DcacheRetry; 251 dcache_pkt = pkt; 252 } else { 253 _status = DcacheWaitResponse; 254 // memory system takes ownership of packet 255 dcache_pkt = NULL; 256 } 257 } 258 259 // This will need a new way to tell if it has a dcache attached. 260 if (req->isUncacheable()) 261 recordEvent("Uncached Read"); 262 263 return fault; 264} 265 266#ifndef DOXYGEN_SHOULD_SKIP_THIS 267 268template 269Fault 270TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 271 272template 273Fault 274TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 275 276template 277Fault 278TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 279 280template 281Fault 282TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 283 284#endif //DOXYGEN_SHOULD_SKIP_THIS 285 286template<> 287Fault 288TimingSimpleCPU::read(Addr addr, double &data, unsigned flags) 289{ 290 return read(addr, *(uint64_t*)&data, flags); 291} 292 293template<> 294Fault 295TimingSimpleCPU::read(Addr addr, float &data, unsigned flags) 296{ 297 return read(addr, *(uint32_t*)&data, flags); 298} 299 300 301template<> 302Fault 303TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 304{ 305 return read(addr, (uint32_t&)data, flags); 306} 307 308 309template <class T> 310Fault 311TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 312{ 313 Request *req = 314 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 315 cpu_id, /* thread ID */ 0); 316 317 // translate to physical address 318 Fault fault = thread->translateDataWriteReq(req); 319 320 // Now do the access. 321 if (fault == NoFault) { 322 assert(dcache_pkt == NULL); 323 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 324 dcache_pkt->allocate(); 325 dcache_pkt->set(data); 326 327 bool do_access = true; // flag to suppress cache access 328 329 if (req->isLocked()) { 330 do_access = TheISA::handleLockedWrite(thread, req); 331 } 332 333 if (do_access) { 334 if (!dcachePort.sendTiming(dcache_pkt)) { 335 _status = DcacheRetry; 336 } else { 337 _status = DcacheWaitResponse; 338 // memory system takes ownership of packet 339 dcache_pkt = NULL; 340 } 341 } 342 } 343 344 // This will need a new way to tell if it's hooked up to a cache or not. 345 if (req->isUncacheable()) 346 recordEvent("Uncached Write"); 347 348 // If the write needs to have a fault on the access, consider calling 349 // changeStatus() and changing it to "bad addr write" or something. 350 return fault; 351} 352 353 354#ifndef DOXYGEN_SHOULD_SKIP_THIS 355template 356Fault 357TimingSimpleCPU::write(uint64_t data, Addr addr, 358 unsigned flags, uint64_t *res); 359 360template 361Fault 362TimingSimpleCPU::write(uint32_t data, Addr addr, 363 unsigned flags, uint64_t *res); 364 365template 366Fault 367TimingSimpleCPU::write(uint16_t data, Addr addr, 368 unsigned flags, uint64_t *res); 369 370template 371Fault 372TimingSimpleCPU::write(uint8_t data, Addr addr, 373 unsigned flags, uint64_t *res); 374 375#endif //DOXYGEN_SHOULD_SKIP_THIS 376 377template<> 378Fault 379TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 380{ 381 return write(*(uint64_t*)&data, addr, flags, res); 382} 383 384template<> 385Fault 386TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 387{ 388 return write(*(uint32_t*)&data, addr, flags, res); 389} 390 391 392template<> 393Fault 394TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 395{ 396 return write((uint32_t)data, addr, flags, res); 397} 398 399 400void 401TimingSimpleCPU::fetch() 402{ 403 checkForInterrupts(); 404 405 Request *ifetch_req = new Request(); 406 ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0); 407 Fault fault = setupFetchRequest(ifetch_req); 408 409 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 410 ifetch_pkt->dataStatic(&inst); 411 412 if (fault == NoFault) { 413 if (!icachePort.sendTiming(ifetch_pkt)) { 414 // Need to wait for retry 415 _status = IcacheRetry; 416 } else { 417 // Need to wait for cache to respond 418 _status = IcacheWaitResponse; 419 // ownership of packet transferred to memory system 420 ifetch_pkt = NULL; 421 } 422 } else { 423 // fetch fault: advance directly to next instruction (fault handler) 424 advanceInst(fault); 425 } 426} 427 428 429void 430TimingSimpleCPU::advanceInst(Fault fault) 431{ 432 advancePC(fault); 433 434 if (_status == Running) { 435 // kick off fetch of next instruction... callback from icache 436 // response will cause that instruction to be executed, 437 // keeping the CPU running. 438 fetch(); 439 } 440} 441 442 443void 444TimingSimpleCPU::completeIfetch(Packet *pkt) 445{ 446 // received a response from the icache: execute the received 447 // instruction 448 assert(pkt->result == Packet::Success); 449 assert(_status == IcacheWaitResponse); 450 451 _status = Running; 452 453 delete pkt->req; 454 delete pkt; 455 456 if (getState() == SimObject::Draining) { 457 completeDrain(); 458 return; 459 } 460 461 preExecute(); 462 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 463 // load or store: just send to dcache 464 Fault fault = curStaticInst->initiateAcc(this, traceData); 465 if (_status != Running) { 466 // instruction will complete in dcache response callback 467 assert(_status == DcacheWaitResponse || _status == DcacheRetry); 468 assert(fault == NoFault); 469 } else { 470 if (fault == NoFault) { 471 // early fail on store conditional: complete now 472 assert(dcache_pkt != NULL); 473 fault = curStaticInst->completeAcc(dcache_pkt, this, 474 traceData); 475 delete dcache_pkt->req; 476 delete dcache_pkt; 477 dcache_pkt = NULL; 478 } 479 postExecute(); 480 advanceInst(fault); 481 } 482 } else { 483 // non-memory instruction: execute completely now 484 Fault fault = curStaticInst->execute(this, traceData); 485 postExecute(); 486 advanceInst(fault); 487 } 488} 489 490void 491TimingSimpleCPU::IcachePort::ITickEvent::process() 492{ 493 cpu->completeIfetch(pkt); 494} 495 496bool 497TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 498{ 499 // delay processing of returned data until next CPU clock edge 500 Tick time = pkt->req->getTime(); 501 while (time < curTick) 502 time += lat; 503 504 if (time == curTick) 505 cpu->completeIfetch(pkt); 506 else 507 tickEvent.schedule(pkt, time); 508 509 return true; 510} 511 512void 513TimingSimpleCPU::IcachePort::recvRetry() 514{ 515 // we shouldn't get a retry unless we have a packet that we're 516 // waiting to transmit 517 assert(cpu->ifetch_pkt != NULL); 518 assert(cpu->_status == IcacheRetry); 519 Packet *tmp = cpu->ifetch_pkt; 520 if (sendTiming(tmp)) { 521 cpu->_status = IcacheWaitResponse; 522 cpu->ifetch_pkt = NULL; 523 } 524} 525 526void 527TimingSimpleCPU::completeDataAccess(Packet *pkt) 528{ 529 // received a response from the dcache: complete the load or store 530 // instruction 531 assert(pkt->result == Packet::Success); 532 assert(_status == DcacheWaitResponse); 533 _status = Running; 534 535 if (getState() == SimObject::Draining) { 536 completeDrain(); 537 538 delete pkt->req; 539 delete pkt; 540 541 return; 542 } 543 544 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 545 546 if (pkt->isRead() && pkt->req->isLocked()) { 547 TheISA::handleLockedRead(thread, pkt->req); 548 } 549 550 delete pkt->req; 551 delete pkt; 552 553 postExecute(); 554 advanceInst(fault); 555} 556 557 558void 559TimingSimpleCPU::completeDrain() 560{ 561 DPRINTF(Config, "Done draining\n"); 562 changeState(SimObject::Drained); 563 drainEvent->process(); 564} 565 566bool 567TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 568{ 569 // delay processing of returned data until next CPU clock edge 570 Tick time = pkt->req->getTime(); 571 while (time < curTick) 572 time += lat; 573 574 if (time == curTick) 575 cpu->completeDataAccess(pkt); 576 else 577 tickEvent.schedule(pkt, time); 578 579 return true; 580} 581 582void 583TimingSimpleCPU::DcachePort::DTickEvent::process() 584{ 585 cpu->completeDataAccess(pkt); 586} 587 588void 589TimingSimpleCPU::DcachePort::recvRetry() 590{ 591 // we shouldn't get a retry unless we have a packet that we're 592 // waiting to transmit 593 assert(cpu->dcache_pkt != NULL); 594 assert(cpu->_status == DcacheRetry); 595 Packet *tmp = cpu->dcache_pkt; 596 if (sendTiming(tmp)) { 597 cpu->_status = DcacheWaitResponse; 598 // memory system takes ownership of packet 599 cpu->dcache_pkt = NULL; 600 } 601} 602 603 604//////////////////////////////////////////////////////////////////////// 605// 606// TimingSimpleCPU Simulation Object 607// 608BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 609 610 Param<Counter> max_insts_any_thread; 611 Param<Counter> max_insts_all_threads; 612 Param<Counter> max_loads_any_thread; 613 Param<Counter> max_loads_all_threads; 614 Param<Tick> progress_interval; 615 SimObjectParam<MemObject *> mem; 616 SimObjectParam<System *> system; 617 Param<int> cpu_id; 618 619#if FULL_SYSTEM 620 SimObjectParam<AlphaITB *> itb; 621 SimObjectParam<AlphaDTB *> dtb; 622 Param<Tick> profile; 623#else 624 SimObjectParam<Process *> workload; 625#endif // FULL_SYSTEM 626 627 Param<int> clock; 628 629 Param<bool> defer_registration; 630 Param<int> width; 631 Param<bool> function_trace; 632 Param<Tick> function_trace_start; 633 Param<bool> simulate_stalls; 634 635END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 636 637BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 638 639 INIT_PARAM(max_insts_any_thread, 640 "terminate when any thread reaches this inst count"), 641 INIT_PARAM(max_insts_all_threads, 642 "terminate when all threads have reached this inst count"), 643 INIT_PARAM(max_loads_any_thread, 644 "terminate when any thread reaches this load count"), 645 INIT_PARAM(max_loads_all_threads, 646 "terminate when all threads have reached this load count"), 647 INIT_PARAM(progress_interval, "Progress interval"), 648 INIT_PARAM(mem, "memory"), 649 INIT_PARAM(system, "system object"), 650 INIT_PARAM(cpu_id, "processor ID"), 651 652#if FULL_SYSTEM 653 INIT_PARAM(itb, "Instruction TLB"), 654 INIT_PARAM(dtb, "Data TLB"), 655 INIT_PARAM(profile, ""), 656#else 657 INIT_PARAM(workload, "processes to run"), 658#endif // FULL_SYSTEM 659 660 INIT_PARAM(clock, "clock speed"), 661 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 662 INIT_PARAM(width, "cpu width"), 663 INIT_PARAM(function_trace, "Enable function trace"), 664 INIT_PARAM(function_trace_start, "Cycle to start function trace"), 665 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles") 666 667END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) 668 669 670CREATE_SIM_OBJECT(TimingSimpleCPU) 671{ 672 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params(); 673 params->name = getInstanceName(); 674 params->numberOfThreads = 1; 675 params->max_insts_any_thread = max_insts_any_thread; 676 params->max_insts_all_threads = max_insts_all_threads; 677 params->max_loads_any_thread = max_loads_any_thread; 678 params->max_loads_all_threads = max_loads_all_threads; 679 params->progress_interval = progress_interval; 680 params->deferRegistration = defer_registration; 681 params->clock = clock; 682 params->functionTrace = function_trace; 683 params->functionTraceStart = function_trace_start; 684 params->mem = mem; 685 params->system = system; 686 params->cpu_id = cpu_id; 687 688#if FULL_SYSTEM 689 params->itb = itb; 690 params->dtb = dtb; 691 params->profile = profile; 692#else 693 params->process = workload; 694#endif 695 696 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 697 return cpu; 698} 699 700REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 701 702